Commit | Line | Data |
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4b17244c CM |
1 | #ifndef __ASMARM_ARCH_SCU_H |
2 | #define __ASMARM_ARCH_SCU_H | |
3 | ||
292ec42a RK |
4 | #define SCU_PM_NORMAL 0 |
5 | #define SCU_PM_DORMANT 2 | |
6 | #define SCU_PM_POWEROFF 3 | |
7 | ||
8 | #ifndef __ASSEMBLER__ | |
e9d6b335 HD |
9 | |
10 | #include <asm/cputype.h> | |
11 | ||
12 | static inline bool scu_a9_has_base(void) | |
13 | { | |
af040ffc | 14 | return read_cpuid_part() == ARM_CPU_PART_CORTEX_A9; |
e9d6b335 HD |
15 | } |
16 | ||
17 | static inline unsigned long scu_a9_get_base(void) | |
18 | { | |
19 | unsigned long pa; | |
20 | ||
21 | asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa)); | |
22 | ||
23 | return pa; | |
24 | } | |
25 | ||
2abc75a8 | 26 | #ifdef CONFIG_HAVE_ARM_SCU |
a8cbcd92 | 27 | unsigned int scu_get_core_count(void __iomem *); |
292ec42a | 28 | int scu_power_mode(void __iomem *, unsigned int); |
2abc75a8 NM |
29 | #else |
30 | static inline unsigned int scu_get_core_count(void __iomem *scu_base) | |
31 | { | |
32 | return 0; | |
33 | } | |
34 | static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode) | |
35 | { | |
36 | return -EINVAL; | |
37 | } | |
38 | #endif | |
eed88123 | 39 | |
2abc75a8 | 40 | #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU) |
eed88123 RH |
41 | void scu_enable(void __iomem *scu_base); |
42 | #else | |
43 | static inline void scu_enable(void __iomem *scu_base) {} | |
44 | #endif | |
45 | ||
292ec42a | 46 | #endif |
4b17244c CM |
47 | |
48 | #endif |