[deliverable/linux.git] / arch / arm / include / asm / system.h

#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H

#ifdef __KERNEL__

#define CPU_ARCH_UNKNOWN	0
#define CPU_ARCH_ARMv3		1
#define CPU_ARCH_ARMv4		2
#define CPU_ARCH_ARMv4T		3
#define CPU_ARCH_ARMv5		4
#define CPU_ARCH_ARMv5T		5
#define CPU_ARCH_ARMv5TE	6
#define CPU_ARCH_ARMv5TEJ	7
#define CPU_ARCH_ARMv6		8
#define CPU_ARCH_ARMv7		9

/*
 * CR1 bits (CP#15 CR1)
 */
#define CR_M	(1 << 0)	/* MMU enable				*/
#define CR_A	(1 << 1)	/* Alignment abort enable		*/
#define CR_C	(1 << 2)	/* Dcache enable			*/
#define CR_W	(1 << 3)	/* Write buffer enable			*/
#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
#define CR_D	(1 << 5)	/* 32-bit data address range		*/
#define CR_L	(1 << 6)	/* Implementation defined		*/
#define CR_B	(1 << 7)	/* Big endian				*/
#define CR_S	(1 << 8)	/* System MMU protection		*/
#define CR_R	(1 << 9)	/* ROM MMU protection			*/
#define CR_F	(1 << 10)	/* Implementation defined		*/
#define CR_Z	(1 << 11)	/* Implementation defined		*/
#define CR_I	(1 << 12)	/* Icache enable			*/
#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
#define CR_DT	(1 << 16)
#define CR_IT	(1 << 18)
#define CR_ST	(1 << 19)
#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
#define CR_U	(1 << 22)	/* Unaligned access operation		*/
#define CR_XP	(1 << 23)	/* Extended page tables			*/
#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
#define CR_AFE	(1 << 29)	/* Access flag enable			*/
#define CR_TE	(1 << 30)	/* Thumb exception enable		*/

/*
 * This is used to ensure the compiler did actually allocate the register we
 * asked it for some inline assembly sequences.  Apparently we can't trust
 * the compiler from one version to another so a bit of paranoia won't hurt.
 * This string is meant to be concatenated with the inline asm string and
 * will cause compilation to stop on mismatch.
 * (for details, see gcc PR 15089)
 */
#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"

#ifndef __ASSEMBLY__

#include <linux/linkage.h>
#include <linux/irqflags.h>

#define __exception	__attribute__((section(".exception.text")))

struct thread_info;
struct task_struct;

/* information about the system we're running on */
extern unsigned int system_rev;
extern unsigned int system_serial_low;
extern unsigned int system_serial_high;
extern unsigned int mem_fclk_21285;

struct pt_regs;

void die(const char *msg, struct pt_regs *regs, int err)
		__attribute__((noreturn));

struct siginfo;
void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
		unsigned long err, unsigned long trap);

void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
				       struct pt_regs *),
		     int sig, const char *name);

#define xchg(ptr,x) \
	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))

extern asmlinkage void __backtrace(void);
extern asmlinkage void c_backtrace(unsigned long fp, int pmode);

struct mm_struct;
extern void show_pte(struct mm_struct *mm, unsigned long addr);
extern void __show_regs(struct pt_regs *);

extern int cpu_architecture(void);
extern void cpu_init(void);

void arm_machine_restart(char mode, const char *cmd);
extern void (*arm_pm_restart)(char str, const char *cmd);

#define UDBG_UNDEFINED	(1 << 0)
#define UDBG_SYSCALL	(1 << 1)
#define UDBG_BADABORT	(1 << 2)
#define UDBG_SEGV	(1 << 3)
#define UDBG_BUS	(1 << 4)

extern unsigned int user_debug;

#if __LINUX_ARM_ARCH__ >= 4
#define vectors_high()	(cr_alignment & CR_V)
#else
#define vectors_high()	(0)
#endif

#if __LINUX_ARM_ARCH__ >= 7
#define isb() __asm__ __volatile__ ("isb" : : : "memory")
#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
				    : : "r" (0) : "memory")
#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
				    : : "r" (0) : "memory")
#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
				    : : "r" (0) : "memory")
#elif defined(CONFIG_CPU_FA526)
#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
				    : : "r" (0) : "memory")
#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
				    : : "r" (0) : "memory")
#define dmb() __asm__ __volatile__ ("" : : : "memory")
#else
#define isb() __asm__ __volatile__ ("" : : : "memory")
#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
				    : : "r" (0) : "memory")
#define dmb() __asm__ __volatile__ ("" : : : "memory")
#endif

#ifndef CONFIG_SMP
#define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
#define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
#define wmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
#define smp_mb()	barrier()
#define smp_rmb()	barrier()
#define smp_wmb()	barrier()
#else
#define mb()		dmb()
#define rmb()		dmb()
#define wmb()		dmb()
#define smp_mb()	dmb()
#define smp_rmb()	dmb()
#define smp_wmb()	dmb()
#endif
#define read_barrier_depends()		do { } while(0)
#define smp_read_barrier_depends()	do { } while(0)

#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
extern unsigned long cr_alignment;	/* defined in entry-armv.S */

static inline unsigned int get_cr(void)
{
	unsigned int val;
	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
	return val;
}

static inline void set_cr(unsigned int val)
{
	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
	  : : "r" (val) : "cc");
	isb();
}

#ifndef CONFIG_SMP
extern void adjust_cr(unsigned long mask, unsigned long set);
#endif

#define CPACC_FULL(n)		(3 << (n * 2))
#define CPACC_SVC(n)		(1 << (n * 2))
#define CPACC_DISABLE(n)	(0 << (n * 2))

static inline unsigned int get_copro_access(void)
{
	unsigned int val;
	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
	  : "=r" (val) : : "cc");
	return val;
}

static inline void set_copro_access(unsigned int val)
{
	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
	  : : "r" (val) : "cc");
	isb();
}

/*
 * switch_mm() may do a full cache flush over the context switch,
 * so enable interrupts over the context switch to avoid high
 * latency.
 */
#define __ARCH_WANT_INTERRUPTS_ON_CTXSW

/*
 * switch_to(prev, next) should switch from task `prev' to `next'
 * `prev' will never be the same as `next'.  schedule() itself
 * contains the memory barrier to tell GCC not to cache `current'.
 */
extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);

#define switch_to(prev,next,last)					\
do {									\
	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
} while (0)

#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
/*
 * On the StrongARM, "swp" is terminally broken since it bypasses the
 * cache totally.  This means that the cache becomes inconsistent, and,
 * since we use normal loads/stores as well, this is really bad.
 * Typically, this causes oopsen in filp_close, but could have other,
 * more disasterous effects.  There are two work-arounds:
 *  1. Disable interrupts and emulate the atomic swap
 *  2. Clean the cache, perform atomic swap, flush the cache
 *
 * We choose (1) since its the "easiest" to achieve here and is not
 * dependent on the processor type.
 *
 * NOTE that this solution won't work on an SMP system, so explcitly
 * forbid it here.
 */
#define swp_is_buggy
#endif

static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
{
	extern void __bad_xchg(volatile void *, int);
	unsigned long ret;
#ifdef swp_is_buggy
	unsigned long flags;
#endif
#if __LINUX_ARM_ARCH__ >= 6
	unsigned int tmp;
#endif

	smp_mb();

	switch (size) {
#if __LINUX_ARM_ARCH__ >= 6
	case 1:
		asm volatile("@	__xchg1\n"
		"1:	ldrexb	%0, [%3]\n"
		"	strexb	%1, %2, [%3]\n"
		"	teq	%1, #0\n"
		"	bne	1b"
			: "=&r" (ret), "=&r" (tmp)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
	case 4:
		asm volatile("@	__xchg4\n"
		"1:	ldrex	%0, [%3]\n"
		"	strex	%1, %2, [%3]\n"
		"	teq	%1, #0\n"
		"	bne	1b"
			: "=&r" (ret), "=&r" (tmp)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
#elif defined(swp_is_buggy)
#ifdef CONFIG_SMP
#error SMP is not supported on this platform
#endif
	case 1:
		raw_local_irq_save(flags);
		ret = *(volatile unsigned char *)ptr;
		*(volatile unsigned char *)ptr = x;
		raw_local_irq_restore(flags);
		break;

	case 4:
		raw_local_irq_save(flags);
		ret = *(volatile unsigned long *)ptr;
		*(volatile unsigned long *)ptr = x;
		raw_local_irq_restore(flags);
		break;
#else
	case 1:
		asm volatile("@	__xchg1\n"
		"	swpb	%0, %1, [%2]"
			: "=&r" (ret)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
	case 4:
		asm volatile("@	__xchg4\n"
		"	swp	%0, %1, [%2]"
			: "=&r" (ret)
			: "r" (x), "r" (ptr)
			: "memory", "cc");
		break;
#endif
	default:
		__bad_xchg(ptr, size), ret = 0;
		break;
	}
	smp_mb();

	return ret;
}

extern void disable_hlt(void);
extern void enable_hlt(void);

#include <asm-generic/cmpxchg-local.h>

/*
 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 * them available.
 */
#define cmpxchg_local(ptr, o, n)				  	       \
	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
			(unsigned long)(n), sizeof(*(ptr))))
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))

#ifndef CONFIG_SMP
#include <asm-generic/cmpxchg.h>
#endif

#endif /* __ASSEMBLY__ */

#define arch_align_stack(x) (x)

#endif /* __KERNEL__ */

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_ARM_SYSTEM_H
	2	#define __ASM_ARM_SYSTEM_H
	3
	4	#ifdef __KERNEL__
	5
1da177e4 LT	6	#define CPU_ARCH_UNKNOWN 0
	7	#define CPU_ARCH_ARMv3 1
	8	#define CPU_ARCH_ARMv4 2
	9	#define CPU_ARCH_ARMv4T 3
	10	#define CPU_ARCH_ARMv5 4
	11	#define CPU_ARCH_ARMv5T 5
	12	#define CPU_ARCH_ARMv5TE 6
	13	#define CPU_ARCH_ARMv5TEJ 7
	14	#define CPU_ARCH_ARMv6 8
bbe88886	15	#define CPU_ARCH_ARMv7 9
1da177e4 LT	16
	17	/*
	18	* CR1 bits (CP#15 CR1)
	19	*/
	20	#define CR_M (1 << 0) /* MMU enable */
	21	#define CR_A (1 << 1) /* Alignment abort enable */
	22	#define CR_C (1 << 2) /* Dcache enable */
	23	#define CR_W (1 << 3) /* Write buffer enable */
	24	#define CR_P (1 << 4) /* 32-bit exception handler */
	25	#define CR_D (1 << 5) /* 32-bit data address range */
	26	#define CR_L (1 << 6) /* Implementation defined */
	27	#define CR_B (1 << 7) /* Big endian */
	28	#define CR_S (1 << 8) /* System MMU protection */
	29	#define CR_R (1 << 9) /* ROM MMU protection */
	30	#define CR_F (1 << 10) /* Implementation defined */
	31	#define CR_Z (1 << 11) /* Implementation defined */
	32	#define CR_I (1 << 12) /* Icache enable */
	33	#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
	34	#define CR_RR (1 << 14) /* Round Robin cache replacement */
	35	#define CR_L4 (1 << 15) /* LDR pc can set T bit */
	36	#define CR_DT (1 << 16)
	37	#define CR_IT (1 << 18)
	38	#define CR_ST (1 << 19)
	39	#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
	40	#define CR_U (1 << 22) /* Unaligned access operation */
	41	#define CR_XP (1 << 23) /* Extended page tables */
	42	#define CR_VE (1 << 24) /* Vectored interrupts */
b1cce6b1 RK	43	#define CR_EE (1 << 25) /* Exception (Big) Endian */
	44	#define CR_TRE (1 << 28) /* TEX remap enable */
	45	#define CR_AFE (1 << 29) /* Access flag enable */
	46	#define CR_TE (1 << 30) /* Thumb exception enable */
1da177e4	47
1da177e4 LT	48	/*
	49	* This is used to ensure the compiler did actually allocate the register we
	50	* asked it for some inline assembly sequences. Apparently we can't trust
	51	* the compiler from one version to another so a bit of paranoia won't hurt.
	52	* This string is meant to be concatenated with the inline asm string and
	53	* will cause compilation to stop on mismatch.
	54	* (for details, see gcc PR 15089)
	55	*/
	56	#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
	57
	58	#ifndef __ASSEMBLY__
	59
	60	#include <linux/linkage.h>
255d1f86	61	#include <linux/irqflags.h>
1da177e4	62
7ab3f8d5 RK	63	#define __exception __attribute__((section(".exception.text")))
7ab3f8d5 RK	64
1da177e4 LT	65	struct thread_info;
	66	struct task_struct;
	67
	68	/* information about the system we're running on */
	69	extern unsigned int system_rev;
	70	extern unsigned int system_serial_low;
	71	extern unsigned int system_serial_high;
	72	extern unsigned int mem_fclk_21285;
	73
	74	struct pt_regs;
	75
	76	void die(const char msg, struct pt_regs regs, int err)
	77	__attribute__((noreturn));
	78
cfb0810e	79	struct siginfo;
1eeb66a1	80	void arm_notify_die(const char str, struct pt_regs regs, struct siginfo *info,
cfb0810e	81	unsigned long err, unsigned long trap);
1da177e4 LT	82
	83	void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
	84	struct pt_regs *),
	85	int sig, const char *name);
	86
1da177e4 LT	87	#define xchg(ptr,x) \
	88	((__typeof__((ptr)))__xchg((unsigned long)(x),(ptr),sizeof((ptr))))
	89
1da177e4	90	extern asmlinkage void __backtrace(void);
652a12ef	91	extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
5470dc65 RK	92
5470dc65 RK	93	struct mm_struct;
652a12ef RK	94	extern void show_pte(struct mm_struct *mm, unsigned long addr);
652a12ef RK	95	extern void __show_regs(struct pt_regs *);
1da177e4 LT	96
1da177e4 LT	97	extern int cpu_architecture(void);
36c5ed23	98	extern void cpu_init(void);
1da177e4	99
be093beb RK	100	void arm_machine_restart(char mode, const char *cmd);
be093beb RK	101	extern void (arm_pm_restart)(char str, const char cmd);
74617fb6	102
56660faf CM	103	#define UDBG_UNDEFINED (1 << 0)
	104	#define UDBG_SYSCALL (1 << 1)
	105	#define UDBG_BADABORT (1 << 2)
	106	#define UDBG_SEGV (1 << 3)
	107	#define UDBG_BUS (1 << 4)
	108
	109	extern unsigned int user_debug;
	110
	111	#if __LINUX_ARM_ARCH__ >= 4
	112	#define vectors_high() (cr_alignment & CR_V)
	113	#else
	114	#define vectors_high() (0)
	115	#endif
	116
56163fcf CM	117	#if __LINUX_ARM_ARCH__ >= 7
	118	#define isb() __asm__ __volatile__ ("isb" : : : "memory")
	119	#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
	120	#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
	121	#elif defined(CONFIG_CPU_XSC3) \|\| __LINUX_ARM_ARCH__ == 6
56660faf CM	122	#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
	123	: : "r" (0) : "memory")
	124	#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
	125	: : "r" (0) : "memory")
	126	#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
	127	: : "r" (0) : "memory")
28853ac8 PZ	128	#elif defined(CONFIG_CPU_FA526)
	129	#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
	130	: : "r" (0) : "memory")
	131	#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
	132	: : "r" (0) : "memory")
	133	#define dmb() __asm__ __volatile__ ("" : : : "memory")
56660faf CM	134	#else
	135	#define isb() __asm__ __volatile__ ("" : : : "memory")
	136	#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
	137	: : "r" (0) : "memory")
	138	#define dmb() __asm__ __volatile__ ("" : : : "memory")
	139	#endif
9623b373	140
398e692f LB	141	#ifndef CONFIG_SMP
	142	#define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
	143	#define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
	144	#define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
	145	#define smp_mb() barrier()
	146	#define smp_rmb() barrier()
	147	#define smp_wmb() barrier()
9623b373	148	#else
398e692f LB	149	#define mb() dmb()
	150	#define rmb() dmb()
	151	#define wmb() dmb()
	152	#define smp_mb() dmb()
	153	#define smp_rmb() dmb()
	154	#define smp_wmb() dmb()
	155	#endif
	156	#define read_barrier_depends() do { } while(0)
	157	#define smp_read_barrier_depends() do { } while(0)
9623b373 CM	158
9623b373 CM	159	#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
56660faf CM	160	#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
56660faf CM	161
255d1f86 RK	162	extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
	163	extern unsigned long cr_alignment; /* defined in entry-armv.S */
	164
efe90d27 RK	165	static inline unsigned int get_cr(void)
	166	{
	167	unsigned int val;
	168	asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
	169	return val;
	170	}
	171
	172	static inline void set_cr(unsigned int val)
	173	{
	174	asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
	175	: : "r" (val) : "cc");
56660faf	176	isb();
efe90d27 RK	177	}
efe90d27 RK	178
255d1f86 RK	179	#ifndef CONFIG_SMP
	180	extern void adjust_cr(unsigned long mask, unsigned long set);
	181	#endif
	182
efe90d27 RK	183	#define CPACC_FULL(n) (3 << (n * 2))
	184	#define CPACC_SVC(n) (1 << (n * 2))
	185	#define CPACC_DISABLE(n) (0 << (n * 2))
	186
	187	static inline unsigned int get_copro_access(void)
	188	{
	189	unsigned int val;
	190	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
	191	: "=r" (val) : : "cc");
	192	return val;
	193	}
	194
	195	static inline void set_copro_access(unsigned int val)
	196	{
	197	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
	198	: : "r" (val) : "cc");
56660faf	199	isb();
efe90d27	200	}
1da177e4	201
1da177e4	202	/*
4866cde0 NP	203	* switch_mm() may do a full cache flush over the context switch,
	204	* so enable interrupts over the context switch to avoid high
	205	* latency.
1da177e4	206	*/
4866cde0	207	#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
1da177e4 LT	208
	209	/*
	210	* switch_to(prev, next) should switch from task `prev' to `next'
	211	* `prev' will never be the same as `next'. schedule() itself
	212	* contains the memory barrier to tell GCC not to cache `current'.
	213	*/
	214	extern struct task_struct __switch_to(struct task_struct , struct thread_info , struct thread_info );
	215
	216	#define switch_to(prev,next,last) \
	217	do { \
e7c1b32f	218	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
1da177e4 LT	219	} while (0)
1da177e4 LT	220
1da177e4 LT	221	#if defined(CONFIG_CPU_SA1100) \|\| defined(CONFIG_CPU_SA110)
	222	/*
	223	* On the StrongARM, "swp" is terminally broken since it bypasses the
	224	* cache totally. This means that the cache becomes inconsistent, and,
	225	* since we use normal loads/stores as well, this is really bad.
	226	* Typically, this causes oopsen in filp_close, but could have other,
	227	* more disasterous effects. There are two work-arounds:
	228	* 1. Disable interrupts and emulate the atomic swap
	229	* 2. Clean the cache, perform atomic swap, flush the cache
	230	*
	231	* We choose (1) since its the "easiest" to achieve here and is not
	232	* dependent on the processor type.
053a7b5b RK	233	*
	234	* NOTE that this solution won't work on an SMP system, so explcitly
	235	* forbid it here.
1da177e4 LT	236	*/
	237	#define swp_is_buggy
	238	#endif
	239
	240	static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
	241	{
	242	extern void __bad_xchg(volatile void *, int);
	243	unsigned long ret;
	244	#ifdef swp_is_buggy
	245	unsigned long flags;
	246	#endif
9560782f RK	247	#if __LINUX_ARM_ARCH__ >= 6
	248	unsigned int tmp;
	249	#endif
1da177e4	250
bac4e960 RK	251	smp_mb();
bac4e960 RK	252
1da177e4	253	switch (size) {
9560782f RK	254	#if __LINUX_ARM_ARCH__ >= 6
	255	case 1:
	256	asm volatile("@ __xchg1\n"
	257	"1: ldrexb %0, [%3]\n"
	258	" strexb %1, %2, [%3]\n"
	259	" teq %1, #0\n"
	260	" bne 1b"
	261	: "=&r" (ret), "=&r" (tmp)
	262	: "r" (x), "r" (ptr)
	263	: "memory", "cc");
	264	break;
	265	case 4:
	266	asm volatile("@ __xchg4\n"
	267	"1: ldrex %0, [%3]\n"
	268	" strex %1, %2, [%3]\n"
	269	" teq %1, #0\n"
	270	" bne 1b"
	271	: "=&r" (ret), "=&r" (tmp)
	272	: "r" (x), "r" (ptr)
	273	: "memory", "cc");
	274	break;
	275	#elif defined(swp_is_buggy)
	276	#ifdef CONFIG_SMP
	277	#error SMP is not supported on this platform
	278	#endif
	279	case 1:
e7cc2c59	280	raw_local_irq_save(flags);
9560782f RK	281	ret = (volatile unsigned char )ptr;
9560782f RK	282	(volatile unsigned char )ptr = x;
e7cc2c59	283	raw_local_irq_restore(flags);
9560782f RK	284	break;
	285
	286	case 4:
e7cc2c59	287	raw_local_irq_save(flags);
9560782f RK	288	ret = (volatile unsigned long )ptr;
9560782f RK	289	(volatile unsigned long )ptr = x;
e7cc2c59	290	raw_local_irq_restore(flags);
9560782f	291	break;
1da177e4	292	#else
9560782f RK	293	case 1:
	294	asm volatile("@ __xchg1\n"
	295	" swpb %0, %1, [%2]"
	296	: "=&r" (ret)
	297	: "r" (x), "r" (ptr)
	298	: "memory", "cc");
	299	break;
	300	case 4:
	301	asm volatile("@ __xchg4\n"
	302	" swp %0, %1, [%2]"
	303	: "=&r" (ret)
	304	: "r" (x), "r" (ptr)
	305	: "memory", "cc");
	306	break;
1da177e4	307	#endif
9560782f RK	308	default:
	309	__bad_xchg(ptr, size), ret = 0;
	310	break;
1da177e4	311	}
bac4e960	312	smp_mb();
1da177e4 LT	313
	314	return ret;
	315	}
	316
dabaeff0 BD	317	extern void disable_hlt(void);
	318	extern void enable_hlt(void);
	319
176393d4 MD	320	#include <asm-generic/cmpxchg-local.h>
	321
	322	/*
	323	* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
	324	* them available.
	325	*/
	326	#define cmpxchg_local(ptr, o, n) \
	327	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
	328	(unsigned long)(n), sizeof(*(ptr))))
	329	#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
	330
	331	#ifndef CONFIG_SMP
	332	#include <asm-generic/cmpxchg.h>
	333	#endif
	334
1da177e4 LT	335	#endif /* __ASSEMBLY__ */
	336
	337	#define arch_align_stack(x) (x)
	338
	339	#endif /* __KERNEL__ */
	340
	341	#endif