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1da177e4 LT |
1 | #ifndef __ASM_ARM_SYSTEM_H |
2 | #define __ASM_ARM_SYSTEM_H | |
3 | ||
4 | #ifdef __KERNEL__ | |
5 | ||
1da177e4 LT |
6 | #define CPU_ARCH_UNKNOWN 0 |
7 | #define CPU_ARCH_ARMv3 1 | |
8 | #define CPU_ARCH_ARMv4 2 | |
9 | #define CPU_ARCH_ARMv4T 3 | |
10 | #define CPU_ARCH_ARMv5 4 | |
11 | #define CPU_ARCH_ARMv5T 5 | |
12 | #define CPU_ARCH_ARMv5TE 6 | |
13 | #define CPU_ARCH_ARMv5TEJ 7 | |
14 | #define CPU_ARCH_ARMv6 8 | |
bbe88886 | 15 | #define CPU_ARCH_ARMv7 9 |
1da177e4 LT |
16 | |
17 | /* | |
18 | * CR1 bits (CP#15 CR1) | |
19 | */ | |
20 | #define CR_M (1 << 0) /* MMU enable */ | |
21 | #define CR_A (1 << 1) /* Alignment abort enable */ | |
22 | #define CR_C (1 << 2) /* Dcache enable */ | |
23 | #define CR_W (1 << 3) /* Write buffer enable */ | |
24 | #define CR_P (1 << 4) /* 32-bit exception handler */ | |
25 | #define CR_D (1 << 5) /* 32-bit data address range */ | |
26 | #define CR_L (1 << 6) /* Implementation defined */ | |
27 | #define CR_B (1 << 7) /* Big endian */ | |
28 | #define CR_S (1 << 8) /* System MMU protection */ | |
29 | #define CR_R (1 << 9) /* ROM MMU protection */ | |
30 | #define CR_F (1 << 10) /* Implementation defined */ | |
31 | #define CR_Z (1 << 11) /* Implementation defined */ | |
32 | #define CR_I (1 << 12) /* Icache enable */ | |
33 | #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ | |
34 | #define CR_RR (1 << 14) /* Round Robin cache replacement */ | |
35 | #define CR_L4 (1 << 15) /* LDR pc can set T bit */ | |
36 | #define CR_DT (1 << 16) | |
37 | #define CR_IT (1 << 18) | |
38 | #define CR_ST (1 << 19) | |
39 | #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ | |
40 | #define CR_U (1 << 22) /* Unaligned access operation */ | |
41 | #define CR_XP (1 << 23) /* Extended page tables */ | |
42 | #define CR_VE (1 << 24) /* Vectored interrupts */ | |
b1cce6b1 RK |
43 | #define CR_EE (1 << 25) /* Exception (Big) Endian */ |
44 | #define CR_TRE (1 << 28) /* TEX remap enable */ | |
45 | #define CR_AFE (1 << 29) /* Access flag enable */ | |
46 | #define CR_TE (1 << 30) /* Thumb exception enable */ | |
1da177e4 | 47 | |
1da177e4 LT |
48 | /* |
49 | * This is used to ensure the compiler did actually allocate the register we | |
50 | * asked it for some inline assembly sequences. Apparently we can't trust | |
51 | * the compiler from one version to another so a bit of paranoia won't hurt. | |
52 | * This string is meant to be concatenated with the inline asm string and | |
53 | * will cause compilation to stop on mismatch. | |
54 | * (for details, see gcc PR 15089) | |
55 | */ | |
56 | #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" | |
57 | ||
58 | #ifndef __ASSEMBLY__ | |
59 | ||
60 | #include <linux/linkage.h> | |
255d1f86 | 61 | #include <linux/irqflags.h> |
1da177e4 | 62 | |
7ab3f8d5 RK |
63 | #define __exception __attribute__((section(".exception.text"))) |
64 | ||
1da177e4 LT |
65 | struct thread_info; |
66 | struct task_struct; | |
67 | ||
68 | /* information about the system we're running on */ | |
69 | extern unsigned int system_rev; | |
70 | extern unsigned int system_serial_low; | |
71 | extern unsigned int system_serial_high; | |
72 | extern unsigned int mem_fclk_21285; | |
73 | ||
74 | struct pt_regs; | |
75 | ||
76 | void die(const char *msg, struct pt_regs *regs, int err) | |
77 | __attribute__((noreturn)); | |
78 | ||
cfb0810e | 79 | struct siginfo; |
1eeb66a1 | 80 | void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info, |
cfb0810e | 81 | unsigned long err, unsigned long trap); |
1da177e4 LT |
82 | |
83 | void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, | |
84 | struct pt_regs *), | |
85 | int sig, const char *name); | |
86 | ||
1da177e4 LT |
87 | #define xchg(ptr,x) \ |
88 | ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | |
89 | ||
1da177e4 | 90 | extern asmlinkage void __backtrace(void); |
652a12ef | 91 | extern asmlinkage void c_backtrace(unsigned long fp, int pmode); |
5470dc65 RK |
92 | |
93 | struct mm_struct; | |
652a12ef RK |
94 | extern void show_pte(struct mm_struct *mm, unsigned long addr); |
95 | extern void __show_regs(struct pt_regs *); | |
1da177e4 LT |
96 | |
97 | extern int cpu_architecture(void); | |
36c5ed23 | 98 | extern void cpu_init(void); |
1da177e4 | 99 | |
be093beb RK |
100 | void arm_machine_restart(char mode, const char *cmd); |
101 | extern void (*arm_pm_restart)(char str, const char *cmd); | |
74617fb6 | 102 | |
56660faf CM |
103 | #define UDBG_UNDEFINED (1 << 0) |
104 | #define UDBG_SYSCALL (1 << 1) | |
105 | #define UDBG_BADABORT (1 << 2) | |
106 | #define UDBG_SEGV (1 << 3) | |
107 | #define UDBG_BUS (1 << 4) | |
108 | ||
109 | extern unsigned int user_debug; | |
110 | ||
111 | #if __LINUX_ARM_ARCH__ >= 4 | |
112 | #define vectors_high() (cr_alignment & CR_V) | |
113 | #else | |
114 | #define vectors_high() (0) | |
115 | #endif | |
116 | ||
56163fcf CM |
117 | #if __LINUX_ARM_ARCH__ >= 7 |
118 | #define isb() __asm__ __volatile__ ("isb" : : : "memory") | |
119 | #define dsb() __asm__ __volatile__ ("dsb" : : : "memory") | |
120 | #define dmb() __asm__ __volatile__ ("dmb" : : : "memory") | |
121 | #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 | |
56660faf CM |
122 | #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ |
123 | : : "r" (0) : "memory") | |
124 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ | |
125 | : : "r" (0) : "memory") | |
126 | #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ | |
127 | : : "r" (0) : "memory") | |
128 | #else | |
129 | #define isb() __asm__ __volatile__ ("" : : : "memory") | |
130 | #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ | |
131 | : : "r" (0) : "memory") | |
132 | #define dmb() __asm__ __volatile__ ("" : : : "memory") | |
133 | #endif | |
9623b373 | 134 | |
398e692f LB |
135 | #ifndef CONFIG_SMP |
136 | #define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) | |
137 | #define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) | |
138 | #define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0) | |
139 | #define smp_mb() barrier() | |
140 | #define smp_rmb() barrier() | |
141 | #define smp_wmb() barrier() | |
9623b373 | 142 | #else |
398e692f LB |
143 | #define mb() dmb() |
144 | #define rmb() dmb() | |
145 | #define wmb() dmb() | |
146 | #define smp_mb() dmb() | |
147 | #define smp_rmb() dmb() | |
148 | #define smp_wmb() dmb() | |
149 | #endif | |
150 | #define read_barrier_depends() do { } while(0) | |
151 | #define smp_read_barrier_depends() do { } while(0) | |
9623b373 CM |
152 | |
153 | #define set_mb(var, value) do { var = value; smp_mb(); } while (0) | |
56660faf CM |
154 | #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); |
155 | ||
255d1f86 RK |
156 | extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ |
157 | extern unsigned long cr_alignment; /* defined in entry-armv.S */ | |
158 | ||
efe90d27 RK |
159 | static inline unsigned int get_cr(void) |
160 | { | |
161 | unsigned int val; | |
162 | asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); | |
163 | return val; | |
164 | } | |
165 | ||
166 | static inline void set_cr(unsigned int val) | |
167 | { | |
168 | asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" | |
169 | : : "r" (val) : "cc"); | |
56660faf | 170 | isb(); |
efe90d27 RK |
171 | } |
172 | ||
255d1f86 RK |
173 | #ifndef CONFIG_SMP |
174 | extern void adjust_cr(unsigned long mask, unsigned long set); | |
175 | #endif | |
176 | ||
efe90d27 RK |
177 | #define CPACC_FULL(n) (3 << (n * 2)) |
178 | #define CPACC_SVC(n) (1 << (n * 2)) | |
179 | #define CPACC_DISABLE(n) (0 << (n * 2)) | |
180 | ||
181 | static inline unsigned int get_copro_access(void) | |
182 | { | |
183 | unsigned int val; | |
184 | asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access" | |
185 | : "=r" (val) : : "cc"); | |
186 | return val; | |
187 | } | |
188 | ||
189 | static inline void set_copro_access(unsigned int val) | |
190 | { | |
191 | asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access" | |
192 | : : "r" (val) : "cc"); | |
56660faf | 193 | isb(); |
efe90d27 | 194 | } |
1da177e4 | 195 | |
1da177e4 | 196 | /* |
4866cde0 NP |
197 | * switch_mm() may do a full cache flush over the context switch, |
198 | * so enable interrupts over the context switch to avoid high | |
199 | * latency. | |
1da177e4 | 200 | */ |
4866cde0 | 201 | #define __ARCH_WANT_INTERRUPTS_ON_CTXSW |
1da177e4 LT |
202 | |
203 | /* | |
204 | * switch_to(prev, next) should switch from task `prev' to `next' | |
205 | * `prev' will never be the same as `next'. schedule() itself | |
206 | * contains the memory barrier to tell GCC not to cache `current'. | |
207 | */ | |
208 | extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *); | |
209 | ||
210 | #define switch_to(prev,next,last) \ | |
211 | do { \ | |
e7c1b32f | 212 | last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ |
1da177e4 LT |
213 | } while (0) |
214 | ||
1da177e4 LT |
215 | #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) |
216 | /* | |
217 | * On the StrongARM, "swp" is terminally broken since it bypasses the | |
218 | * cache totally. This means that the cache becomes inconsistent, and, | |
219 | * since we use normal loads/stores as well, this is really bad. | |
220 | * Typically, this causes oopsen in filp_close, but could have other, | |
221 | * more disasterous effects. There are two work-arounds: | |
222 | * 1. Disable interrupts and emulate the atomic swap | |
223 | * 2. Clean the cache, perform atomic swap, flush the cache | |
224 | * | |
225 | * We choose (1) since its the "easiest" to achieve here and is not | |
226 | * dependent on the processor type. | |
053a7b5b RK |
227 | * |
228 | * NOTE that this solution won't work on an SMP system, so explcitly | |
229 | * forbid it here. | |
1da177e4 LT |
230 | */ |
231 | #define swp_is_buggy | |
232 | #endif | |
233 | ||
234 | static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) | |
235 | { | |
236 | extern void __bad_xchg(volatile void *, int); | |
237 | unsigned long ret; | |
238 | #ifdef swp_is_buggy | |
239 | unsigned long flags; | |
240 | #endif | |
9560782f RK |
241 | #if __LINUX_ARM_ARCH__ >= 6 |
242 | unsigned int tmp; | |
243 | #endif | |
1da177e4 LT |
244 | |
245 | switch (size) { | |
9560782f RK |
246 | #if __LINUX_ARM_ARCH__ >= 6 |
247 | case 1: | |
248 | asm volatile("@ __xchg1\n" | |
249 | "1: ldrexb %0, [%3]\n" | |
250 | " strexb %1, %2, [%3]\n" | |
251 | " teq %1, #0\n" | |
252 | " bne 1b" | |
253 | : "=&r" (ret), "=&r" (tmp) | |
254 | : "r" (x), "r" (ptr) | |
255 | : "memory", "cc"); | |
256 | break; | |
257 | case 4: | |
258 | asm volatile("@ __xchg4\n" | |
259 | "1: ldrex %0, [%3]\n" | |
260 | " strex %1, %2, [%3]\n" | |
261 | " teq %1, #0\n" | |
262 | " bne 1b" | |
263 | : "=&r" (ret), "=&r" (tmp) | |
264 | : "r" (x), "r" (ptr) | |
265 | : "memory", "cc"); | |
266 | break; | |
267 | #elif defined(swp_is_buggy) | |
268 | #ifdef CONFIG_SMP | |
269 | #error SMP is not supported on this platform | |
270 | #endif | |
271 | case 1: | |
e7cc2c59 | 272 | raw_local_irq_save(flags); |
9560782f RK |
273 | ret = *(volatile unsigned char *)ptr; |
274 | *(volatile unsigned char *)ptr = x; | |
e7cc2c59 | 275 | raw_local_irq_restore(flags); |
9560782f RK |
276 | break; |
277 | ||
278 | case 4: | |
e7cc2c59 | 279 | raw_local_irq_save(flags); |
9560782f RK |
280 | ret = *(volatile unsigned long *)ptr; |
281 | *(volatile unsigned long *)ptr = x; | |
e7cc2c59 | 282 | raw_local_irq_restore(flags); |
9560782f | 283 | break; |
1da177e4 | 284 | #else |
9560782f RK |
285 | case 1: |
286 | asm volatile("@ __xchg1\n" | |
287 | " swpb %0, %1, [%2]" | |
288 | : "=&r" (ret) | |
289 | : "r" (x), "r" (ptr) | |
290 | : "memory", "cc"); | |
291 | break; | |
292 | case 4: | |
293 | asm volatile("@ __xchg4\n" | |
294 | " swp %0, %1, [%2]" | |
295 | : "=&r" (ret) | |
296 | : "r" (x), "r" (ptr) | |
297 | : "memory", "cc"); | |
298 | break; | |
1da177e4 | 299 | #endif |
9560782f RK |
300 | default: |
301 | __bad_xchg(ptr, size), ret = 0; | |
302 | break; | |
1da177e4 LT |
303 | } |
304 | ||
305 | return ret; | |
306 | } | |
307 | ||
dabaeff0 BD |
308 | extern void disable_hlt(void); |
309 | extern void enable_hlt(void); | |
310 | ||
176393d4 MD |
311 | #include <asm-generic/cmpxchg-local.h> |
312 | ||
313 | /* | |
314 | * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make | |
315 | * them available. | |
316 | */ | |
317 | #define cmpxchg_local(ptr, o, n) \ | |
318 | ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ | |
319 | (unsigned long)(n), sizeof(*(ptr)))) | |
320 | #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) | |
321 | ||
322 | #ifndef CONFIG_SMP | |
323 | #include <asm-generic/cmpxchg.h> | |
324 | #endif | |
325 | ||
1da177e4 LT |
326 | #endif /* __ASSEMBLY__ */ |
327 | ||
328 | #define arch_align_stack(x) (x) | |
329 | ||
330 | #endif /* __KERNEL__ */ | |
331 | ||
332 | #endif |