[deliverable/linux.git] / arch / arm / include / asm / tlbflush.h

/*
 *  arch/arm/include/asm/tlbflush.h
 *
 *  Copyright (C) 1999-2003 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _ASMARM_TLBFLUSH_H
#define _ASMARM_TLBFLUSH_H

#ifdef CONFIG_MMU

#include <asm/glue.h>

#define TLB_V3_PAGE	(1 << 0)
#define TLB_V4_U_PAGE	(1 << 1)
#define TLB_V4_D_PAGE	(1 << 2)
#define TLB_V4_I_PAGE	(1 << 3)
#define TLB_V6_U_PAGE	(1 << 4)
#define TLB_V6_D_PAGE	(1 << 5)
#define TLB_V6_I_PAGE	(1 << 6)

#define TLB_V3_FULL	(1 << 8)
#define TLB_V4_U_FULL	(1 << 9)
#define TLB_V4_D_FULL	(1 << 10)
#define TLB_V4_I_FULL	(1 << 11)
#define TLB_V6_U_FULL	(1 << 12)
#define TLB_V6_D_FULL	(1 << 13)
#define TLB_V6_I_FULL	(1 << 14)

#define TLB_V6_U_ASID	(1 << 16)
#define TLB_V6_D_ASID	(1 << 17)
#define TLB_V6_I_ASID	(1 << 18)

/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
#define TLB_V7_UIS_PAGE	(1 << 19)
#define TLB_V7_UIS_FULL (1 << 20)
#define TLB_V7_UIS_ASID (1 << 21)

#define TLB_BARRIER	(1 << 28)
#define TLB_L2CLEAN_FR	(1 << 29)		/* Feroceon */
#define TLB_DCLEAN	(1 << 30)
#define TLB_WB		(1 << 31)

/*
 *	MMU TLB Model
 *	=============
 *
 *	We have the following to choose from:
 *	  v3    - ARMv3
 *	  v4    - ARMv4 without write buffer
 *	  v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
 *	  v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
 *	  fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
 *	  fa    - Faraday (v4 with write buffer with UTLB)
 *	  v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
 *	  v7wbi - identical to v6wbi
 */
#undef _TLB
#undef MULTI_TLB

#ifdef CONFIG_SMP_ON_UP
#define MULTI_TLB 1
#endif

#define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)

#ifdef CONFIG_CPU_TLB_V3
# define v3_possible_flags	v3_tlb_flags
# define v3_always_flags	v3_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v3
# endif
#else
# define v3_possible_flags	0
# define v3_always_flags	(-1UL)
#endif

#define v4_tlb_flags	(TLB_V4_U_FULL | TLB_V4_U_PAGE)

#ifdef CONFIG_CPU_TLB_V4WT
# define v4_possible_flags	v4_tlb_flags
# define v4_always_flags	v4_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4
# endif
#else
# define v4_possible_flags	0
# define v4_always_flags	(-1UL)
#endif

#define fa_tlb_flags	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
			 TLB_V4_U_FULL | TLB_V4_U_PAGE)

#ifdef CONFIG_CPU_TLB_FA
# define fa_possible_flags	fa_tlb_flags
# define fa_always_flags	fa_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB fa
# endif
#else
# define fa_possible_flags	0
# define fa_always_flags	(-1UL)
#endif

#define v4wbi_tlb_flags	(TLB_WB | TLB_DCLEAN | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_I_PAGE | TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_V4WBI
# define v4wbi_possible_flags	v4wbi_tlb_flags
# define v4wbi_always_flags	v4wbi_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wbi
# endif
#else
# define v4wbi_possible_flags	0
# define v4wbi_always_flags	(-1UL)
#endif

#define fr_tlb_flags	(TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_I_PAGE | TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_FEROCEON
# define fr_possible_flags	fr_tlb_flags
# define fr_always_flags	fr_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wbi
# endif
#else
# define fr_possible_flags	0
# define fr_always_flags	(-1UL)
#endif

#define v4wb_tlb_flags	(TLB_WB | TLB_DCLEAN | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_V4WB
# define v4wb_possible_flags	v4wb_tlb_flags
# define v4wb_always_flags	v4wb_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wb
# endif
#else
# define v4wb_possible_flags	0
# define v4wb_always_flags	(-1UL)
#endif

#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
			 TLB_V6_I_FULL | TLB_V6_D_FULL | \
			 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
			 TLB_V6_I_ASID | TLB_V6_D_ASID)

#ifdef CONFIG_CPU_TLB_V6
# define v6wbi_possible_flags	v6wbi_tlb_flags
# define v6wbi_always_flags	v6wbi_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v6wbi
# endif
#else
# define v6wbi_possible_flags	0
# define v6wbi_always_flags	(-1UL)
#endif

#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
#define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)

#ifdef CONFIG_CPU_TLB_V7

# ifdef CONFIG_SMP_ON_UP
#  define v7wbi_possible_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
#  define v7wbi_always_flags	(v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
# elif defined(CONFIG_SMP)
#  define v7wbi_possible_flags	v7wbi_tlb_flags_smp
#  define v7wbi_always_flags	v7wbi_tlb_flags_smp
# else
#  define v7wbi_possible_flags	v7wbi_tlb_flags_up
#  define v7wbi_always_flags	v7wbi_tlb_flags_up
# endif
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v7wbi
# endif
#else
# define v7wbi_possible_flags	0
# define v7wbi_always_flags	(-1UL)
#endif

#ifndef _TLB
#error Unknown TLB model
#endif

#ifndef __ASSEMBLY__

#include <linux/sched.h>

struct cpu_tlb_fns {
	void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
	void (*flush_kern_range)(unsigned long, unsigned long);
	unsigned long tlb_flags;
};

/*
 * Select the calling method
 */
#ifdef MULTI_TLB

#define __cpu_flush_user_tlb_range	cpu_tlb.flush_user_range
#define __cpu_flush_kern_tlb_range	cpu_tlb.flush_kern_range

#else

#define __cpu_flush_user_tlb_range	__glue(_TLB,_flush_user_tlb_range)
#define __cpu_flush_kern_tlb_range	__glue(_TLB,_flush_kern_tlb_range)

extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);

#endif

extern struct cpu_tlb_fns cpu_tlb;

#define __cpu_tlb_flags			cpu_tlb.tlb_flags

/*
 *	TLB Management
 *	==============
 *
 *	The arch/arm/mm/tlb-*.S files implement these methods.
 *
 *	The TLB specific code is expected to perform whatever tests it
 *	needs to determine if it should invalidate the TLB for each
 *	call.  Start addresses are inclusive and end addresses are
 *	exclusive; it is safe to round these addresses down.
 *
 *	flush_tlb_all()
 *
 *		Invalidate the entire TLB.
 *
 *	flush_tlb_mm(mm)
 *
 *		Invalidate all TLB entries in a particular address
 *		space.
 *		- mm	- mm_struct describing address space
 *
 *	flush_tlb_range(mm,start,end)
 *
 *		Invalidate a range of TLB entries in the specified
 *		address space.
 *		- mm	- mm_struct describing address space
 *		- start - start address (may not be aligned)
 *		- end	- end address (exclusive, may not be aligned)
 *
 *	flush_tlb_page(vaddr,vma)
 *
 *		Invalidate the specified page in the specified address range.
 *		- vaddr - virtual address (may not be aligned)
 *		- vma	- vma_struct describing address range
 *
 *	flush_kern_tlb_page(kaddr)
 *
 *		Invalidate the TLB entry for the specified page.  The address
 *		will be in the kernels virtual memory space.  Current uses
 *		only require the D-TLB to be invalidated.
 *		- kaddr - Kernel virtual memory address
 */

/*
 * We optimise the code below by:
 *  - building a set of TLB flags that might be set in __cpu_tlb_flags
 *  - building a set of TLB flags that will always be set in __cpu_tlb_flags
 *  - if we're going to need __cpu_tlb_flags, access it once and only once
 *
 * This allows us to build optimal assembly for the single-CPU type case,
 * and as close to optimal given the compiler constrants for multi-CPU
 * case.  We could do better for the multi-CPU case if the compiler
 * implemented the "%?" method, but this has been discontinued due to too
 * many people getting it wrong.
 */
#define possible_tlb_flags	(v3_possible_flags | \
				 v4_possible_flags | \
				 v4wbi_possible_flags | \
				 fr_possible_flags | \
				 v4wb_possible_flags | \
				 fa_possible_flags | \
				 v6wbi_possible_flags | \
				 v7wbi_possible_flags)

#define always_tlb_flags	(v3_always_flags & \
				 v4_always_flags & \
				 v4wbi_always_flags & \
				 fr_always_flags & \
				 v4wb_always_flags & \
				 fa_always_flags & \
				 v6wbi_always_flags & \
				 v7wbi_always_flags)

#define tlb_flag(f)	((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))

static inline void local_flush_tlb_all(void)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_WB))
		dsb();

	if (tlb_flag(TLB_V3_FULL))
		asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
	if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
		asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
	if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
		asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
	if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
		asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
	if (tlb_flag(TLB_V7_UIS_FULL))
		asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");

	if (tlb_flag(TLB_BARRIER)) {
		dsb();
		isb();
	}
}

static inline void local_flush_tlb_mm(struct mm_struct *mm)
{
	const int zero = 0;
	const int asid = ASID(mm);
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_WB))
		dsb();

	if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
		if (tlb_flag(TLB_V3_FULL))
			asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
		if (tlb_flag(TLB_V4_U_FULL))
			asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
		if (tlb_flag(TLB_V4_D_FULL))
			asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
		if (tlb_flag(TLB_V4_I_FULL))
			asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
	}
	put_cpu();

	if (tlb_flag(TLB_V6_U_ASID))
		asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
	if (tlb_flag(TLB_V6_D_ASID))
		asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
	if (tlb_flag(TLB_V6_I_ASID))
		asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
	if (tlb_flag(TLB_V7_UIS_ASID))
#ifdef CONFIG_ARM_ERRATA_720789
		asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
#else
		asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
#endif

	if (tlb_flag(TLB_BARRIER))
		dsb();
}

static inline void
local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);

	if (tlb_flag(TLB_WB))
		dsb();

	if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
		if (tlb_flag(TLB_V3_PAGE))
			asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
		if (tlb_flag(TLB_V4_U_PAGE))
			asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
		if (tlb_flag(TLB_V4_D_PAGE))
			asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
		if (tlb_flag(TLB_V4_I_PAGE))
			asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
		if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
			asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
	}

	if (tlb_flag(TLB_V6_U_PAGE))
		asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
	if (tlb_flag(TLB_V6_D_PAGE))
		asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
	if (tlb_flag(TLB_V6_I_PAGE))
		asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
	if (tlb_flag(TLB_V7_UIS_PAGE))
#ifdef CONFIG_ARM_ERRATA_720789
		asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc");
#else
		asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
#endif

	if (tlb_flag(TLB_BARRIER))
		dsb();
}

static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	kaddr &= PAGE_MASK;

	if (tlb_flag(TLB_WB))
		dsb();

	if (tlb_flag(TLB_V3_PAGE))
		asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V4_U_PAGE))
		asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V4_D_PAGE))
		asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V4_I_PAGE))
		asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
		asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");

	if (tlb_flag(TLB_V6_U_PAGE))
		asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V6_D_PAGE))
		asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V6_I_PAGE))
		asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
	if (tlb_flag(TLB_V7_UIS_PAGE))
		asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");

	if (tlb_flag(TLB_BARRIER)) {
		dsb();
		isb();
	}
}

/*
 *	flush_pmd_entry
 *
 *	Flush a PMD entry (word aligned, or double-word aligned) to
 *	RAM if the TLB for the CPU we are running on requires this.
 *	This is typically used when we are creating PMD entries.
 *
 *	clean_pmd_entry
 *
 *	Clean (but don't drain the write buffer) if the CPU requires
 *	these operations.  This is typically used when we are removing
 *	PMD entries.
 */
static inline void flush_pmd_entry(pmd_t *pmd)
{
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_DCLEAN))
		asm("mcr	p15, 0, %0, c7, c10, 1	@ flush_pmd"
			: : "r" (pmd) : "cc");

	if (tlb_flag(TLB_L2CLEAN_FR))
		asm("mcr	p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
			: : "r" (pmd) : "cc");

	if (tlb_flag(TLB_WB))
		dsb();
}

static inline void clean_pmd_entry(pmd_t *pmd)
{
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_DCLEAN))
		asm("mcr	p15, 0, %0, c7, c10, 1	@ flush_pmd"
			: : "r" (pmd) : "cc");

	if (tlb_flag(TLB_L2CLEAN_FR))
		asm("mcr	p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
			: : "r" (pmd) : "cc");
}

#undef tlb_flag
#undef always_tlb_flags
#undef possible_tlb_flags

/*
 * Convert calls to our calling convention.
 */
#define local_flush_tlb_range(vma,start,end)	__cpu_flush_user_tlb_range(start,end,vma)
#define local_flush_tlb_kernel_range(s,e)	__cpu_flush_kern_tlb_range(s,e)

#ifndef CONFIG_SMP
#define flush_tlb_all		local_flush_tlb_all
#define flush_tlb_mm		local_flush_tlb_mm
#define flush_tlb_page		local_flush_tlb_page
#define flush_tlb_kernel_page	local_flush_tlb_kernel_page
#define flush_tlb_range		local_flush_tlb_range
#define flush_tlb_kernel_range	local_flush_tlb_kernel_range
#else
extern void flush_tlb_all(void);
extern void flush_tlb_mm(struct mm_struct *mm);
extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
extern void flush_tlb_kernel_page(unsigned long kaddr);
extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
#endif

/*
 * If PG_dcache_clean is not set for the page, we need to ensure that any
 * cache entries for the kernels virtual memory range are written
 * back to the page. On ARMv6 and later, the cache coherency is handled via
 * the set_pte_at() function.
 */
#if __LINUX_ARM_ARCH__ < 6
extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
	pte_t *ptep);
#else
static inline void update_mmu_cache(struct vm_area_struct *vma,
				    unsigned long addr, pte_t *ptep)
{
}
#endif

#endif

#endif /* CONFIG_MMU */

#endif
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/tlbflush.h
1da177e4 LT	3	*
	4	* Copyright (C) 1999-2003 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef _ASMARM_TLBFLUSH_H
	11	#define _ASMARM_TLBFLUSH_H
	12
58e9c47f	13	#ifdef CONFIG_MMU
0157903e	14
1da177e4 LT	15	#include <asm/glue.h>
	16
	17	#define TLB_V3_PAGE (1 << 0)
	18	#define TLB_V4_U_PAGE (1 << 1)
	19	#define TLB_V4_D_PAGE (1 << 2)
	20	#define TLB_V4_I_PAGE (1 << 3)
	21	#define TLB_V6_U_PAGE (1 << 4)
	22	#define TLB_V6_D_PAGE (1 << 5)
	23	#define TLB_V6_I_PAGE (1 << 6)
	24
	25	#define TLB_V3_FULL (1 << 8)
	26	#define TLB_V4_U_FULL (1 << 9)
	27	#define TLB_V4_D_FULL (1 << 10)
	28	#define TLB_V4_I_FULL (1 << 11)
	29	#define TLB_V6_U_FULL (1 << 12)
	30	#define TLB_V6_D_FULL (1 << 13)
	31	#define TLB_V6_I_FULL (1 << 14)
	32
	33	#define TLB_V6_U_ASID (1 << 16)
	34	#define TLB_V6_D_ASID (1 << 17)
	35	#define TLB_V6_I_ASID (1 << 18)
	36
faa7bc51 CM	37	/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
	38	#define TLB_V7_UIS_PAGE (1 << 19)
	39	#define TLB_V7_UIS_FULL (1 << 20)
	40	#define TLB_V7_UIS_ASID (1 << 21)
	41
4348810a	42	#define TLB_BARRIER (1 << 28)
99c6dc11	43	#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
1da177e4 LT	44	#define TLB_DCLEAN (1 << 30)
	45	#define TLB_WB (1 << 31)
	46
	47	/*
	48	* MMU TLB Model
	49	* =============
	50	*
	51	* We have the following to choose from:
	52	* v3 - ARMv3
	53	* v4 - ARMv4 without write buffer
	54	* v4wb - ARMv4 with write buffer without I TLB flush entry instruction
	55	* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
99c6dc11	56	* fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
4348810a	57	* fa - Faraday (v4 with write buffer with UTLB)
1da177e4	58	* v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
61db7fb1	59	* v7wbi - identical to v6wbi
1da177e4 LT	60	*/
	61	#undef _TLB
	62	#undef MULTI_TLB
	63
f00ec48f RK	64	#ifdef CONFIG_SMP_ON_UP
	65	#define MULTI_TLB 1
	66	#endif
	67
1da177e4 LT	68	#define v3_tlb_flags (TLB_V3_FULL \| TLB_V3_PAGE)
	69
	70	#ifdef CONFIG_CPU_TLB_V3
	71	# define v3_possible_flags v3_tlb_flags
	72	# define v3_always_flags v3_tlb_flags
	73	# ifdef _TLB
	74	# define MULTI_TLB 1
	75	# else
	76	# define _TLB v3
	77	# endif
	78	#else
	79	# define v3_possible_flags 0
	80	# define v3_always_flags (-1UL)
	81	#endif
	82
	83	#define v4_tlb_flags (TLB_V4_U_FULL \| TLB_V4_U_PAGE)
	84
	85	#ifdef CONFIG_CPU_TLB_V4WT
	86	# define v4_possible_flags v4_tlb_flags
	87	# define v4_always_flags v4_tlb_flags
	88	# ifdef _TLB
	89	# define MULTI_TLB 1
	90	# else
	91	# define _TLB v4
	92	# endif
	93	#else
	94	# define v4_possible_flags 0
	95	# define v4_always_flags (-1UL)
	96	#endif
	97
4348810a	98	#define fa_tlb_flags (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
28853ac8 PZ	99	TLB_V4_U_FULL \| TLB_V4_U_PAGE)
	100
	101	#ifdef CONFIG_CPU_TLB_FA
	102	# define fa_possible_flags fa_tlb_flags
	103	# define fa_always_flags fa_tlb_flags
	104	# ifdef _TLB
	105	# define MULTI_TLB 1
	106	# else
	107	# define _TLB fa
	108	# endif
	109	#else
	110	# define fa_possible_flags 0
	111	# define fa_always_flags (-1UL)
	112	#endif
	113
1da177e4 LT	114	#define v4wbi_tlb_flags (TLB_WB \| TLB_DCLEAN \| \
	115	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
	116	TLB_V4_I_PAGE \| TLB_V4_D_PAGE)
	117
	118	#ifdef CONFIG_CPU_TLB_V4WBI
	119	# define v4wbi_possible_flags v4wbi_tlb_flags
	120	# define v4wbi_always_flags v4wbi_tlb_flags
	121	# ifdef _TLB
	122	# define MULTI_TLB 1
	123	# else
	124	# define _TLB v4wbi
	125	# endif
	126	#else
	127	# define v4wbi_possible_flags 0
	128	# define v4wbi_always_flags (-1UL)
	129	#endif
	130
99c6dc11 LB	131	#define fr_tlb_flags (TLB_WB \| TLB_DCLEAN \| TLB_L2CLEAN_FR \| \
	132	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
	133	TLB_V4_I_PAGE \| TLB_V4_D_PAGE)
	134
	135	#ifdef CONFIG_CPU_TLB_FEROCEON
	136	# define fr_possible_flags fr_tlb_flags
	137	# define fr_always_flags fr_tlb_flags
	138	# ifdef _TLB
	139	# define MULTI_TLB 1
	140	# else
	141	# define _TLB v4wbi
	142	# endif
	143	#else
	144	# define fr_possible_flags 0
	145	# define fr_always_flags (-1UL)
	146	#endif
	147
1da177e4 LT	148	#define v4wb_tlb_flags (TLB_WB \| TLB_DCLEAN \| \
	149	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
	150	TLB_V4_D_PAGE)
	151
	152	#ifdef CONFIG_CPU_TLB_V4WB
	153	# define v4wb_possible_flags v4wb_tlb_flags
	154	# define v4wb_always_flags v4wb_tlb_flags
	155	# ifdef _TLB
	156	# define MULTI_TLB 1
	157	# else
	158	# define _TLB v4wb
	159	# endif
	160	#else
	161	# define v4wb_possible_flags 0
	162	# define v4wb_always_flags (-1UL)
	163	#endif
	164
4348810a	165	#define v6wbi_tlb_flags (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
1da177e4 LT	166	TLB_V6_I_FULL \| TLB_V6_D_FULL \| \
	167	TLB_V6_I_PAGE \| TLB_V6_D_PAGE \| \
	168	TLB_V6_I_ASID \| TLB_V6_D_ASID)
	169
	170	#ifdef CONFIG_CPU_TLB_V6
	171	# define v6wbi_possible_flags v6wbi_tlb_flags
	172	# define v6wbi_always_flags v6wbi_tlb_flags
	173	# ifdef _TLB
	174	# define MULTI_TLB 1
	175	# else
	176	# define _TLB v6wbi
	177	# endif
	178	#else
	179	# define v6wbi_possible_flags 0
	180	# define v6wbi_always_flags (-1UL)
	181	#endif
	182
4348810a	183	#define v7wbi_tlb_flags_smp (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
faa7bc51	184	TLB_V7_UIS_FULL \| TLB_V7_UIS_PAGE \| TLB_V7_UIS_ASID)
4348810a	185	#define v7wbi_tlb_flags_up (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
faa7bc51	186	TLB_V6_U_FULL \| TLB_V6_U_PAGE \| TLB_V6_U_ASID)
faa7bc51	187
2ccdd1e7	188	#ifdef CONFIG_CPU_TLB_V7
f00ec48f RK	189
	190	# ifdef CONFIG_SMP_ON_UP
	191	# define v7wbi_possible_flags (v7wbi_tlb_flags_smp \| v7wbi_tlb_flags_up)
	192	# define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
	193	# elif defined(CONFIG_SMP)
	194	# define v7wbi_possible_flags v7wbi_tlb_flags_smp
	195	# define v7wbi_always_flags v7wbi_tlb_flags_smp
	196	# else
	197	# define v7wbi_possible_flags v7wbi_tlb_flags_up
	198	# define v7wbi_always_flags v7wbi_tlb_flags_up
	199	# endif
2ccdd1e7 CM	200	# ifdef _TLB
	201	# define MULTI_TLB 1
	202	# else
	203	# define _TLB v7wbi
	204	# endif
	205	#else
	206	# define v7wbi_possible_flags 0
	207	# define v7wbi_always_flags (-1UL)
	208	#endif
	209
1da177e4 LT	210	#ifndef _TLB
	211	#error Unknown TLB model
	212	#endif
	213
	214	#ifndef __ASSEMBLY__
	215
e8edc6e0 AD	216	#include <linux/sched.h>
e8edc6e0 AD	217
1da177e4 LT	218	struct cpu_tlb_fns {
	219	void (flush_user_range)(unsigned long, unsigned long, struct vm_area_struct );
	220	void (*flush_kern_range)(unsigned long, unsigned long);
	221	unsigned long tlb_flags;
	222	};
	223
	224	/*
	225	* Select the calling method
	226	*/
	227	#ifdef MULTI_TLB
	228
	229	#define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
	230	#define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range
	231
	232	#else
	233
	234	#define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
	235	#define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range)
	236
	237	extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
	238	extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
	239
	240	#endif
	241
	242	extern struct cpu_tlb_fns cpu_tlb;
	243
	244	#define __cpu_tlb_flags cpu_tlb.tlb_flags
	245
	246	/*
	247	* TLB Management
	248	* ==============
	249	*
	250	* The arch/arm/mm/tlb-*.S files implement these methods.
	251	*
	252	* The TLB specific code is expected to perform whatever tests it
	253	* needs to determine if it should invalidate the TLB for each
	254	* call. Start addresses are inclusive and end addresses are
	255	* exclusive; it is safe to round these addresses down.
	256	*
	257	* flush_tlb_all()
	258	*
	259	* Invalidate the entire TLB.
	260	*
	261	* flush_tlb_mm(mm)
	262	*
	263	* Invalidate all TLB entries in a particular address
	264	* space.
	265	* - mm - mm_struct describing address space
	266	*
	267	* flush_tlb_range(mm,start,end)
	268	*
	269	* Invalidate a range of TLB entries in the specified
	270	* address space.
	271	* - mm - mm_struct describing address space
	272	* - start - start address (may not be aligned)
	273	* - end - end address (exclusive, may not be aligned)
	274	*
	275	* flush_tlb_page(vaddr,vma)
	276	*
	277	* Invalidate the specified page in the specified address range.
	278	* - vaddr - virtual address (may not be aligned)
	279	* - vma - vma_struct describing address range
	280	*
	281	* flush_kern_tlb_page(kaddr)
282	*
283	* Invalidate the TLB entry for the specified page. The address
284	* will be in the kernels virtual memory space. Current uses
285	* only require the D-TLB to be invalidated.
286	* - kaddr - Kernel virtual memory address
287	*/
288
289	/*
290	* We optimise the code below by:
291	* - building a set of TLB flags that might be set in __cpu_tlb_flags
292	* - building a set of TLB flags that will always be set in __cpu_tlb_flags
293	* - if we're going to need __cpu_tlb_flags, access it once and only once
294	*
295	* This allows us to build optimal assembly for the single-CPU type case,
296	* and as close to optimal given the compiler constrants for multi-CPU
297	* case. We could do better for the multi-CPU case if the compiler
298	* implemented the "%?" method, but this has been discontinued due to too
299	* many people getting it wrong.
300	*/
301	#define possible_tlb_flags (v3_possible_flags \| \
302	v4_possible_flags \| \
303	v4wbi_possible_flags \| \
99c6dc11	304	fr_possible_flags \| \
1da177e4	305	v4wb_possible_flags \| \
28853ac8	306	fa_possible_flags \| \
61db7fb1 PW	307	v6wbi_possible_flags \| \
61db7fb1 PW	308	v7wbi_possible_flags)
1da177e4 LT	309
	310	#define always_tlb_flags (v3_always_flags & \
	311	v4_always_flags & \
	312	v4wbi_always_flags & \
99c6dc11	313	fr_always_flags & \
1da177e4	314	v4wb_always_flags & \
28853ac8	315	fa_always_flags & \
61db7fb1 PW	316	v6wbi_always_flags & \
61db7fb1 PW	317	v7wbi_always_flags)
1da177e4 LT	318
	319	#define tlb_flag(f) ((always_tlb_flags & (f)) \|\| (__tlb_flag & possible_tlb_flags & (f)))
	320
603fff54	321	static inline void local_flush_tlb_all(void)
1da177e4 LT	322	{
	323	const int zero = 0;
	324	const unsigned int __tlb_flag = __cpu_tlb_flags;
	325
	326	if (tlb_flag(TLB_WB))
e6a5d66f	327	dsb();
1da177e4 LT	328
1da177e4 LT	329	if (tlb_flag(TLB_V3_FULL))
6a39dd62	330	asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
1da177e4	331	if (tlb_flag(TLB_V4_U_FULL \| TLB_V6_U_FULL))
6a39dd62	332	asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
1da177e4	333	if (tlb_flag(TLB_V4_D_FULL \| TLB_V6_D_FULL))
6a39dd62	334	asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
1da177e4	335	if (tlb_flag(TLB_V4_I_FULL \| TLB_V6_I_FULL))
6a39dd62	336	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
faa7bc51 CM	337	if (tlb_flag(TLB_V7_UIS_FULL))
faa7bc51 CM	338	asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
e6a5d66f	339
4348810a	340	if (tlb_flag(TLB_BARRIER)) {
b8349b56 CM	341	dsb();
	342	isb();
	343	}
1da177e4 LT	344	}
1da177e4 LT	345
603fff54	346	static inline void local_flush_tlb_mm(struct mm_struct *mm)
1da177e4 LT	347	{
	348	const int zero = 0;
	349	const int asid = ASID(mm);
	350	const unsigned int __tlb_flag = __cpu_tlb_flags;
	351
	352	if (tlb_flag(TLB_WB))
e6a5d66f	353	dsb();
1da177e4	354
daaeb6c9	355	if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
1da177e4	356	if (tlb_flag(TLB_V3_FULL))
6a39dd62	357	asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
1da177e4	358	if (tlb_flag(TLB_V4_U_FULL))
6a39dd62	359	asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
1da177e4	360	if (tlb_flag(TLB_V4_D_FULL))
6a39dd62	361	asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
1da177e4	362	if (tlb_flag(TLB_V4_I_FULL))
6a39dd62	363	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
1da177e4	364	}
daaeb6c9	365	put_cpu();
1da177e4 LT	366
1da177e4 LT	367	if (tlb_flag(TLB_V6_U_ASID))
6a39dd62	368	asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
1da177e4	369	if (tlb_flag(TLB_V6_D_ASID))
6a39dd62	370	asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
1da177e4	371	if (tlb_flag(TLB_V6_I_ASID))
6a39dd62	372	asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
faa7bc51	373	if (tlb_flag(TLB_V7_UIS_ASID))
cdf357f1 WD	374	#ifdef CONFIG_ARM_ERRATA_720789
	375	asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
	376	#else
faa7bc51	377	asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
cdf357f1	378	#endif
e6a5d66f	379
4348810a	380	if (tlb_flag(TLB_BARRIER))
b8349b56	381	dsb();
1da177e4 LT	382	}
	383
	384	static inline void
603fff54	385	local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
1da177e4 LT	386	{
	387	const int zero = 0;
	388	const unsigned int __tlb_flag = __cpu_tlb_flags;
	389
	390	uaddr = (uaddr & PAGE_MASK) \| ASID(vma->vm_mm);
	391
	392	if (tlb_flag(TLB_WB))
e6a5d66f	393	dsb();
1da177e4	394
56f8ba83	395	if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
1da177e4	396	if (tlb_flag(TLB_V3_PAGE))
6a39dd62	397	asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
1da177e4	398	if (tlb_flag(TLB_V4_U_PAGE))
6a39dd62	399	asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
1da177e4	400	if (tlb_flag(TLB_V4_D_PAGE))
6a39dd62	401	asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
1da177e4	402	if (tlb_flag(TLB_V4_I_PAGE))
6a39dd62	403	asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
1da177e4	404	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
6a39dd62	405	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
1da177e4 LT	406	}
	407
	408	if (tlb_flag(TLB_V6_U_PAGE))
6a39dd62	409	asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
1da177e4	410	if (tlb_flag(TLB_V6_D_PAGE))
6a39dd62	411	asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
1da177e4	412	if (tlb_flag(TLB_V6_I_PAGE))
6a39dd62	413	asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
faa7bc51	414	if (tlb_flag(TLB_V7_UIS_PAGE))
cdf357f1 WD	415	#ifdef CONFIG_ARM_ERRATA_720789
	416	asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc");
	417	#else
faa7bc51	418	asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
cdf357f1	419	#endif
e6a5d66f	420
4348810a	421	if (tlb_flag(TLB_BARRIER))
b8349b56	422	dsb();
1da177e4 LT	423	}
1da177e4 LT	424
603fff54	425	static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
1da177e4 LT	426	{
	427	const int zero = 0;
	428	const unsigned int __tlb_flag = __cpu_tlb_flags;
	429
	430	kaddr &= PAGE_MASK;
	431
	432	if (tlb_flag(TLB_WB))
e6a5d66f	433	dsb();
1da177e4 LT	434
1da177e4 LT	435	if (tlb_flag(TLB_V3_PAGE))
6a39dd62	436	asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
1da177e4	437	if (tlb_flag(TLB_V4_U_PAGE))
6a39dd62	438	asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
1da177e4	439	if (tlb_flag(TLB_V4_D_PAGE))
6a39dd62	440	asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
1da177e4	441	if (tlb_flag(TLB_V4_I_PAGE))
6a39dd62	442	asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
1da177e4	443	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
6a39dd62	444	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
1da177e4 LT	445
1da177e4 LT	446	if (tlb_flag(TLB_V6_U_PAGE))
6a39dd62	447	asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
1da177e4	448	if (tlb_flag(TLB_V6_D_PAGE))
6a39dd62	449	asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
1da177e4	450	if (tlb_flag(TLB_V6_I_PAGE))
6a39dd62	451	asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
faa7bc51 CM	452	if (tlb_flag(TLB_V7_UIS_PAGE))
faa7bc51 CM	453	asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
6a0e2430	454
4348810a	455	if (tlb_flag(TLB_BARRIER)) {
b8349b56 CM	456	dsb();
	457	isb();
	458	}
1da177e4 LT	459	}
	460
	461	/*
	462	* flush_pmd_entry
	463	*
	464	* Flush a PMD entry (word aligned, or double-word aligned) to
	465	* RAM if the TLB for the CPU we are running on requires this.
	466	* This is typically used when we are creating PMD entries.
	467	*
	468	* clean_pmd_entry
	469	*
	470	* Clean (but don't drain the write buffer) if the CPU requires
	471	* these operations. This is typically used when we are removing
	472	* PMD entries.
	473	*/
	474	static inline void flush_pmd_entry(pmd_t *pmd)
	475	{
1da177e4 LT	476	const unsigned int __tlb_flag = __cpu_tlb_flags;
	477
	478	if (tlb_flag(TLB_DCLEAN))
6a39dd62 DJ	479	asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
6a39dd62 DJ	480	: : "r" (pmd) : "cc");
99c6dc11 LB	481
	482	if (tlb_flag(TLB_L2CLEAN_FR))
	483	asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
	484	: : "r" (pmd) : "cc");
	485
1da177e4	486	if (tlb_flag(TLB_WB))
e6a5d66f	487	dsb();
1da177e4 LT	488	}
	489
	490	static inline void clean_pmd_entry(pmd_t *pmd)
	491	{
	492	const unsigned int __tlb_flag = __cpu_tlb_flags;
	493
	494	if (tlb_flag(TLB_DCLEAN))
6a39dd62 DJ	495	asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
6a39dd62 DJ	496	: : "r" (pmd) : "cc");
99c6dc11 LB	497
	498	if (tlb_flag(TLB_L2CLEAN_FR))
	499	asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
	500	: : "r" (pmd) : "cc");
1da177e4 LT	501	}
	502
	503	#undef tlb_flag
	504	#undef always_tlb_flags
	505	#undef possible_tlb_flags
	506
	507	/*
	508	* Convert calls to our calling convention.
	509	*/
603fff54 RK	510	#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
	511	#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
	512
	513	#ifndef CONFIG_SMP
	514	#define flush_tlb_all local_flush_tlb_all
	515	#define flush_tlb_mm local_flush_tlb_mm
	516	#define flush_tlb_page local_flush_tlb_page
	517	#define flush_tlb_kernel_page local_flush_tlb_kernel_page
	518	#define flush_tlb_range local_flush_tlb_range
	519	#define flush_tlb_kernel_range local_flush_tlb_kernel_range
	520	#else
	521	extern void flush_tlb_all(void);
	522	extern void flush_tlb_mm(struct mm_struct *mm);
	523	extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
	524	extern void flush_tlb_kernel_page(unsigned long kaddr);
	525	extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
	526	extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
	527	#endif
1da177e4 LT	528
1da177e4 LT	529	/*
c0177800	530	* If PG_dcache_clean is not set for the page, we need to ensure that any
1da177e4	531	* cache entries for the kernels virtual memory range are written
6012191a CM	532	* back to the page. On ARMv6 and later, the cache coherency is handled via
6012191a CM	533	* the set_pte_at() function.
1da177e4	534	*/
6012191a	535	#if __LINUX_ARM_ARCH__ < 6
4b3073e1 RK	536	extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
4b3073e1 RK	537	pte_t *ptep);
6012191a CM	538	#else
	539	static inline void update_mmu_cache(struct vm_area_struct *vma,
	540	unsigned long addr, pte_t *ptep)
	541	{
	542	}
	543	#endif
1da177e4	544
1da177e4 LT	545	#endif
1da177e4 LT	546
0157903e HC	547	#endif /* CONFIG_MMU */
0157903e HC	548
1da177e4	549	#endif