[deliverable/linux.git] / arch / arm / include / asm / tlbflush.h

/*
 *  arch/arm/include/asm/tlbflush.h
 *
 *  Copyright (C) 1999-2003 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _ASMARM_TLBFLUSH_H
#define _ASMARM_TLBFLUSH_H

#ifdef CONFIG_MMU

#include <asm/glue.h>

#define TLB_V4_U_PAGE	(1 << 1)
#define TLB_V4_D_PAGE	(1 << 2)
#define TLB_V4_I_PAGE	(1 << 3)
#define TLB_V6_U_PAGE	(1 << 4)
#define TLB_V6_D_PAGE	(1 << 5)
#define TLB_V6_I_PAGE	(1 << 6)

#define TLB_V4_U_FULL	(1 << 9)
#define TLB_V4_D_FULL	(1 << 10)
#define TLB_V4_I_FULL	(1 << 11)
#define TLB_V6_U_FULL	(1 << 12)
#define TLB_V6_D_FULL	(1 << 13)
#define TLB_V6_I_FULL	(1 << 14)

#define TLB_V6_U_ASID	(1 << 16)
#define TLB_V6_D_ASID	(1 << 17)
#define TLB_V6_I_ASID	(1 << 18)

#define TLB_V6_BP	(1 << 19)

/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
#define TLB_V7_UIS_PAGE	(1 << 20)
#define TLB_V7_UIS_FULL (1 << 21)
#define TLB_V7_UIS_ASID (1 << 22)
#define TLB_V7_UIS_BP	(1 << 23)

#define TLB_BARRIER	(1 << 28)
#define TLB_L2CLEAN_FR	(1 << 29)		/* Feroceon */
#define TLB_DCLEAN	(1 << 30)
#define TLB_WB		(1 << 31)

/*
 *	MMU TLB Model
 *	=============
 *
 *	We have the following to choose from:
 *	  v4    - ARMv4 without write buffer
 *	  v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
 *	  v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
 *	  fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
 *	  fa    - Faraday (v4 with write buffer with UTLB)
 *	  v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
 *	  v7wbi - identical to v6wbi
 */
#undef _TLB
#undef MULTI_TLB

#ifdef CONFIG_SMP_ON_UP
#define MULTI_TLB 1
#endif

#define v4_tlb_flags	(TLB_V4_U_FULL | TLB_V4_U_PAGE)

#ifdef CONFIG_CPU_TLB_V4WT
# define v4_possible_flags	v4_tlb_flags
# define v4_always_flags	v4_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4
# endif
#else
# define v4_possible_flags	0
# define v4_always_flags	(-1UL)
#endif

#define fa_tlb_flags	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
			 TLB_V4_U_FULL | TLB_V4_U_PAGE)

#ifdef CONFIG_CPU_TLB_FA
# define fa_possible_flags	fa_tlb_flags
# define fa_always_flags	fa_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB fa
# endif
#else
# define fa_possible_flags	0
# define fa_always_flags	(-1UL)
#endif

#define v4wbi_tlb_flags	(TLB_WB | TLB_DCLEAN | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_I_PAGE | TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_V4WBI
# define v4wbi_possible_flags	v4wbi_tlb_flags
# define v4wbi_always_flags	v4wbi_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wbi
# endif
#else
# define v4wbi_possible_flags	0
# define v4wbi_always_flags	(-1UL)
#endif

#define fr_tlb_flags	(TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_I_PAGE | TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_FEROCEON
# define fr_possible_flags	fr_tlb_flags
# define fr_always_flags	fr_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wbi
# endif
#else
# define fr_possible_flags	0
# define fr_always_flags	(-1UL)
#endif

#define v4wb_tlb_flags	(TLB_WB | TLB_DCLEAN | \
			 TLB_V4_I_FULL | TLB_V4_D_FULL | \
			 TLB_V4_D_PAGE)

#ifdef CONFIG_CPU_TLB_V4WB
# define v4wb_possible_flags	v4wb_tlb_flags
# define v4wb_always_flags	v4wb_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v4wb
# endif
#else
# define v4wb_possible_flags	0
# define v4wb_always_flags	(-1UL)
#endif

#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
			 TLB_V6_I_FULL | TLB_V6_D_FULL | \
			 TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
			 TLB_V6_I_ASID | TLB_V6_D_ASID | \
			 TLB_V6_BP)

#ifdef CONFIG_CPU_TLB_V6
# define v6wbi_possible_flags	v6wbi_tlb_flags
# define v6wbi_always_flags	v6wbi_tlb_flags
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v6wbi
# endif
#else
# define v6wbi_possible_flags	0
# define v6wbi_always_flags	(-1UL)
#endif

#define v7wbi_tlb_flags_smp	(TLB_WB | TLB_BARRIER | \
				 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
				 TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
#define v7wbi_tlb_flags_up	(TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
				 TLB_V6_U_FULL | TLB_V6_U_PAGE | \
				 TLB_V6_U_ASID | TLB_V6_BP)

#ifdef CONFIG_CPU_TLB_V7

# ifdef CONFIG_SMP_ON_UP
#  define v7wbi_possible_flags	(v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
#  define v7wbi_always_flags	(v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
# elif defined(CONFIG_SMP)
#  define v7wbi_possible_flags	v7wbi_tlb_flags_smp
#  define v7wbi_always_flags	v7wbi_tlb_flags_smp
# else
#  define v7wbi_possible_flags	v7wbi_tlb_flags_up
#  define v7wbi_always_flags	v7wbi_tlb_flags_up
# endif
# ifdef _TLB
#  define MULTI_TLB 1
# else
#  define _TLB v7wbi
# endif
#else
# define v7wbi_possible_flags	0
# define v7wbi_always_flags	(-1UL)
#endif

#ifndef _TLB
#error Unknown TLB model
#endif

#ifndef __ASSEMBLY__

#include <linux/sched.h>

struct cpu_tlb_fns {
	void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
	void (*flush_kern_range)(unsigned long, unsigned long);
	unsigned long tlb_flags;
};

/*
 * Select the calling method
 */
#ifdef MULTI_TLB

#define __cpu_flush_user_tlb_range	cpu_tlb.flush_user_range
#define __cpu_flush_kern_tlb_range	cpu_tlb.flush_kern_range

#else

#define __cpu_flush_user_tlb_range	__glue(_TLB,_flush_user_tlb_range)
#define __cpu_flush_kern_tlb_range	__glue(_TLB,_flush_kern_tlb_range)

extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);

#endif

extern struct cpu_tlb_fns cpu_tlb;

#define __cpu_tlb_flags			cpu_tlb.tlb_flags

/*
 *	TLB Management
 *	==============
 *
 *	The arch/arm/mm/tlb-*.S files implement these methods.
 *
 *	The TLB specific code is expected to perform whatever tests it
 *	needs to determine if it should invalidate the TLB for each
 *	call.  Start addresses are inclusive and end addresses are
 *	exclusive; it is safe to round these addresses down.
 *
 *	flush_tlb_all()
 *
 *		Invalidate the entire TLB.
 *
 *	flush_tlb_mm(mm)
 *
 *		Invalidate all TLB entries in a particular address
 *		space.
 *		- mm	- mm_struct describing address space
 *
 *	flush_tlb_range(mm,start,end)
 *
 *		Invalidate a range of TLB entries in the specified
 *		address space.
 *		- mm	- mm_struct describing address space
 *		- start - start address (may not be aligned)
 *		- end	- end address (exclusive, may not be aligned)
 *
 *	flush_tlb_page(vaddr,vma)
 *
 *		Invalidate the specified page in the specified address range.
 *		- vaddr - virtual address (may not be aligned)
 *		- vma	- vma_struct describing address range
 *
 *	flush_kern_tlb_page(kaddr)
 *
 *		Invalidate the TLB entry for the specified page.  The address
 *		will be in the kernels virtual memory space.  Current uses
 *		only require the D-TLB to be invalidated.
 *		- kaddr - Kernel virtual memory address
 */

/*
 * We optimise the code below by:
 *  - building a set of TLB flags that might be set in __cpu_tlb_flags
 *  - building a set of TLB flags that will always be set in __cpu_tlb_flags
 *  - if we're going to need __cpu_tlb_flags, access it once and only once
 *
 * This allows us to build optimal assembly for the single-CPU type case,
 * and as close to optimal given the compiler constrants for multi-CPU
 * case.  We could do better for the multi-CPU case if the compiler
 * implemented the "%?" method, but this has been discontinued due to too
 * many people getting it wrong.
 */
#define possible_tlb_flags	(v4_possible_flags | \
				 v4wbi_possible_flags | \
				 fr_possible_flags | \
				 v4wb_possible_flags | \
				 fa_possible_flags | \
				 v6wbi_possible_flags | \
				 v7wbi_possible_flags)

#define always_tlb_flags	(v4_always_flags & \
				 v4wbi_always_flags & \
				 fr_always_flags & \
				 v4wb_always_flags & \
				 fa_always_flags & \
				 v6wbi_always_flags & \
				 v7wbi_always_flags)

#define tlb_flag(f)	((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))

#define __tlb_op(f, insnarg, arg)					\
	do {								\
		if (always_tlb_flags & (f))				\
			asm("mcr " insnarg				\
			    : : "r" (arg) : "cc");			\
		else if (possible_tlb_flags & (f))			\
			asm("tst %1, %2\n\t"				\
			    "mcrne " insnarg				\
			    : : "r" (arg), "r" (__tlb_flag), "Ir" (f)	\
			    : "cc");					\
	} while (0)

#define tlb_op(f, regs, arg)	__tlb_op(f, "p15, 0, %0, " regs, arg)
#define tlb_l2_op(f, regs, arg)	__tlb_op(f, "p15, 1, %0, " regs, arg)

static inline void local_flush_tlb_all(void)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_WB))
		dsb();

	tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);
	tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);
	tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
	tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);

	if (tlb_flag(TLB_BARRIER)) {
		dsb();
		isb();
	}
}

static inline void local_flush_tlb_mm(struct mm_struct *mm)
{
	const int zero = 0;
	const int asid = ASID(mm);
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_WB))
		dsb();

	if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {
		if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
			tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
			tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
			tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
		}
		put_cpu();
	}

	tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
	tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
	tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
#ifdef CONFIG_ARM_ERRATA_720789
	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero);
#else
	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid);
#endif

	if (tlb_flag(TLB_BARRIER))
		dsb();
}

static inline void
local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);

	if (tlb_flag(TLB_WB))
		dsb();

	if (possible_tlb_flags & (TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&
	    cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
		tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
		tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
		tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
		if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
			asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
	}

	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
#ifdef CONFIG_ARM_ERRATA_720789
	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
#else
	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr);
#endif

	if (tlb_flag(TLB_BARRIER))
		dsb();
}

static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	kaddr &= PAGE_MASK;

	if (tlb_flag(TLB_WB))
		dsb();

	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
		asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");

	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);

	if (tlb_flag(TLB_BARRIER)) {
		dsb();
		isb();
	}
}

static inline void local_flush_bp_all(void)
{
	const int zero = 0;
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	if (tlb_flag(TLB_V7_UIS_BP))
		asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
	else if (tlb_flag(TLB_V6_BP))
		asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));

	if (tlb_flag(TLB_BARRIER))
		isb();
}

#ifdef CONFIG_ARM_ERRATA_798181
static inline void dummy_flush_tlb_a15_erratum(void)
{
	/*
	 * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
	 */
	asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
	dsb();
}
#else
static inline void dummy_flush_tlb_a15_erratum(void)
{
}
#endif

/*
 *	flush_pmd_entry
 *
 *	Flush a PMD entry (word aligned, or double-word aligned) to
 *	RAM if the TLB for the CPU we are running on requires this.
 *	This is typically used when we are creating PMD entries.
 *
 *	clean_pmd_entry
 *
 *	Clean (but don't drain the write buffer) if the CPU requires
 *	these operations.  This is typically used when we are removing
 *	PMD entries.
 */
static inline void flush_pmd_entry(void *pmd)
{
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);

	if (tlb_flag(TLB_WB))
		dsb();
}

static inline void clean_pmd_entry(void *pmd)
{
	const unsigned int __tlb_flag = __cpu_tlb_flags;

	tlb_op(TLB_DCLEAN, "c7, c10, 1	@ flush_pmd", pmd);
	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1  @ L2 flush_pmd", pmd);
}

#undef tlb_op
#undef tlb_flag
#undef always_tlb_flags
#undef possible_tlb_flags

/*
 * Convert calls to our calling convention.
 */
#define local_flush_tlb_range(vma,start,end)	__cpu_flush_user_tlb_range(start,end,vma)
#define local_flush_tlb_kernel_range(s,e)	__cpu_flush_kern_tlb_range(s,e)

#ifndef CONFIG_SMP
#define flush_tlb_all		local_flush_tlb_all
#define flush_tlb_mm		local_flush_tlb_mm
#define flush_tlb_page		local_flush_tlb_page
#define flush_tlb_kernel_page	local_flush_tlb_kernel_page
#define flush_tlb_range		local_flush_tlb_range
#define flush_tlb_kernel_range	local_flush_tlb_kernel_range
#define flush_bp_all		local_flush_bp_all
#else
extern void flush_tlb_all(void);
extern void flush_tlb_mm(struct mm_struct *mm);
extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
extern void flush_tlb_kernel_page(unsigned long kaddr);
extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
extern void flush_bp_all(void);
#endif

/*
 * If PG_dcache_clean is not set for the page, we need to ensure that any
 * cache entries for the kernels virtual memory range are written
 * back to the page. On ARMv6 and later, the cache coherency is handled via
 * the set_pte_at() function.
 */
#if __LINUX_ARM_ARCH__ < 6
extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
	pte_t *ptep);
#else
static inline void update_mmu_cache(struct vm_area_struct *vma,
				    unsigned long addr, pte_t *ptep)
{
}
#endif

#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)

#endif

#endif /* CONFIG_MMU */

#endif
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/tlbflush.h
1da177e4 LT	3	*
	4	* Copyright (C) 1999-2003 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef _ASMARM_TLBFLUSH_H
	11	#define _ASMARM_TLBFLUSH_H
	12
58e9c47f	13	#ifdef CONFIG_MMU
0157903e	14
1da177e4 LT	15	#include <asm/glue.h>
1da177e4 LT	16
1da177e4 LT	17	#define TLB_V4_U_PAGE (1 << 1)
	18	#define TLB_V4_D_PAGE (1 << 2)
	19	#define TLB_V4_I_PAGE (1 << 3)
	20	#define TLB_V6_U_PAGE (1 << 4)
	21	#define TLB_V6_D_PAGE (1 << 5)
	22	#define TLB_V6_I_PAGE (1 << 6)
	23
1da177e4 LT	24	#define TLB_V4_U_FULL (1 << 9)
	25	#define TLB_V4_D_FULL (1 << 10)
	26	#define TLB_V4_I_FULL (1 << 11)
	27	#define TLB_V6_U_FULL (1 << 12)
	28	#define TLB_V6_D_FULL (1 << 13)
	29	#define TLB_V6_I_FULL (1 << 14)
	30
	31	#define TLB_V6_U_ASID (1 << 16)
	32	#define TLB_V6_D_ASID (1 << 17)
	33	#define TLB_V6_I_ASID (1 << 18)
	34
862c588f WD	35	#define TLB_V6_BP (1 << 19)
862c588f WD	36
faa7bc51	37	/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
862c588f WD	38	#define TLB_V7_UIS_PAGE (1 << 20)
	39	#define TLB_V7_UIS_FULL (1 << 21)
	40	#define TLB_V7_UIS_ASID (1 << 22)
	41	#define TLB_V7_UIS_BP (1 << 23)
faa7bc51	42
4348810a	43	#define TLB_BARRIER (1 << 28)
99c6dc11	44	#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
1da177e4 LT	45	#define TLB_DCLEAN (1 << 30)
	46	#define TLB_WB (1 << 31)
	47
	48	/*
	49	* MMU TLB Model
	50	* =============
	51	*
	52	* We have the following to choose from:
1da177e4 LT	53	* v4 - ARMv4 without write buffer
	54	* v4wb - ARMv4 with write buffer without I TLB flush entry instruction
	55	* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
99c6dc11	56	* fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
4348810a	57	* fa - Faraday (v4 with write buffer with UTLB)
1da177e4	58	* v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
61db7fb1	59	* v7wbi - identical to v6wbi
1da177e4 LT	60	*/
	61	#undef _TLB
	62	#undef MULTI_TLB
	63
f00ec48f RK	64	#ifdef CONFIG_SMP_ON_UP
	65	#define MULTI_TLB 1
	66	#endif
	67
1da177e4 LT	68	#define v4_tlb_flags (TLB_V4_U_FULL \| TLB_V4_U_PAGE)
	69
	70	#ifdef CONFIG_CPU_TLB_V4WT
	71	# define v4_possible_flags v4_tlb_flags
	72	# define v4_always_flags v4_tlb_flags
	73	# ifdef _TLB
	74	# define MULTI_TLB 1
	75	# else
	76	# define _TLB v4
	77	# endif
	78	#else
	79	# define v4_possible_flags 0
	80	# define v4_always_flags (-1UL)
	81	#endif
	82
4348810a	83	#define fa_tlb_flags (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
28853ac8 PZ	84	TLB_V4_U_FULL \| TLB_V4_U_PAGE)
	85
	86	#ifdef CONFIG_CPU_TLB_FA
	87	# define fa_possible_flags fa_tlb_flags
	88	# define fa_always_flags fa_tlb_flags
	89	# ifdef _TLB
	90	# define MULTI_TLB 1
	91	# else
	92	# define _TLB fa
	93	# endif
	94	#else
	95	# define fa_possible_flags 0
	96	# define fa_always_flags (-1UL)
	97	#endif
	98
1da177e4 LT	99	#define v4wbi_tlb_flags (TLB_WB \| TLB_DCLEAN \| \
	100	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
	101	TLB_V4_I_PAGE \| TLB_V4_D_PAGE)
	102
	103	#ifdef CONFIG_CPU_TLB_V4WBI
	104	# define v4wbi_possible_flags v4wbi_tlb_flags
	105	# define v4wbi_always_flags v4wbi_tlb_flags
	106	# ifdef _TLB
	107	# define MULTI_TLB 1
	108	# else
	109	# define _TLB v4wbi
	110	# endif
	111	#else
	112	# define v4wbi_possible_flags 0
	113	# define v4wbi_always_flags (-1UL)
	114	#endif
	115
99c6dc11 LB	116	#define fr_tlb_flags (TLB_WB \| TLB_DCLEAN \| TLB_L2CLEAN_FR \| \
	117	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
	118	TLB_V4_I_PAGE \| TLB_V4_D_PAGE)
	119
	120	#ifdef CONFIG_CPU_TLB_FEROCEON
	121	# define fr_possible_flags fr_tlb_flags
	122	# define fr_always_flags fr_tlb_flags
	123	# ifdef _TLB
	124	# define MULTI_TLB 1
	125	# else
	126	# define _TLB v4wbi
	127	# endif
	128	#else
	129	# define fr_possible_flags 0
	130	# define fr_always_flags (-1UL)
	131	#endif
	132
1da177e4 LT	133	#define v4wb_tlb_flags (TLB_WB \| TLB_DCLEAN \| \
	134	TLB_V4_I_FULL \| TLB_V4_D_FULL \| \
	135	TLB_V4_D_PAGE)
	136
	137	#ifdef CONFIG_CPU_TLB_V4WB
	138	# define v4wb_possible_flags v4wb_tlb_flags
	139	# define v4wb_always_flags v4wb_tlb_flags
	140	# ifdef _TLB
	141	# define MULTI_TLB 1
	142	# else
	143	# define _TLB v4wb
	144	# endif
	145	#else
	146	# define v4wb_possible_flags 0
	147	# define v4wb_always_flags (-1UL)
	148	#endif
	149
4348810a	150	#define v6wbi_tlb_flags (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
1da177e4 LT	151	TLB_V6_I_FULL \| TLB_V6_D_FULL \| \
1da177e4 LT	152	TLB_V6_I_PAGE \| TLB_V6_D_PAGE \| \
862c588f WD	153	TLB_V6_I_ASID \| TLB_V6_D_ASID \| \
862c588f WD	154	TLB_V6_BP)
1da177e4 LT	155
	156	#ifdef CONFIG_CPU_TLB_V6
	157	# define v6wbi_possible_flags v6wbi_tlb_flags
	158	# define v6wbi_always_flags v6wbi_tlb_flags
	159	# ifdef _TLB
	160	# define MULTI_TLB 1
	161	# else
	162	# define _TLB v6wbi
	163	# endif
	164	#else
	165	# define v6wbi_possible_flags 0
	166	# define v6wbi_always_flags (-1UL)
	167	#endif
	168
ae8a8b95	169	#define v7wbi_tlb_flags_smp (TLB_WB \| TLB_BARRIER \| \
862c588f WD	170	TLB_V7_UIS_FULL \| TLB_V7_UIS_PAGE \| \
862c588f WD	171	TLB_V7_UIS_ASID \| TLB_V7_UIS_BP)
4348810a	172	#define v7wbi_tlb_flags_up (TLB_WB \| TLB_DCLEAN \| TLB_BARRIER \| \
862c588f WD	173	TLB_V6_U_FULL \| TLB_V6_U_PAGE \| \
862c588f WD	174	TLB_V6_U_ASID \| TLB_V6_BP)
faa7bc51	175
2ccdd1e7	176	#ifdef CONFIG_CPU_TLB_V7
f00ec48f RK	177
	178	# ifdef CONFIG_SMP_ON_UP
	179	# define v7wbi_possible_flags (v7wbi_tlb_flags_smp \| v7wbi_tlb_flags_up)
	180	# define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
	181	# elif defined(CONFIG_SMP)
	182	# define v7wbi_possible_flags v7wbi_tlb_flags_smp
	183	# define v7wbi_always_flags v7wbi_tlb_flags_smp
	184	# else
	185	# define v7wbi_possible_flags v7wbi_tlb_flags_up
	186	# define v7wbi_always_flags v7wbi_tlb_flags_up
	187	# endif
2ccdd1e7 CM	188	# ifdef _TLB
	189	# define MULTI_TLB 1
	190	# else
	191	# define _TLB v7wbi
	192	# endif
	193	#else
	194	# define v7wbi_possible_flags 0
	195	# define v7wbi_always_flags (-1UL)
	196	#endif
	197
1da177e4 LT	198	#ifndef _TLB
	199	#error Unknown TLB model
	200	#endif
	201
	202	#ifndef __ASSEMBLY__
	203
e8edc6e0 AD	204	#include <linux/sched.h>
e8edc6e0 AD	205
1da177e4 LT	206	struct cpu_tlb_fns {
	207	void (flush_user_range)(unsigned long, unsigned long, struct vm_area_struct );
	208	void (*flush_kern_range)(unsigned long, unsigned long);
	209	unsigned long tlb_flags;
	210	};
	211
	212	/*
	213	* Select the calling method
	214	*/
	215	#ifdef MULTI_TLB
	216
	217	#define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
	218	#define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range
	219
	220	#else
	221
	222	#define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
	223	#define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range)
	224
	225	extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
	226	extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
	227
	228	#endif
	229
	230	extern struct cpu_tlb_fns cpu_tlb;
	231
	232	#define __cpu_tlb_flags cpu_tlb.tlb_flags
	233
	234	/*
	235	* TLB Management
	236	* ==============
	237	*
	238	* The arch/arm/mm/tlb-*.S files implement these methods.
	239	*
	240	* The TLB specific code is expected to perform whatever tests it
	241	* needs to determine if it should invalidate the TLB for each
	242	* call. Start addresses are inclusive and end addresses are
	243	* exclusive; it is safe to round these addresses down.
	244	*
	245	* flush_tlb_all()
	246	*
	247	* Invalidate the entire TLB.
	248	*
	249	* flush_tlb_mm(mm)
	250	*
	251	* Invalidate all TLB entries in a particular address
	252	* space.
	253	* - mm - mm_struct describing address space
	254	*
	255	* flush_tlb_range(mm,start,end)
	256	*
	257	* Invalidate a range of TLB entries in the specified
	258	* address space.
	259	* - mm - mm_struct describing address space
	260	* - start - start address (may not be aligned)
	261	* - end - end address (exclusive, may not be aligned)
	262	*
	263	* flush_tlb_page(vaddr,vma)
	264	*
	265	* Invalidate the specified page in the specified address range.
	266	* - vaddr - virtual address (may not be aligned)
	267	* - vma - vma_struct describing address range
	268	*
	269	* flush_kern_tlb_page(kaddr)
270	*
271	* Invalidate the TLB entry for the specified page. The address
272	* will be in the kernels virtual memory space. Current uses
273	* only require the D-TLB to be invalidated.
274	* - kaddr - Kernel virtual memory address
275	*/
276
277	/*
278	* We optimise the code below by:
279	* - building a set of TLB flags that might be set in __cpu_tlb_flags
280	* - building a set of TLB flags that will always be set in __cpu_tlb_flags
281	* - if we're going to need __cpu_tlb_flags, access it once and only once
282	*
283	* This allows us to build optimal assembly for the single-CPU type case,
284	* and as close to optimal given the compiler constrants for multi-CPU
285	* case. We could do better for the multi-CPU case if the compiler
286	* implemented the "%?" method, but this has been discontinued due to too
287	* many people getting it wrong.
288	*/
357c9c1f	289	#define possible_tlb_flags (v4_possible_flags \| \
1da177e4	290	v4wbi_possible_flags \| \
99c6dc11	291	fr_possible_flags \| \
1da177e4	292	v4wb_possible_flags \| \
28853ac8	293	fa_possible_flags \| \
61db7fb1 PW	294	v6wbi_possible_flags \| \
61db7fb1 PW	295	v7wbi_possible_flags)
1da177e4	296
357c9c1f	297	#define always_tlb_flags (v4_always_flags & \
1da177e4	298	v4wbi_always_flags & \
99c6dc11	299	fr_always_flags & \
1da177e4	300	v4wb_always_flags & \
28853ac8	301	fa_always_flags & \
61db7fb1 PW	302	v6wbi_always_flags & \
61db7fb1 PW	303	v7wbi_always_flags)
1da177e4 LT	304
	305	#define tlb_flag(f) ((always_tlb_flags & (f)) \|\| (__tlb_flag & possible_tlb_flags & (f)))
	306
87067a93 RK	307	#define __tlb_op(f, insnarg, arg) \
	308	do { \
	309	if (always_tlb_flags & (f)) \
	310	asm("mcr " insnarg \
	311	: : "r" (arg) : "cc"); \
	312	else if (possible_tlb_flags & (f)) \
	313	asm("tst %1, %2\n\t" \
	314	"mcrne " insnarg \
	315	: : "r" (arg), "r" (__tlb_flag), "Ir" (f) \
	316	: "cc"); \
	317	} while (0)
	318
	319	#define tlb_op(f, regs, arg) __tlb_op(f, "p15, 0, %0, " regs, arg)
	320	#define tlb_l2_op(f, regs, arg) __tlb_op(f, "p15, 1, %0, " regs, arg)
	321
603fff54	322	static inline void local_flush_tlb_all(void)
1da177e4 LT	323	{
	324	const int zero = 0;
	325	const unsigned int __tlb_flag = __cpu_tlb_flags;
	326
	327	if (tlb_flag(TLB_WB))
e6a5d66f	328	dsb();
1da177e4	329
87067a93 RK	330	tlb_op(TLB_V4_U_FULL \| TLB_V6_U_FULL, "c8, c7, 0", zero);
	331	tlb_op(TLB_V4_D_FULL \| TLB_V6_D_FULL, "c8, c6, 0", zero);
	332	tlb_op(TLB_V4_I_FULL \| TLB_V6_I_FULL, "c8, c5, 0", zero);
	333	tlb_op(TLB_V7_UIS_FULL, "c8, c3, 0", zero);
e6a5d66f	334
4348810a	335	if (tlb_flag(TLB_BARRIER)) {
b8349b56 CM	336	dsb();
	337	isb();
	338	}
1da177e4 LT	339	}
1da177e4 LT	340
603fff54	341	static inline void local_flush_tlb_mm(struct mm_struct *mm)
1da177e4 LT	342	{
	343	const int zero = 0;
	344	const int asid = ASID(mm);
	345	const unsigned int __tlb_flag = __cpu_tlb_flags;
	346
	347	if (tlb_flag(TLB_WB))
e6a5d66f	348	dsb();
1da177e4	349
4cc3daaf	350	if (possible_tlb_flags & (TLB_V4_U_FULL\|TLB_V4_D_FULL\|TLB_V4_I_FULL)) {
87067a93	351	if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
87067a93 RK	352	tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);
	353	tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);
	354	tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
	355	}
	356	put_cpu();
1da177e4	357	}
87067a93 RK	358
	359	tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid);
	360	tlb_op(TLB_V6_D_ASID, "c8, c6, 2", asid);
	361	tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid);
cdf357f1	362	#ifdef CONFIG_ARM_ERRATA_720789
87067a93	363	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 0", zero);
cdf357f1	364	#else
87067a93	365	tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", asid);
cdf357f1	366	#endif
e6a5d66f	367
4348810a	368	if (tlb_flag(TLB_BARRIER))
b8349b56	369	dsb();
1da177e4 LT	370	}
	371
	372	static inline void
603fff54	373	local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
1da177e4 LT	374	{
	375	const int zero = 0;
	376	const unsigned int __tlb_flag = __cpu_tlb_flags;
	377
	378	uaddr = (uaddr & PAGE_MASK) \| ASID(vma->vm_mm);
	379
	380	if (tlb_flag(TLB_WB))
e6a5d66f	381	dsb();
1da177e4	382
4cc3daaf	383	if (possible_tlb_flags & (TLB_V4_U_PAGE\|TLB_V4_D_PAGE\|TLB_V4_I_PAGE\|TLB_V4_I_FULL) &&
87067a93	384	cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
87067a93 RK	385	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);
	386	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);
	387	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
1da177e4	388	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
6a39dd62	389	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
1da177e4 LT	390	}
1da177e4 LT	391
87067a93 RK	392	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr);
	393	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", uaddr);
	394	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr);
cdf357f1	395	#ifdef CONFIG_ARM_ERRATA_720789
87067a93	396	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 3", uaddr & PAGE_MASK);
cdf357f1	397	#else
87067a93	398	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", uaddr);
cdf357f1	399	#endif
e6a5d66f	400
4348810a	401	if (tlb_flag(TLB_BARRIER))
b8349b56	402	dsb();
1da177e4 LT	403	}
1da177e4 LT	404
603fff54	405	static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
1da177e4 LT	406	{
	407	const int zero = 0;
	408	const unsigned int __tlb_flag = __cpu_tlb_flags;
	409
	410	kaddr &= PAGE_MASK;
	411
	412	if (tlb_flag(TLB_WB))
e6a5d66f	413	dsb();
1da177e4	414
87067a93 RK	415	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);
	416	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);
	417	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);
1da177e4	418	if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
6a39dd62	419	asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
1da177e4	420
87067a93 RK	421	tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr);
	422	tlb_op(TLB_V6_D_PAGE, "c8, c6, 1", kaddr);
	423	tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr);
	424	tlb_op(TLB_V7_UIS_PAGE, "c8, c3, 1", kaddr);
6a0e2430	425
4348810a	426	if (tlb_flag(TLB_BARRIER)) {
b8349b56 CM	427	dsb();
	428	isb();
	429	}
1da177e4 LT	430	}
1da177e4 LT	431
862c588f WD	432	static inline void local_flush_bp_all(void)
	433	{
	434	const int zero = 0;
	435	const unsigned int __tlb_flag = __cpu_tlb_flags;
	436
	437	if (tlb_flag(TLB_V7_UIS_BP))
	438	asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
	439	else if (tlb_flag(TLB_V6_BP))
	440	asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
	441
	442	if (tlb_flag(TLB_BARRIER))
	443	isb();
	444	}
	445
93dc6887 CM	446	#ifdef CONFIG_ARM_ERRATA_798181
	447	static inline void dummy_flush_tlb_a15_erratum(void)
	448	{
	449	/*
	450	* Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
	451	*/
	452	asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
	453	dsb();
	454	}
	455	#else
	456	static inline void dummy_flush_tlb_a15_erratum(void)
	457	{
	458	}
	459	#endif
	460
1da177e4 LT	461	/*
	462	* flush_pmd_entry
	463	*
	464	* Flush a PMD entry (word aligned, or double-word aligned) to
	465	* RAM if the TLB for the CPU we are running on requires this.
	466	* This is typically used when we are creating PMD entries.
	467	*
	468	* clean_pmd_entry
	469	*
	470	* Clean (but don't drain the write buffer) if the CPU requires
	471	* these operations. This is typically used when we are removing
	472	* PMD entries.
	473	*/
442e70c0	474	static inline void flush_pmd_entry(void *pmd)
1da177e4	475	{
1da177e4 LT	476	const unsigned int __tlb_flag = __cpu_tlb_flags;
1da177e4 LT	477
87067a93 RK	478	tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
87067a93 RK	479	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
99c6dc11	480
1da177e4	481	if (tlb_flag(TLB_WB))
e6a5d66f	482	dsb();
1da177e4 LT	483	}
1da177e4 LT	484
442e70c0	485	static inline void clean_pmd_entry(void *pmd)
1da177e4 LT	486	{
	487	const unsigned int __tlb_flag = __cpu_tlb_flags;
	488
87067a93 RK	489	tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd);
87067a93 RK	490	tlb_l2_op(TLB_L2CLEAN_FR, "c15, c9, 1 @ L2 flush_pmd", pmd);
1da177e4 LT	491	}
1da177e4 LT	492
87067a93	493	#undef tlb_op
1da177e4 LT	494	#undef tlb_flag
	495	#undef always_tlb_flags
	496	#undef possible_tlb_flags
	497
	498	/*
	499	* Convert calls to our calling convention.
	500	*/
603fff54 RK	501	#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
	502	#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
	503
	504	#ifndef CONFIG_SMP
	505	#define flush_tlb_all local_flush_tlb_all
	506	#define flush_tlb_mm local_flush_tlb_mm
	507	#define flush_tlb_page local_flush_tlb_page
	508	#define flush_tlb_kernel_page local_flush_tlb_kernel_page
	509	#define flush_tlb_range local_flush_tlb_range
	510	#define flush_tlb_kernel_range local_flush_tlb_kernel_range
862c588f	511	#define flush_bp_all local_flush_bp_all
603fff54 RK	512	#else
	513	extern void flush_tlb_all(void);
	514	extern void flush_tlb_mm(struct mm_struct *mm);
	515	extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
	516	extern void flush_tlb_kernel_page(unsigned long kaddr);
	517	extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
	518	extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
862c588f	519	extern void flush_bp_all(void);
603fff54	520	#endif
1da177e4 LT	521
1da177e4 LT	522	/*
c0177800	523	* If PG_dcache_clean is not set for the page, we need to ensure that any
1da177e4	524	* cache entries for the kernels virtual memory range are written
6012191a CM	525	* back to the page. On ARMv6 and later, the cache coherency is handled via
6012191a CM	526	* the set_pte_at() function.
1da177e4	527	*/
6012191a	528	#if __LINUX_ARM_ARCH__ < 6
4b3073e1 RK	529	extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
4b3073e1 RK	530	pte_t *ptep);
6012191a CM	531	#else
	532	static inline void update_mmu_cache(struct vm_area_struct *vma,
	533	unsigned long addr, pte_t *ptep)
	534	{
	535	}
	536	#endif
1da177e4	537
8d962507 CM	538	#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
8d962507 CM	539
1da177e4 LT	540	#endif
1da177e4 LT	541
0157903e HC	542	#endif /* CONFIG_MMU */
0157903e HC	543
1da177e4	544	#endif