Commit | Line | Data |
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1da177e4 | 1 | /* |
4baa9922 | 2 | * arch/arm/include/asm/vfp.h |
1da177e4 LT |
3 | * |
4 | * VFP register definitions. | |
5 | * First, the standard VFP set. | |
6 | */ | |
7 | ||
e7f0f376 FF |
8 | #ifndef __ASM_VFP_H |
9 | #define __ASM_VFP_H | |
10 | ||
1da177e4 LT |
11 | #define FPSID cr0 |
12 | #define FPSCR cr1 | |
25ebee02 CM |
13 | #define MVFR1 cr6 |
14 | #define MVFR0 cr7 | |
1da177e4 | 15 | #define FPEXC cr8 |
c98929c0 CM |
16 | #define FPINST cr9 |
17 | #define FPINST2 cr10 | |
1da177e4 LT |
18 | |
19 | /* FPSID bits */ | |
20 | #define FPSID_IMPLEMENTER_BIT (24) | |
21 | #define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT) | |
22 | #define FPSID_SOFTWARE (1<<23) | |
23 | #define FPSID_FORMAT_BIT (21) | |
24 | #define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT) | |
25 | #define FPSID_NODOUBLE (1<<20) | |
26 | #define FPSID_ARCH_BIT (16) | |
27 | #define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) | |
6c96a4a6 | 28 | #define FPSID_CPUID_ARCH_MASK (0x7F << FPSID_ARCH_BIT) |
1da177e4 LT |
29 | #define FPSID_PART_BIT (8) |
30 | #define FPSID_PART_MASK (0xFF << FPSID_PART_BIT) | |
31 | #define FPSID_VARIANT_BIT (4) | |
32 | #define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) | |
33 | #define FPSID_REV_BIT (0) | |
34 | #define FPSID_REV_MASK (0xF << FPSID_REV_BIT) | |
35 | ||
36 | /* FPEXC bits */ | |
228adef1 RK |
37 | #define FPEXC_EX (1 << 31) |
38 | #define FPEXC_EN (1 << 30) | |
c98929c0 CM |
39 | #define FPEXC_DEX (1 << 29) |
40 | #define FPEXC_FP2V (1 << 28) | |
41 | #define FPEXC_VV (1 << 27) | |
42 | #define FPEXC_TFV (1 << 26) | |
43 | #define FPEXC_LENGTH_BIT (8) | |
44 | #define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) | |
45 | #define FPEXC_IDF (1 << 7) | |
46 | #define FPEXC_IXF (1 << 4) | |
47 | #define FPEXC_UFF (1 << 3) | |
48 | #define FPEXC_OFF (1 << 2) | |
49 | #define FPEXC_DZF (1 << 1) | |
50 | #define FPEXC_IOF (1 << 0) | |
51 | #define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF) | |
1da177e4 LT |
52 | |
53 | /* FPSCR bits */ | |
54 | #define FPSCR_DEFAULT_NAN (1<<25) | |
55 | #define FPSCR_FLUSHTOZERO (1<<24) | |
56 | #define FPSCR_ROUND_NEAREST (0<<22) | |
57 | #define FPSCR_ROUND_PLUSINF (1<<22) | |
58 | #define FPSCR_ROUND_MINUSINF (2<<22) | |
59 | #define FPSCR_ROUND_TOZERO (3<<22) | |
60 | #define FPSCR_RMODE_BIT (22) | |
61 | #define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) | |
62 | #define FPSCR_STRIDE_BIT (20) | |
63 | #define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) | |
64 | #define FPSCR_LENGTH_BIT (16) | |
65 | #define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) | |
66 | #define FPSCR_IOE (1<<8) | |
67 | #define FPSCR_DZE (1<<9) | |
68 | #define FPSCR_OFE (1<<10) | |
69 | #define FPSCR_UFE (1<<11) | |
70 | #define FPSCR_IXE (1<<12) | |
71 | #define FPSCR_IDE (1<<15) | |
72 | #define FPSCR_IOC (1<<0) | |
73 | #define FPSCR_DZC (1<<1) | |
74 | #define FPSCR_OFC (1<<2) | |
75 | #define FPSCR_UFC (1<<3) | |
76 | #define FPSCR_IXC (1<<4) | |
77 | #define FPSCR_IDC (1<<7) | |
78 | ||
25ebee02 CM |
79 | /* MVFR0 bits */ |
80 | #define MVFR0_A_SIMD_BIT (0) | |
81 | #define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT) | |
6c96a4a6 SB |
82 | #define MVFR0_SP_BIT (4) |
83 | #define MVFR0_SP_MASK (0xf << MVFR0_SP_BIT) | |
84 | #define MVFR0_DP_BIT (8) | |
85 | #define MVFR0_DP_MASK (0xf << MVFR0_DP_BIT) | |
25ebee02 | 86 | |
1da177e4 LT |
87 | /* Bit patterns for decoding the packaged operation descriptors */ |
88 | #define VFPOPDESC_LENGTH_BIT (9) | |
89 | #define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT) | |
90 | #define VFPOPDESC_UNUSED_BIT (24) | |
91 | #define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT) | |
92 | #define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK)) | |
e7f0f376 | 93 | |
7d7d7a41 FF |
94 | #ifndef __ASSEMBLY__ |
95 | void vfp_disable(void); | |
96 | #endif | |
97 | ||
e7f0f376 | 98 | #endif /* __ASM_VFP_H */ |