projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| 4baa9922 | 2 | * arch/arm/include/asm/vfp.h |
| 1da177e4 LT |
3 | * |
| 4 | * VFP register definitions. | |
| 5 | * First, the standard VFP set. | |
| 6 | */ | |
| 7 | ||
| 8 | #define FPSID cr0 | |
| 9 | #define FPSCR cr1 | |
| 25ebee02 CM |
10 | #define MVFR1 cr6 |
| 11 | #define MVFR0 cr7 | |
| 1da177e4 | 12 | #define FPEXC cr8 |
| c98929c0 CM |
13 | #define FPINST cr9 |
| 14 | #define FPINST2 cr10 | |
| 1da177e4 LT |
15 | |
| 16 | /* FPSID bits */ | |
| 17 | #define FPSID_IMPLEMENTER_BIT (24) | |
| 18 | #define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT) | |
| 19 | #define FPSID_SOFTWARE (1<<23) | |
| 20 | #define FPSID_FORMAT_BIT (21) | |
| 21 | #define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT) | |
| 22 | #define FPSID_NODOUBLE (1<<20) | |
| 23 | #define FPSID_ARCH_BIT (16) | |
| 24 | #define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) | |
| 6c96a4a6 | 25 | #define FPSID_CPUID_ARCH_MASK (0x7F << FPSID_ARCH_BIT) |
| 1da177e4 LT |
26 | #define FPSID_PART_BIT (8) |
| 27 | #define FPSID_PART_MASK (0xFF << FPSID_PART_BIT) | |
| 28 | #define FPSID_VARIANT_BIT (4) | |
| 29 | #define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) | |
| 30 | #define FPSID_REV_BIT (0) | |
| 31 | #define FPSID_REV_MASK (0xF << FPSID_REV_BIT) | |
| 32 | ||
| 33 | /* FPEXC bits */ | |
| 228adef1 RK |
34 | #define FPEXC_EX (1 << 31) |
| 35 | #define FPEXC_EN (1 << 30) | |
| c98929c0 CM |
36 | #define FPEXC_DEX (1 << 29) |
| 37 | #define FPEXC_FP2V (1 << 28) | |
| 38 | #define FPEXC_VV (1 << 27) | |
| 39 | #define FPEXC_TFV (1 << 26) | |
| 40 | #define FPEXC_LENGTH_BIT (8) | |
| 41 | #define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) | |
| 42 | #define FPEXC_IDF (1 << 7) | |
| 43 | #define FPEXC_IXF (1 << 4) | |
| 44 | #define FPEXC_UFF (1 << 3) | |
| 45 | #define FPEXC_OFF (1 << 2) | |
| 46 | #define FPEXC_DZF (1 << 1) | |
| 47 | #define FPEXC_IOF (1 << 0) | |
| 48 | #define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF) | |
| 1da177e4 LT |
49 | |
| 50 | /* FPSCR bits */ | |
| 51 | #define FPSCR_DEFAULT_NAN (1<<25) | |
| 52 | #define FPSCR_FLUSHTOZERO (1<<24) | |
| 53 | #define FPSCR_ROUND_NEAREST (0<<22) | |
| 54 | #define FPSCR_ROUND_PLUSINF (1<<22) | |
| 55 | #define FPSCR_ROUND_MINUSINF (2<<22) | |
| 56 | #define FPSCR_ROUND_TOZERO (3<<22) | |
| 57 | #define FPSCR_RMODE_BIT (22) | |
| 58 | #define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) | |
| 59 | #define FPSCR_STRIDE_BIT (20) | |
| 60 | #define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) | |
| 61 | #define FPSCR_LENGTH_BIT (16) | |
| 62 | #define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) | |
| 63 | #define FPSCR_IOE (1<<8) | |
| 64 | #define FPSCR_DZE (1<<9) | |
| 65 | #define FPSCR_OFE (1<<10) | |
| 66 | #define FPSCR_UFE (1<<11) | |
| 67 | #define FPSCR_IXE (1<<12) | |
| 68 | #define FPSCR_IDE (1<<15) | |
| 69 | #define FPSCR_IOC (1<<0) | |
| 70 | #define FPSCR_DZC (1<<1) | |
| 71 | #define FPSCR_OFC (1<<2) | |
| 72 | #define FPSCR_UFC (1<<3) | |
| 73 | #define FPSCR_IXC (1<<4) | |
| 74 | #define FPSCR_IDC (1<<7) | |
| 75 | ||
| 25ebee02 CM |
76 | /* MVFR0 bits */ |
| 77 | #define MVFR0_A_SIMD_BIT (0) | |
| 78 | #define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT) | |
| 6c96a4a6 SB |
79 | #define MVFR0_SP_BIT (4) |
| 80 | #define MVFR0_SP_MASK (0xf << MVFR0_SP_BIT) | |
| 81 | #define MVFR0_DP_BIT (8) | |
| 82 | #define MVFR0_DP_MASK (0xf << MVFR0_DP_BIT) | |
| 25ebee02 | 83 | |
| 1da177e4 LT |
84 | /* Bit patterns for decoding the packaged operation descriptors */ |
| 85 | #define VFPOPDESC_LENGTH_BIT (9) | |
| 86 | #define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT) | |
| 87 | #define VFPOPDESC_UNUSED_BIT (24) | |
| 88 | #define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT) | |
| 89 | #define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK)) |