projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f8c95fe6 | 1 | /* |
| 52d7aec2 | 2 | * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. |
| f8c95fe6 SG |
3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef __DEBUG_IMX_UART_H | |
| 10 | #define __DEBUG_IMX_UART_H | |
| 11 | ||
| 12 | #define IMX1_UART1_BASE_ADDR 0x00206000 | |
| 13 | #define IMX1_UART2_BASE_ADDR 0x00207000 | |
| 14 | #define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR | |
| 15 | #define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n) | |
| 16 | ||
| 17 | #define IMX21_UART1_BASE_ADDR 0x1000a000 | |
| 18 | #define IMX21_UART2_BASE_ADDR 0x1000b000 | |
| 19 | #define IMX21_UART3_BASE_ADDR 0x1000c000 | |
| 20 | #define IMX21_UART4_BASE_ADDR 0x1000d000 | |
| 21 | #define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR | |
| 22 | #define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n) | |
| 23 | ||
| 24 | #define IMX25_UART1_BASE_ADDR 0x43f90000 | |
| 25 | #define IMX25_UART2_BASE_ADDR 0x43f94000 | |
| 26 | #define IMX25_UART3_BASE_ADDR 0x5000c000 | |
| 27 | #define IMX25_UART4_BASE_ADDR 0x50008000 | |
| 28 | #define IMX25_UART5_BASE_ADDR 0x5002c000 | |
| 29 | #define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR | |
| 30 | #define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n) | |
| 31 | ||
| 32 | #define IMX31_UART1_BASE_ADDR 0x43f90000 | |
| 33 | #define IMX31_UART2_BASE_ADDR 0x43f94000 | |
| 34 | #define IMX31_UART3_BASE_ADDR 0x5000c000 | |
| 35 | #define IMX31_UART4_BASE_ADDR 0x43fb0000 | |
| 36 | #define IMX31_UART5_BASE_ADDR 0x43fb4000 | |
| 37 | #define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR | |
| 38 | #define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n) | |
| 39 | ||
| 40 | #define IMX35_UART1_BASE_ADDR 0x43f90000 | |
| 41 | #define IMX35_UART2_BASE_ADDR 0x43f94000 | |
| 42 | #define IMX35_UART3_BASE_ADDR 0x5000c000 | |
| 43 | #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR | |
| 44 | #define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) | |
| 45 | ||
| ad364a70 GU |
46 | #define IMX50_UART1_BASE_ADDR 0x53fbc000 |
| 47 | #define IMX50_UART2_BASE_ADDR 0x53fc0000 | |
| 48 | #define IMX50_UART3_BASE_ADDR 0x5000c000 | |
| 49 | #define IMX50_UART4_BASE_ADDR 0x53ff0000 | |
| 50 | #define IMX50_UART5_BASE_ADDR 0x63f90000 | |
| 51 | #define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR | |
| 52 | #define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n) | |
| 53 | ||
| f8c95fe6 SG |
54 | #define IMX51_UART1_BASE_ADDR 0x73fbc000 |
| 55 | #define IMX51_UART2_BASE_ADDR 0x73fc0000 | |
| 56 | #define IMX51_UART3_BASE_ADDR 0x7000c000 | |
| 57 | #define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR | |
| 58 | #define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n) | |
| 59 | ||
| 60 | #define IMX53_UART1_BASE_ADDR 0x53fbc000 | |
| 61 | #define IMX53_UART2_BASE_ADDR 0x53fc0000 | |
| 62 | #define IMX53_UART3_BASE_ADDR 0x5000c000 | |
| 63 | #define IMX53_UART4_BASE_ADDR 0x53ff0000 | |
| 64 | #define IMX53_UART5_BASE_ADDR 0x63f90000 | |
| 65 | #define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR | |
| 66 | #define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n) | |
| 67 | ||
| 68 | #define IMX6Q_UART1_BASE_ADDR 0x02020000 | |
| 69 | #define IMX6Q_UART2_BASE_ADDR 0x021e8000 | |
| 70 | #define IMX6Q_UART3_BASE_ADDR 0x021ec000 | |
| 71 | #define IMX6Q_UART4_BASE_ADDR 0x021f0000 | |
| 72 | #define IMX6Q_UART5_BASE_ADDR 0x021f4000 | |
| 73 | #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR | |
| 74 | #define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) | |
| 75 | ||
| 34e8a16b SG |
76 | #define IMX6SL_UART1_BASE_ADDR 0x02020000 |
| 77 | #define IMX6SL_UART2_BASE_ADDR 0x02024000 | |
| 78 | #define IMX6SL_UART3_BASE_ADDR 0x02034000 | |
| 79 | #define IMX6SL_UART4_BASE_ADDR 0x02038000 | |
| 80 | #define IMX6SL_UART5_BASE_ADDR 0x02018000 | |
| 81 | #define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR | |
| 82 | #define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n) | |
| 83 | ||
| 74368e81 SG |
84 | #define IMX6SX_UART1_BASE_ADDR 0x02020000 |
| 85 | #define IMX6SX_UART2_BASE_ADDR 0x021e8000 | |
| 86 | #define IMX6SX_UART3_BASE_ADDR 0x021ec000 | |
| 87 | #define IMX6SX_UART4_BASE_ADDR 0x021f0000 | |
| 88 | #define IMX6SX_UART5_BASE_ADDR 0x021f4000 | |
| 89 | #define IMX6SX_UART6_BASE_ADDR 0x022a0000 | |
| 90 | #define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR | |
| 91 | #define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n) | |
| 92 | ||
| 20c305f6 AH |
93 | #define IMX6UL_UART1_BASE_ADDR 0x02020000 |
| 94 | #define IMX6UL_UART2_BASE_ADDR 0x021e8000 | |
| 95 | #define IMX6UL_UART3_BASE_ADDR 0x021ec000 | |
| 96 | #define IMX6UL_UART4_BASE_ADDR 0x021f0000 | |
| 97 | #define IMX6UL_UART5_BASE_ADDR 0x021f4000 | |
| 98 | #define IMX6UL_UART6_BASE_ADDR 0x021fc000 | |
| 99 | #define IMX6UL_UART7_BASE_ADDR 0x02018000 | |
| 100 | #define IMX6UL_UART8_BASE_ADDR 0x02024000 | |
| 101 | #define IMX6UL_UART_BASE_ADDR(n) IMX6UL_UART##n##_BASE_ADDR | |
| 102 | #define IMX6UL_UART_BASE(n) IMX6UL_UART_BASE_ADDR(n) | |
| 103 | ||
| 52d7aec2 AH |
104 | #define IMX7D_UART1_BASE_ADDR 0x30860000 |
| 105 | #define IMX7D_UART2_BASE_ADDR 0x30890000 | |
| 106 | #define IMX7D_UART3_BASE_ADDR 0x30880000 | |
| 107 | #define IMX7D_UART4_BASE_ADDR 0x30a60000 | |
| 108 | #define IMX7D_UART5_BASE_ADDR 0x30a70000 | |
| 109 | #define IMX7D_UART6_BASE_ADDR 0x30a80000 | |
| 110 | #define IMX7D_UART7_BASE_ADDR 0x30a90000 | |
| 111 | #define IMX7D_UART_BASE_ADDR(n) IMX7D_UART##n##_BASE_ADDR | |
| 112 | #define IMX7D_UART_BASE(n) IMX7D_UART_BASE_ADDR(n) | |
| 113 | ||
| f8c95fe6 SG |
114 | #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) |
| 115 | ||
| 116 | #ifdef CONFIG_DEBUG_IMX1_UART | |
| 117 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX1) | |
| 118 | #elif defined(CONFIG_DEBUG_IMX21_IMX27_UART) | |
| 119 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX21) | |
| 120 | #elif defined(CONFIG_DEBUG_IMX25_UART) | |
| 121 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX25) | |
| 122 | #elif defined(CONFIG_DEBUG_IMX31_UART) | |
| 123 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) | |
| 124 | #elif defined(CONFIG_DEBUG_IMX35_UART) | |
| 125 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX35) | |
| ad364a70 GU |
126 | #elif defined(CONFIG_DEBUG_IMX50_UART) |
| 127 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX50) | |
| f8c95fe6 SG |
128 | #elif defined(CONFIG_DEBUG_IMX51_UART) |
| 129 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX51) | |
| 130 | #elif defined(CONFIG_DEBUG_IMX53_UART) | |
| 131 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) | |
| 132 | #elif defined(CONFIG_DEBUG_IMX6Q_UART) | |
| 133 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) | |
| 34e8a16b SG |
134 | #elif defined(CONFIG_DEBUG_IMX6SL_UART) |
| 135 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) | |
| 74368e81 SG |
136 | #elif defined(CONFIG_DEBUG_IMX6SX_UART) |
| 137 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX) | |
| 20c305f6 AH |
138 | #elif defined(CONFIG_DEBUG_IMX6UL_UART) |
| 139 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6UL) | |
| 52d7aec2 AH |
140 | #elif defined(CONFIG_DEBUG_IMX7D_UART) |
| 141 | #define UART_PADDR IMX_DEBUG_UART_BASE(IMX7D) | |
| 142 | ||
| f8c95fe6 SG |
143 | #endif |
| 144 | ||
| 145 | #endif /* __DEBUG_IMX_UART_H */ |