[deliverable/linux.git] / arch / arm / include / debug / msm.S

/*
 *
 * Copyright (C) 2007 Google, Inc.
 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
 * Author: Brian Swetland <swetland@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

	.macro	addruart, rp, rv, tmp
	ldr	\rp, =CONFIG_DEBUG_UART_PHYS
	ldr	\rv, =CONFIG_DEBUG_UART_VIRT
	.endm

	.macro	senduart, rd, rx
ARM_BE8(rev	\rd, \rd )
	@ Write the 1 character to UARTDM_TF
	str	\rd, [\rx, #0x70]
	.endm

	.macro	waituart, rd, rx
	@ check for TX_EMT in UARTDM_SR
	ldr	\rd, [\rx, #0x08]
ARM_BE8(rev     \rd, \rd )
	tst	\rd, #0x08
	bne	1002f
	@ wait for TXREADY in UARTDM_ISR
1001:	ldr	\rd, [\rx, #0x14]
ARM_BE8(rev     \rd, \rd )
	tst	\rd, #0x80
	beq 	1001b
1002:
	@ Clear TX_READY by writing to the UARTDM_CR register
	mov	\rd, #0x300
ARM_BE8(rev     \rd, \rd )
	str	\rd, [\rx, #0x10]
	@ Write 0x1 to NCF register
	mov 	\rd, #0x1
ARM_BE8(rev     \rd, \rd )
	str	\rd, [\rx, #0x40]
	@ UARTDM reg. Read to induce delay
	ldr	\rd, [\rx, #0x08]
	.endm

	.macro	busyuart, rd, rx
	.endm
Commit	Line	Data
650e3f0d	1	/*
3042102a BS	2	*
3042102a BS	3	* Copyright (C) 2007 Google, Inc.
a3d3ef9d	4	* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3042102a BS	5	* Author: Brian Swetland <swetland@google.com>
	6	*
	7	* This software is licensed under the terms of the GNU General Public
	8	* License version 2, as published by the Free Software Foundation, and
	9	* may be copied, distributed, and modified under those terms.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	*/
	17
639da5ee	18	.macro addruart, rp, rv, tmp
7098cff2 II	19	ldr \rp, =CONFIG_DEBUG_UART_PHYS
7098cff2 II	20	ldr \rv, =CONFIG_DEBUG_UART_VIRT
3042102a BS	21	.endm
3042102a BS	22
a3d3ef9d	23	.macro senduart, rd, rx
9edb4b13	24	ARM_BE8(rev \rd, \rd )
a3d3ef9d SB	25	@ Write the 1 character to UARTDM_TF
a3d3ef9d SB	26	str \rd, [\rx, #0x70]
3042102a BS	27	.endm
3042102a BS	28
a3d3ef9d	29	.macro waituart, rd, rx
a3d3ef9d SB	30	@ check for TX_EMT in UARTDM_SR
a3d3ef9d SB	31	ldr \rd, [\rx, #0x08]
9edb4b13	32	ARM_BE8(rev \rd, \rd )
a3d3ef9d SB	33	tst \rd, #0x08
	34	bne 1002f
	35	@ wait for TXREADY in UARTDM_ISR
	36	1001: ldr \rd, [\rx, #0x14]
9edb4b13	37	ARM_BE8(rev \rd, \rd )
a3d3ef9d SB	38	tst \rd, #0x80
	39	beq 1001b
	40	1002:
	41	@ Clear TX_READY by writing to the UARTDM_CR register
	42	mov \rd, #0x300
9edb4b13	43	ARM_BE8(rev \rd, \rd )
a3d3ef9d SB	44	str \rd, [\rx, #0x10]
	45	@ Write 0x1 to NCF register
	46	mov \rd, #0x1
9edb4b13	47	ARM_BE8(rev \rd, \rd )
a3d3ef9d SB	48	str \rd, [\rx, #0x40]
	49	@ UARTDM reg. Read to induce delay
	50	ldr \rd, [\rx, #0x08]
6339f669	51	.endm
bcd72c3e	52
a3d3ef9d	53	.macro busyuart, rd, rx
bcd72c3e	54	.endm