[deliverable/linux.git] / arch / arm / include / debug / zynq.S

/*
 * Debugging macro include header
 *
 *  Copyright (C) 2011 Xilinx
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#define UART_CR_OFFSET		0x00  /* Control Register [8:0] */
#define UART_SR_OFFSET		0x2C  /* Channel Status [11:0] */
#define UART_FIFO_OFFSET	0x30  /* FIFO [15:0] or [7:0] */

#define UART_SR_TXFULL		0x00000010	/* TX FIFO full */
#define UART_SR_TXEMPTY		0x00000008	/* TX FIFO empty */

#define UART0_PHYS		0xE0000000
#define UART1_PHYS		0xE0001000
#define UART_SIZE		SZ_4K
#define UART_VIRT		0xF0001000

#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
# define LL_UART_PADDR		UART1_PHYS
#else
# define LL_UART_PADDR		UART0_PHYS
#endif

#define LL_UART_VADDR		UART_VIRT

		.macro	addruart, rp, rv, tmp
		ldr	\rp, =LL_UART_PADDR	@ physical
		ldr	\rv, =LL_UART_VADDR	@ virtual
		.endm

		.macro	senduart,rd,rx
		str	\rd, [\rx, #UART_FIFO_OFFSET]	@ TXDATA
		.endm

		.macro	waituart,rd,rx
		.endm

		.macro	busyuart,rd,rx
1002:		ldr	\rd, [\rx, #UART_SR_OFFSET]	@ get status register
		tst	\rd, #UART_SR_TXFULL		@
		bne	1002b			@ wait if FIFO is full
		.endm
Commit	Line	Data
385f02b1	1	/*
b85a3ef4 JL	2	* Debugging macro include header
	3	*
	4	* Copyright (C) 2011 Xilinx
	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
9a45eb69 JC	15	#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
	16	#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
	17	#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
b85a3ef4	18
9a45eb69 JC	19	#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
	20	#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
	21
	22	#define UART0_PHYS 0xE0000000
	23	#define UART1_PHYS 0xE0001000
	24	#define UART_SIZE SZ_4K
	25	#define UART_VIRT 0xF0001000
	26
	27	#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
	28	# define LL_UART_PADDR UART1_PHYS
	29	#else
	30	# define LL_UART_PADDR UART0_PHYS
	31	#endif
	32
	33	#define LL_UART_VADDR UART_VIRT
b85a3ef4	34
639da5ee	35	.macro addruart, rp, rv, tmp
b85a3ef4 JL	36	ldr \rp, =LL_UART_PADDR @ physical
	37	ldr \rv, =LL_UART_VADDR @ virtual
	38	.endm
	39
	40	.macro senduart,rd,rx
	41	str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
	42	.endm
	43
	44	.macro waituart,rd,rx
	45	.endm
	46
	47	.macro busyuart,rd,rx
	48	1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
	49	tst \rd, #UART_SR_TXFULL @
	50	bne 1002b @ wait if FIFO is full
	51	.endm