[deliverable/linux.git] / arch / arm / kernel / bios32.c

/*
 *  linux/arch/arm/kernel/bios32.c
 *
 *  PCI bios-type initialisation for PCI machines
 *
 *  Bits taken from various places.
 */
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/io.h>

#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>

static int debug_pci;

/*
 * We can't use pci_get_device() here since we are
 * called from interrupt context.
 */
static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 status;

		/*
		 * ignore host bridge - we handle
		 * that separately
		 */
		if (dev->bus->number == 0 && dev->devfn == 0)
			continue;

		pci_read_config_word(dev, PCI_STATUS, &status);
		if (status == 0xffff)
			continue;

		if ((status & status_mask) == 0)
			continue;

		/* clear the status errors */
		pci_write_config_word(dev, PCI_STATUS, status & status_mask);

		if (warn)
			printk("(%s: %04X) ", pci_name(dev), status);
	}

	list_for_each_entry(dev, &bus->devices, bus_list)
		if (dev->subordinate)
			pcibios_bus_report_status(dev->subordinate, status_mask, warn);
}

void pcibios_report_status(u_int status_mask, int warn)
{
	struct pci_bus *bus;

	list_for_each_entry(bus, &pci_root_buses, node)
		pcibios_bus_report_status(bus, status_mask, warn);
}

/*
 * We don't use this to fix the device, but initialisation of it.
 * It's not the correct use for this, but it works.
 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
 * the following area:
 * 1. park on CPU
 * 2. ISA bridge ping-pong
 * 3. ISA bridge master handling of target RETRY
 *
 * Bug 3 is responsible for the sound DMA grinding to a halt.  We now
 * live with bug 2.
 */
static void pci_fixup_83c553(struct pci_dev *dev)
{
	/*
	 * Set memory region to start at address 0, and enable IO
	 */
	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
	pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);

	dev->resource[0].end -= dev->resource[0].start;
	dev->resource[0].start = 0;

	/*
	 * All memory requests from ISA to be channelled to PCI
	 */
	pci_write_config_byte(dev, 0x48, 0xff);

	/*
	 * Enable ping-pong on bus master to ISA bridge transactions.
	 * This improves the sound DMA substantially.  The fixed
	 * priority arbiter also helps (see below).
	 */
	pci_write_config_byte(dev, 0x42, 0x01);

	/*
	 * Enable PCI retry
	 */
	pci_write_config_byte(dev, 0x40, 0x22);

	/*
	 * We used to set the arbiter to "park on last master" (bit
	 * 1 set), but unfortunately the CyberPro does not park the
	 * bus.  We must therefore park on CPU.  Unfortunately, this
	 * may trigger yet another bug in the 553.
	 */
	pci_write_config_byte(dev, 0x83, 0x02);

	/*
	 * Make the ISA DMA request lowest priority, and disable
	 * rotating priorities completely.
	 */
	pci_write_config_byte(dev, 0x80, 0x11);
	pci_write_config_byte(dev, 0x81, 0x00);

	/*
	 * Route INTA input to IRQ 11, and set IRQ11 to be level
	 * sensitive.
	 */
	pci_write_config_word(dev, 0x44, 0xb000);
	outb(0x08, 0x4d1);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);

static void pci_fixup_unassign(struct pci_dev *dev)
{
	dev->resource[0].end -= dev->resource[0].start;
	dev->resource[0].start = 0;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);

/*
 * Prevent the PCI layer from seeing the resources allocated to this device
 * if it is the host bridge by marking it as such.  These resources are of
 * no consequence to the PCI layer (they are handled elsewhere).
 */
static void pci_fixup_dec21285(struct pci_dev *dev)
{
	int i;

	if (dev->devfn == 0) {
		dev->class &= 0xff;
		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);

/*
 * PCI IDE controllers use non-standard I/O port decoding, respect it.
 */
static void pci_fixup_ide_bases(struct pci_dev *dev)
{
	struct resource *r;
	int i;

	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
		return;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		r = dev->resource + i;
		if ((r->start & ~0x80) == 0x374) {
			r->start |= 2;
			r->end = r->start;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);

/*
 * Put the DEC21142 to sleep
 */
static void pci_fixup_dec21142(struct pci_dev *dev)
{
	pci_write_config_dword(dev, 0x40, 0x80000000);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);

/*
 * The CY82C693 needs some rather major fixups to ensure that it does
 * the right thing.  Idea from the Alpha people, with a few additions.
 *
 * We ensure that the IDE base registers are set to 1f0/3f4 for the
 * primary bus, and 170/374 for the secondary bus.  Also, hide them
 * from the PCI subsystem view as well so we won't try to perform
 * our own auto-configuration on them.
 *
 * In addition, we ensure that the PCI IDE interrupts are routed to
 * IRQ 14 and IRQ 15 respectively.
 *
 * The above gets us to a point where the IDE on this device is
 * functional.  However, The CY82C693U _does not work_ in bus
 * master mode without locking the PCI bus solid.
 */
static void pci_fixup_cy82c693(struct pci_dev *dev)
{
	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
		u32 base0, base1;

		if (dev->class & 0x80) {	/* primary */
			base0 = 0x1f0;
			base1 = 0x3f4;
		} else {			/* secondary */
			base0 = 0x170;
			base1 = 0x374;
		}

		pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
				       base0 | PCI_BASE_ADDRESS_SPACE_IO);
		pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
				       base1 | PCI_BASE_ADDRESS_SPACE_IO);

		dev->resource[0].start = 0;
		dev->resource[0].end   = 0;
		dev->resource[0].flags = 0;

		dev->resource[1].start = 0;
		dev->resource[1].end   = 0;
		dev->resource[1].flags = 0;
	} else if (PCI_FUNC(dev->devfn) == 0) {
		/*
		 * Setup IDE IRQ routing.
		 */
		pci_write_config_byte(dev, 0x4b, 14);
		pci_write_config_byte(dev, 0x4c, 15);

		/*
		 * Disable FREQACK handshake, enable USB.
		 */
		pci_write_config_byte(dev, 0x4d, 0x41);

		/*
		 * Enable PCI retry, and PCI post-write buffer.
		 */
		pci_write_config_byte(dev, 0x44, 0x17);

		/*
		 * Enable ISA master and DMA post write buffering.
		 */
		pci_write_config_byte(dev, 0x45, 0x03);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);

static void pci_fixup_it8152(struct pci_dev *dev)
{
	int i;
	/* fixup for ITE 8152 devices */
	/* FIXME: add defines for class 0x68000 and 0x80103 */
	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
	    dev->class == 0x68000 ||
	    dev->class == 0x80103) {
		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);

/*
 * If the bus contains any of these devices, then we must not turn on
 * parity checking of any kind.  Currently this is CyberPro 20x0 only.
 */
static inline int pdev_bad_for_parity(struct pci_dev *dev)
{
	return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
		 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
		  dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
		(dev->vendor == PCI_VENDOR_ID_ITE &&
		 dev->device == PCI_DEVICE_ID_ITE_8152));

}

/*
 * pcibios_fixup_bus - Called after each bus is probed,
 * but before its children are examined.
 */
void pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_dev *dev;
	u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;

	/*
	 * Walk the devices on this bus, working out what we can
	 * and can't support.
	 */
	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 status;

		pci_read_config_word(dev, PCI_STATUS, &status);

		/*
		 * If any device on this bus does not support fast back
		 * to back transfers, then the bus as a whole is not able
		 * to support them.  Having fast back to back transfers
		 * on saves us one PCI cycle per transaction.
		 */
		if (!(status & PCI_STATUS_FAST_BACK))
			features &= ~PCI_COMMAND_FAST_BACK;

		if (pdev_bad_for_parity(dev))
			features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);

		switch (dev->class >> 8) {
		case PCI_CLASS_BRIDGE_PCI:
			pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
			status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
			status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
			pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
			break;

		case PCI_CLASS_BRIDGE_CARDBUS:
			pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
			status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
			pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
			break;
		}
	}

	/*
	 * Now walk the devices again, this time setting them up.
	 */
	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 cmd;

		pci_read_config_word(dev, PCI_COMMAND, &cmd);
		cmd |= features;
		pci_write_config_word(dev, PCI_COMMAND, cmd);

		pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
				      L1_CACHE_BYTES >> 2);
	}

	/*
	 * Propagate the flags to the PCI bridge.
	 */
	if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
		if (features & PCI_COMMAND_FAST_BACK)
			bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
		if (features & PCI_COMMAND_PARITY)
			bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
	}

	/*
	 * Report what we did for this bus
	 */
	printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
		bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
}
EXPORT_SYMBOL(pcibios_fixup_bus);

void pcibios_add_bus(struct pci_bus *bus)
{
	struct pci_sys_data *sys = bus->sysdata;
	if (sys->add_bus)
		sys->add_bus(bus);
}

void pcibios_remove_bus(struct pci_bus *bus)
{
	struct pci_sys_data *sys = bus->sysdata;
	if (sys->remove_bus)
		sys->remove_bus(bus);
}

/*
 * Swizzle the device pin each time we cross a bridge.  If a platform does
 * not provide a swizzle function, we perform the standard PCI swizzling.
 *
 * The default swizzling walks up the bus tree one level at a time, applying
 * the standard swizzle function at each step, stopping when it finds the PCI
 * root bus.  This will return the slot number of the bridge device on the
 * root bus and the interrupt pin on that device which should correspond
 * with the downstream device interrupt.
 *
 * Platforms may override this, in which case the slot and pin returned
 * depend entirely on the platform code.  However, please note that the
 * PCI standard swizzle is implemented on plug-in cards and Cardbus based
 * PCI extenders, so it can not be ignored.
 */
static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
{
	struct pci_sys_data *sys = dev->sysdata;
	int slot, oldpin = *pin;

	if (sys->swizzle)
		slot = sys->swizzle(dev, pin);
	else
		slot = pci_common_swizzle(dev, pin);

	if (debug_pci)
		printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
			pci_name(dev), oldpin, *pin, slot);

	return slot;
}

/*
 * Map a slot/pin to an IRQ.
 */
static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pci_sys_data *sys = dev->sysdata;
	int irq = -1;

	if (sys->map_irq)
		irq = sys->map_irq(dev, slot, pin);

	if (debug_pci)
		printk("PCI: %s mapping slot %d pin %d => irq %d\n",
			pci_name(dev), slot, pin, irq);

	return irq;
}

static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
{
	int ret;
	struct pci_host_bridge_window *window;

	if (list_empty(&sys->resources)) {
		pci_add_resource_offset(&sys->resources,
			 &iomem_resource, sys->mem_offset);
	}

	list_for_each_entry(window, &sys->resources, list) {
		if (resource_type(window->res) == IORESOURCE_IO)
			return 0;
	}

	sys->io_res.start = (busnr * SZ_64K) ?  : pcibios_min_io;
	sys->io_res.end = (busnr + 1) * SZ_64K - 1;
	sys->io_res.flags = IORESOURCE_IO;
	sys->io_res.name = sys->io_res_name;
	sprintf(sys->io_res_name, "PCI%d I/O", busnr);

	ret = request_resource(&ioport_resource, &sys->io_res);
	if (ret) {
		pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
		return ret;
	}
	pci_add_resource_offset(&sys->resources, &sys->io_res,
				sys->io_offset);

	return 0;
}

static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
			    struct list_head *head)
{
	struct pci_sys_data *sys = NULL;
	int ret;
	int nr, busnr;

	for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
		sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
		if (!sys)
			panic("PCI: unable to allocate sys data!");

#ifdef CONFIG_PCI_DOMAINS
		sys->domain  = hw->domain;
#endif
		sys->busnr   = busnr;
		sys->swizzle = hw->swizzle;
		sys->map_irq = hw->map_irq;
		sys->align_resource = hw->align_resource;
		sys->add_bus = hw->add_bus;
		sys->remove_bus = hw->remove_bus;
		INIT_LIST_HEAD(&sys->resources);

		if (hw->private_data)
			sys->private_data = hw->private_data[nr];

		ret = hw->setup(nr, sys);

		if (ret > 0) {
			ret = pcibios_init_resources(nr, sys);
			if (ret)  {
				kfree(sys);
				break;
			}

			if (hw->scan)
				sys->bus = hw->scan(nr, sys);
			else
				sys->bus = pci_scan_root_bus(parent, sys->busnr,
						hw->ops, sys, &sys->resources);

			if (!sys->bus)
				panic("PCI: unable to scan bus!");

			busnr = sys->bus->busn_res.end + 1;

			list_add(&sys->node, head);
		} else {
			kfree(sys);
			if (ret < 0)
				break;
		}
	}
}

void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
{
	struct pci_sys_data *sys;
	LIST_HEAD(head);

	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
	if (hw->preinit)
		hw->preinit();
	pcibios_init_hw(parent, hw, &head);
	if (hw->postinit)
		hw->postinit();

	pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);

	list_for_each_entry(sys, &head, node) {
		struct pci_bus *bus = sys->bus;

		if (!pci_has_flag(PCI_PROBE_ONLY)) {
			/*
			 * Size the bridge windows.
			 */
			pci_bus_size_bridges(bus);

			/*
			 * Assign resources.
			 */
			pci_bus_assign_resources(bus);
		}

		/*
		 * Tell drivers about devices found.
		 */
		pci_bus_add_devices(bus);
	}

	list_for_each_entry(sys, &head, node) {
		struct pci_bus *bus = sys->bus;

		/* Configure PCI Express settings */
		if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
			struct pci_bus *child;

			list_for_each_entry(child, &bus->children, node)
				pcie_bus_configure_settings(child);
		}
	}
}

#ifndef CONFIG_PCI_HOST_ITE8152
void pcibios_set_master(struct pci_dev *dev)
{
	/* No special bus mastering setup handling */
}
#endif

char * __init pcibios_setup(char *str)
{
	if (!strcmp(str, "debug")) {
		debug_pci = 1;
		return NULL;
	} else if (!strcmp(str, "firmware")) {
		pci_add_flags(PCI_PROBE_ONLY);
		return NULL;
	}
	return str;
}

/*
 * From arch/i386/kernel/pci-i386.c:
 *
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might be mirrored at 0x0100-0x03ff..
 */
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
				resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_sys_data *sys = dev->sysdata;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO && start & 0x300)
		start = (start + 0x3ff) & ~0x3ff;

	start = (start + align - 1) & ~(align - 1);

	if (sys->align_resource)
		return sys->align_resource(dev, res, start, size, align);

	return start;
}

/**
 * pcibios_enable_device - Enable I/O and memory.
 * @dev: PCI device to be enabled
 */
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	if (pci_has_flag(PCI_PROBE_ONLY))
		return 0;

	return pci_enable_resources(dev, mask);
}

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	struct pci_sys_data *root = dev->sysdata;
	unsigned long phys;

	if (mmap_state == pci_mmap_io) {
		return -EINVAL;
	} else {
		phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
	}

	/*
	 * Mark this as IO
	 */
	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);

	if (remap_pfn_range(vma, vma->vm_start, phys,
			     vma->vm_end - vma->vm_start,
			     vma->vm_page_prot))
		return -EAGAIN;

	return 0;
}

void __init pci_map_io_early(unsigned long pfn)
{
	struct map_desc pci_io_desc = {
		.virtual	= PCI_IO_VIRT_BASE,
		.type		= MT_DEVICE,
		.length		= SZ_64K,
	};

	pci_io_desc.pfn = pfn;
	iotable_init(&pci_io_desc, 1);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/kernel/bios32.c
	3	*
	4	* PCI bios-type initialisation for PCI machines
	5	*
	6	* Bits taken from various places.
	7	*/
ecea4ab6	8	#include <linux/export.h>
1da177e4 LT	9	#include <linux/kernel.h>
	10	#include <linux/pci.h>
	11	#include <linux/slab.h>
	12	#include <linux/init.h>
fced80c7	13	#include <linux/io.h>
1da177e4	14
1da177e4	15	#include <asm/mach-types.h>
c2794437	16	#include <asm/mach/map.h>
1da177e4 LT	17	#include <asm/mach/pci.h>
	18
	19	static int debug_pci;
1da177e4 LT	20
1da177e4 LT	21	/*
5ee09efe	22	* We can't use pci_get_device() here since we are
1da177e4 LT	23	* called from interrupt context.
	24	*/
	25	static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
	26	{
	27	struct pci_dev *dev;
	28
	29	list_for_each_entry(dev, &bus->devices, bus_list) {
	30	u16 status;
	31
	32	/*
	33	* ignore host bridge - we handle
	34	* that separately
	35	*/
	36	if (dev->bus->number == 0 && dev->devfn == 0)
	37	continue;
	38
	39	pci_read_config_word(dev, PCI_STATUS, &status);
	40	if (status == 0xffff)
	41	continue;
	42
	43	if ((status & status_mask) == 0)
	44	continue;
	45
	46	/* clear the status errors */
	47	pci_write_config_word(dev, PCI_STATUS, status & status_mask);
	48
	49	if (warn)
	50	printk("(%s: %04X) ", pci_name(dev), status);
	51	}
	52
	53	list_for_each_entry(dev, &bus->devices, bus_list)
	54	if (dev->subordinate)
	55	pcibios_bus_report_status(dev->subordinate, status_mask, warn);
	56	}
	57
	58	void pcibios_report_status(u_int status_mask, int warn)
	59	{
f0197e0c	60	struct pci_bus *bus;
1da177e4	61
f0197e0c	62	list_for_each_entry(bus, &pci_root_buses, node)
1da177e4	63	pcibios_bus_report_status(bus, status_mask, warn);
1da177e4 LT	64	}
	65
	66	/*
	67	* We don't use this to fix the device, but initialisation of it.
	68	* It's not the correct use for this, but it works.
	69	* Note that the arbiter/ISA bridge appears to be buggy, specifically in
	70	* the following area:
	71	* 1. park on CPU
	72	* 2. ISA bridge ping-pong
	73	* 3. ISA bridge master handling of target RETRY
	74	*
	75	* Bug 3 is responsible for the sound DMA grinding to a halt. We now
	76	* live with bug 2.
	77	*/
351a102d	78	static void pci_fixup_83c553(struct pci_dev *dev)
1da177e4 LT	79	{
	80	/*
	81	* Set memory region to start at address 0, and enable IO
	82	*/
	83	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
	84	pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
	85
	86	dev->resource[0].end -= dev->resource[0].start;
	87	dev->resource[0].start = 0;
	88
	89	/*
	90	* All memory requests from ISA to be channelled to PCI
	91	*/
	92	pci_write_config_byte(dev, 0x48, 0xff);
	93
	94	/*
	95	* Enable ping-pong on bus master to ISA bridge transactions.
	96	* This improves the sound DMA substantially. The fixed
	97	* priority arbiter also helps (see below).
	98	*/
	99	pci_write_config_byte(dev, 0x42, 0x01);
	100
	101	/*
	102	* Enable PCI retry
	103	*/
	104	pci_write_config_byte(dev, 0x40, 0x22);
	105
	106	/*
	107	* We used to set the arbiter to "park on last master" (bit
	108	* 1 set), but unfortunately the CyberPro does not park the
	109	* bus. We must therefore park on CPU. Unfortunately, this
	110	* may trigger yet another bug in the 553.
	111	*/
	112	pci_write_config_byte(dev, 0x83, 0x02);
	113
	114	/*
	115	* Make the ISA DMA request lowest priority, and disable
	116	* rotating priorities completely.
	117	*/
	118	pci_write_config_byte(dev, 0x80, 0x11);
	119	pci_write_config_byte(dev, 0x81, 0x00);
	120
	121	/*
	122	* Route INTA input to IRQ 11, and set IRQ11 to be level
	123	* sensitive.
	124	*/
	125	pci_write_config_word(dev, 0x44, 0xb000);
	126	outb(0x08, 0x4d1);
	127	}
	128	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
	129
351a102d	130	static void pci_fixup_unassign(struct pci_dev *dev)
1da177e4 LT	131	{
	132	dev->resource[0].end -= dev->resource[0].start;
	133	dev->resource[0].start = 0;
	134	}
	135	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
	136
	137	/*
	138	* Prevent the PCI layer from seeing the resources allocated to this device
	139	* if it is the host bridge by marking it as such. These resources are of
	140	* no consequence to the PCI layer (they are handled elsewhere).
	141	*/
351a102d	142	static void pci_fixup_dec21285(struct pci_dev *dev)
1da177e4 LT	143	{
	144	int i;
	145
	146	if (dev->devfn == 0) {
	147	dev->class &= 0xff;
	148	dev->class \|= PCI_CLASS_BRIDGE_HOST << 8;
	149	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	150	dev->resource[i].start = 0;
	151	dev->resource[i].end = 0;
	152	dev->resource[i].flags = 0;
	153	}
	154	}
	155	}
	156	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
	157
1da177e4 LT	158	/*
	159	* PCI IDE controllers use non-standard I/O port decoding, respect it.
	160	*/
351a102d	161	static void pci_fixup_ide_bases(struct pci_dev *dev)
1da177e4 LT	162	{
	163	struct resource *r;
	164	int i;
	165
	166	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
	167	return;
	168
	169	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	170	r = dev->resource + i;
	171	if ((r->start & ~0x80) == 0x374) {
	172	r->start \|= 2;
	173	r->end = r->start;
	174	}
	175	}
	176	}
	177	DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
	178
	179	/*
	180	* Put the DEC21142 to sleep
	181	*/
351a102d	182	static void pci_fixup_dec21142(struct pci_dev *dev)
1da177e4 LT	183	{
	184	pci_write_config_dword(dev, 0x40, 0x80000000);
	185	}
	186	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
	187
	188	/*
	189	* The CY82C693 needs some rather major fixups to ensure that it does
	190	* the right thing. Idea from the Alpha people, with a few additions.
	191	*
	192	* We ensure that the IDE base registers are set to 1f0/3f4 for the
	193	* primary bus, and 170/374 for the secondary bus. Also, hide them
	194	* from the PCI subsystem view as well so we won't try to perform
	195	* our own auto-configuration on them.
	196	*
	197	* In addition, we ensure that the PCI IDE interrupts are routed to
	198	* IRQ 14 and IRQ 15 respectively.
	199	*
	200	* The above gets us to a point where the IDE on this device is
	201	* functional. However, The CY82C693U _does not work_ in bus
	202	* master mode without locking the PCI bus solid.
	203	*/
351a102d	204	static void pci_fixup_cy82c693(struct pci_dev *dev)
1da177e4 LT	205	{
	206	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
	207	u32 base0, base1;
	208
	209	if (dev->class & 0x80) { /* primary */
	210	base0 = 0x1f0;
	211	base1 = 0x3f4;
	212	} else { /* secondary */
	213	base0 = 0x170;
	214	base1 = 0x374;
	215	}
	216
	217	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
	218	base0 \| PCI_BASE_ADDRESS_SPACE_IO);
	219	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
	220	base1 \| PCI_BASE_ADDRESS_SPACE_IO);
	221
	222	dev->resource[0].start = 0;
	223	dev->resource[0].end = 0;
	224	dev->resource[0].flags = 0;
	225
	226	dev->resource[1].start = 0;
	227	dev->resource[1].end = 0;
	228	dev->resource[1].flags = 0;
	229	} else if (PCI_FUNC(dev->devfn) == 0) {
	230	/*
	231	* Setup IDE IRQ routing.
	232	*/
	233	pci_write_config_byte(dev, 0x4b, 14);
	234	pci_write_config_byte(dev, 0x4c, 15);
	235
	236	/*
	237	* Disable FREQACK handshake, enable USB.
	238	*/
	239	pci_write_config_byte(dev, 0x4d, 0x41);
	240
	241	/*
	242	* Enable PCI retry, and PCI post-write buffer.
	243	*/
	244	pci_write_config_byte(dev, 0x44, 0x17);
	245
	246	/*
	247	* Enable ISA master and DMA post write buffering.
	248	*/
	249	pci_write_config_byte(dev, 0x45, 0x03);
	250	}
	251	}
	252	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
	253
351a102d	254	static void pci_fixup_it8152(struct pci_dev *dev)
a8fc0789 MR	255	{
	256	int i;
	257	/* fixup for ITE 8152 devices */
	258	/* FIXME: add defines for class 0x68000 and 0x80103 */
	259	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST \|\|
	260	dev->class == 0x68000 \|\|
	261	dev->class == 0x80103) {
	262	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	263	dev->resource[i].start = 0;
	264	dev->resource[i].end = 0;
	265	dev->resource[i].flags = 0;
	266	}
	267	}
	268	}
	269	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
	270
1da177e4 LT	271	/*
	272	* If the bus contains any of these devices, then we must not turn on
	273	* parity checking of any kind. Currently this is CyberPro 20x0 only.
	274	*/
	275	static inline int pdev_bad_for_parity(struct pci_dev *dev)
	276	{
a8fc0789 MR	277	return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
	278	(dev->device == PCI_DEVICE_ID_INTERG_2000 \|\|
	279	dev->device == PCI_DEVICE_ID_INTERG_2010)) \|\|
	280	(dev->vendor == PCI_VENDOR_ID_ITE &&
	281	dev->device == PCI_DEVICE_ID_ITE_8152));
	282
1da177e4 LT	283	}
1da177e4 LT	284
1da177e4 LT	285	/*
	286	* pcibios_fixup_bus - Called after each bus is probed,
	287	* but before its children are examined.
	288	*/
46edfc54	289	void pcibios_fixup_bus(struct pci_bus *bus)
1da177e4	290	{
1da177e4 LT	291	struct pci_dev *dev;
	292	u16 features = PCI_COMMAND_SERR \| PCI_COMMAND_PARITY \| PCI_COMMAND_FAST_BACK;
	293
1da177e4 LT	294	/*
	295	* Walk the devices on this bus, working out what we can
	296	* and can't support.
	297	*/
	298	list_for_each_entry(dev, &bus->devices, bus_list) {
	299	u16 status;
	300
1da177e4 LT	301	pci_read_config_word(dev, PCI_STATUS, &status);
	302
	303	/*
	304	* If any device on this bus does not support fast back
	305	* to back transfers, then the bus as a whole is not able
	306	* to support them. Having fast back to back transfers
	307	* on saves us one PCI cycle per transaction.
	308	*/
	309	if (!(status & PCI_STATUS_FAST_BACK))
	310	features &= ~PCI_COMMAND_FAST_BACK;
	311
	312	if (pdev_bad_for_parity(dev))
	313	features &= ~(PCI_COMMAND_SERR \| PCI_COMMAND_PARITY);
	314
	315	switch (dev->class >> 8) {
1da177e4 LT	316	case PCI_CLASS_BRIDGE_PCI:
	317	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
	318	status \|= PCI_BRIDGE_CTL_PARITY\|PCI_BRIDGE_CTL_MASTER_ABORT;
	319	status &= ~(PCI_BRIDGE_CTL_BUS_RESET\|PCI_BRIDGE_CTL_FAST_BACK);
	320	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
	321	break;
	322
	323	case PCI_CLASS_BRIDGE_CARDBUS:
	324	pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
	325	status \|= PCI_CB_BRIDGE_CTL_PARITY\|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
	326	pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
	327	break;
	328	}
	329	}
	330
	331	/*
	332	* Now walk the devices again, this time setting them up.
	333	*/
	334	list_for_each_entry(dev, &bus->devices, bus_list) {
	335	u16 cmd;
	336
	337	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	338	cmd \|= features;
	339	pci_write_config_word(dev, PCI_COMMAND, cmd);
	340
	341	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
	342	L1_CACHE_BYTES >> 2);
	343	}
	344
	345	/*
	346	* Propagate the flags to the PCI bridge.
	347	*/
	348	if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
	349	if (features & PCI_COMMAND_FAST_BACK)
	350	bus->bridge_ctl \|= PCI_BRIDGE_CTL_FAST_BACK;
	351	if (features & PCI_COMMAND_PARITY)
	352	bus->bridge_ctl \|= PCI_BRIDGE_CTL_PARITY;
	353	}
	354
	355	/*
	356	* Report what we did for this bus
	357	*/
	358	printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
	359	bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
	360	}
b214bea5	361	EXPORT_SYMBOL(pcibios_fixup_bus);
1da177e4	362
9d981ea5 TP	363	void pcibios_add_bus(struct pci_bus *bus)
	364	{
	365	struct pci_sys_data *sys = bus->sysdata;
	366	if (sys->add_bus)
	367	sys->add_bus(bus);
	368	}
	369
	370	void pcibios_remove_bus(struct pci_bus *bus)
	371	{
	372	struct pci_sys_data *sys = bus->sysdata;
	373	if (sys->remove_bus)
	374	sys->remove_bus(bus);
	375	}
	376
1da177e4	377	/*
daeb4c0c RK	378	* Swizzle the device pin each time we cross a bridge. If a platform does
	379	* not provide a swizzle function, we perform the standard PCI swizzling.
	380	*
	381	* The default swizzling walks up the bus tree one level at a time, applying
	382	* the standard swizzle function at each step, stopping when it finds the PCI
	383	* root bus. This will return the slot number of the bridge device on the
	384	* root bus and the interrupt pin on that device which should correspond
	385	* with the downstream device interrupt.
	386	*
	387	* Platforms may override this, in which case the slot and pin returned
	388	* depend entirely on the platform code. However, please note that the
	389	* PCI standard swizzle is implemented on plug-in cards and Cardbus based
	390	* PCI extenders, so it can not be ignored.
1da177e4	391	*/
351a102d	392	static u8 pcibios_swizzle(struct pci_dev dev, u8 pin)
1da177e4 LT	393	{
1da177e4 LT	394	struct pci_sys_data *sys = dev->sysdata;
daeb4c0c	395	int slot, oldpin = *pin;
1da177e4 LT	396
	397	if (sys->swizzle)
	398	slot = sys->swizzle(dev, pin);
daeb4c0c RK	399	else
daeb4c0c RK	400	slot = pci_common_swizzle(dev, pin);
1da177e4 LT	401
	402	if (debug_pci)
	403	printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
	404	pci_name(dev), oldpin, *pin, slot);
	405
	406	return slot;
	407	}
	408
	409	/*
	410	* Map a slot/pin to an IRQ.
	411	*/
d5341942	412	static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1da177e4 LT	413	{
	414	struct pci_sys_data *sys = dev->sysdata;
	415	int irq = -1;
	416
	417	if (sys->map_irq)
	418	irq = sys->map_irq(dev, slot, pin);
	419
	420	if (debug_pci)
	421	printk("PCI: %s mapping slot %d pin %d => irq %d\n",
	422	pci_name(dev), slot, pin, irq);
	423
	424	return irq;
	425	}
	426
276fd3c5	427	static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
3c5d1699 RH	428	{
	429	int ret;
	430	struct pci_host_bridge_window *window;
	431
	432	if (list_empty(&sys->resources)) {
	433	pci_add_resource_offset(&sys->resources,
	434	&iomem_resource, sys->mem_offset);
	435	}
	436
	437	list_for_each_entry(window, &sys->resources, list) {
	438	if (resource_type(window->res) == IORESOURCE_IO)
	439	return 0;
	440	}
	441
	442	sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
	443	sys->io_res.end = (busnr + 1) * SZ_64K - 1;
	444	sys->io_res.flags = IORESOURCE_IO;
	445	sys->io_res.name = sys->io_res_name;
	446	sprintf(sys->io_res_name, "PCI%d I/O", busnr);
	447
	448	ret = request_resource(&ioport_resource, &sys->io_res);
	449	if (ret) {
	450	pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
	451	return ret;
	452	}
	453	pci_add_resource_offset(&sys->resources, &sys->io_res,
	454	sys->io_offset);
	455
	456	return 0;
	457	}
	458
14d86e72 LW	459	static void pcibios_init_hw(struct device parent, struct hw_pci hw,
14d86e72 LW	460	struct list_head *head)
1da177e4 LT	461	{
	462	struct pci_sys_data *sys = NULL;
	463	int ret;
	464	int nr, busnr;
	465
	466	for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
d2a02b93	467	sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
1da177e4 LT	468	if (!sys)
	469	panic("PCI: unable to allocate sys data!");
	470
52882173 AV	471	#ifdef CONFIG_PCI_DOMAINS
	472	sys->domain = hw->domain;
	473	#endif
1da177e4 LT	474	sys->busnr = busnr;
	475	sys->swizzle = hw->swizzle;
	476	sys->map_irq = hw->map_irq;
029baf14	477	sys->align_resource = hw->align_resource;
9d981ea5 TP	478	sys->add_bus = hw->add_bus;
9d981ea5 TP	479	sys->remove_bus = hw->remove_bus;
37d15909	480	INIT_LIST_HEAD(&sys->resources);
1da177e4	481
352af7d4 TR	482	if (hw->private_data)
	483	sys->private_data = hw->private_data[nr];
	484
1da177e4 LT	485	ret = hw->setup(nr, sys);
	486
	487	if (ret > 0) {
3c5d1699 RH	488	ret = pcibios_init_resources(nr, sys);
	489	if (ret) {
	490	kfree(sys);
	491	break;
37d15909 BH	492	}
37d15909 BH	493
c23bfc38 RK	494	if (hw->scan)
	495	sys->bus = hw->scan(nr, sys);
	496	else
14d86e72	497	sys->bus = pci_scan_root_bus(parent, sys->busnr,
c23bfc38	498	hw->ops, sys, &sys->resources);
1da177e4 LT	499
	500	if (!sys->bus)
	501	panic("PCI: unable to scan bus!");
	502
b918c62e	503	busnr = sys->bus->busn_res.end + 1;
1da177e4	504
90cf2418	505	list_add(&sys->node, head);
1da177e4 LT	506	} else {
	507	kfree(sys);
	508	if (ret < 0)
	509	break;
	510	}
	511	}
	512	}
	513
14d86e72	514	void pci_common_init_dev(struct device parent, struct hw_pci hw)
1da177e4 LT	515	{
1da177e4 LT	516	struct pci_sys_data *sys;
90cf2418	517	LIST_HEAD(head);
1da177e4	518
6696cbc3	519	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
1da177e4 LT	520	if (hw->preinit)
1da177e4 LT	521	hw->preinit();
14d86e72	522	pcibios_init_hw(parent, hw, &head);
1da177e4 LT	523	if (hw->postinit)
	524	hw->postinit();
	525
	526	pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
	527
90cf2418	528	list_for_each_entry(sys, &head, node) {
1da177e4 LT	529	struct pci_bus *bus = sys->bus;
1da177e4 LT	530
a4fab044	531	if (!pci_has_flag(PCI_PROBE_ONLY)) {
1da177e4 LT	532	/*
	533	* Size the bridge windows.
	534	*/
	535	pci_bus_size_bridges(bus);
	536
	537	/*
	538	* Assign resources.
	539	*/
	540	pci_bus_assign_resources(bus);
	541	}
	542
	543	/*
	544	* Tell drivers about devices found.
	545	*/
	546	pci_bus_add_devices(bus);
	547	}
8b5742ad MK	548
	549	list_for_each_entry(sys, &head, node) {
	550	struct pci_bus *bus = sys->bus;
	551
	552	/* Configure PCI Express settings */
	553	if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
	554	struct pci_bus *child;
	555
	556	list_for_each_entry(child, &bus->children, node)
	557	pcie_bus_configure_settings(child);
	558	}
	559	}
1da177e4 LT	560	}
1da177e4 LT	561
168c8619 MS	562	#ifndef CONFIG_PCI_HOST_ITE8152
	563	void pcibios_set_master(struct pci_dev *dev)
	564	{
	565	/* No special bus mastering setup handling */
	566	}
	567	#endif
	568
1da177e4 LT	569	char * __init pcibios_setup(char *str)
	570	{
	571	if (!strcmp(str, "debug")) {
	572	debug_pci = 1;
	573	return NULL;
	574	} else if (!strcmp(str, "firmware")) {
a4fab044	575	pci_add_flags(PCI_PROBE_ONLY);
1da177e4 LT	576	return NULL;
	577	}
	578	return str;
	579	}
	580
	581	/*
	582	* From arch/i386/kernel/pci-i386.c:
	583	*
	584	* We need to avoid collisions with `mirrored' VGA ports
	585	* and other strange ISA hardware, so we always want the
	586	* addresses to be allocated in the 0x000-0x0ff region
	587	* modulo 0x400.
	588	*
	589	* Why? Because some silly external IO cards only decode
	590	* the low 10 bits of the IO address. The 0x00-0xff region
	591	* is reserved for motherboard devices that decode all 16
	592	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	593	* but we want to try to avoid allocating at 0x2900-0x2bff
	594	* which might be mirrored at 0x0100-0x03ff..
	595	*/
3b7a17fc	596	resource_size_t pcibios_align_resource(void data, const struct resource res,
b26b2d49	597	resource_size_t size, resource_size_t align)
1da177e4	598	{
029baf14 TP	599	struct pci_dev *dev = data;
029baf14 TP	600	struct pci_sys_data *sys = dev->sysdata;
e31dd6e4	601	resource_size_t start = res->start;
1da177e4 LT	602
	603	if (res->flags & IORESOURCE_IO && start & 0x300)
	604	start = (start + 0x3ff) & ~0x3ff;
	605
b26b2d49 DB	606	start = (start + align - 1) & ~(align - 1);
b26b2d49 DB	607
029baf14 TP	608	if (sys->align_resource)
	609	return sys->align_resource(dev, res, start, size, align);
	610
b26b2d49	611	return start;
1da177e4 LT	612	}
	613
	614	/**
	615	* pcibios_enable_device - Enable I/O and memory.
	616	* @dev: PCI device to be enabled
	617	*/
	618	int pcibios_enable_device(struct pci_dev *dev, int mask)
	619	{
27e8efdb WD	620	if (pci_has_flag(PCI_PROBE_ONLY))
27e8efdb WD	621	return 0;
1da177e4	622
27e8efdb	623	return pci_enable_resources(dev, mask);
1da177e4 LT	624	}
	625
	626	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	627	enum pci_mmap_state mmap_state, int write_combine)
	628	{
	629	struct pci_sys_data *root = dev->sysdata;
	630	unsigned long phys;
	631
	632	if (mmap_state == pci_mmap_io) {
	633	return -EINVAL;
	634	} else {
	635	phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
	636	}
	637
	638	/*
	639	* Mark this as IO
	640	*/
1da177e4 LT	641	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
	642
	643	if (remap_pfn_range(vma, vma->vm_start, phys,
	644	vma->vm_end - vma->vm_start,
	645	vma->vm_page_prot))
	646	return -EAGAIN;
	647
	648	return 0;
	649	}
c2794437 RH	650
	651	void __init pci_map_io_early(unsigned long pfn)
	652	{
	653	struct map_desc pci_io_desc = {
	654	.virtual = PCI_IO_VIRT_BASE,
	655	.type = MT_DEVICE,
	656	.length = SZ_64K,
	657	};
	658
	659	pci_io_desc.pfn = pfn;
	660	iotable_init(&pci_io_desc, 1);
	661	}