Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/bios32.c | |
3 | * | |
4 | * PCI bios-type initialisation for PCI machines | |
5 | * | |
6 | * Bits taken from various places. | |
7 | */ | |
1da177e4 LT |
8 | #include <linux/module.h> |
9 | #include <linux/kernel.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/init.h> | |
fced80c7 | 13 | #include <linux/io.h> |
1da177e4 | 14 | |
1da177e4 LT |
15 | #include <asm/mach-types.h> |
16 | #include <asm/mach/pci.h> | |
17 | ||
18 | static int debug_pci; | |
19 | static int use_firmware; | |
20 | ||
21 | /* | |
22 | * We can't use pci_find_device() here since we are | |
23 | * called from interrupt context. | |
24 | */ | |
25 | static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn) | |
26 | { | |
27 | struct pci_dev *dev; | |
28 | ||
29 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
30 | u16 status; | |
31 | ||
32 | /* | |
33 | * ignore host bridge - we handle | |
34 | * that separately | |
35 | */ | |
36 | if (dev->bus->number == 0 && dev->devfn == 0) | |
37 | continue; | |
38 | ||
39 | pci_read_config_word(dev, PCI_STATUS, &status); | |
40 | if (status == 0xffff) | |
41 | continue; | |
42 | ||
43 | if ((status & status_mask) == 0) | |
44 | continue; | |
45 | ||
46 | /* clear the status errors */ | |
47 | pci_write_config_word(dev, PCI_STATUS, status & status_mask); | |
48 | ||
49 | if (warn) | |
50 | printk("(%s: %04X) ", pci_name(dev), status); | |
51 | } | |
52 | ||
53 | list_for_each_entry(dev, &bus->devices, bus_list) | |
54 | if (dev->subordinate) | |
55 | pcibios_bus_report_status(dev->subordinate, status_mask, warn); | |
56 | } | |
57 | ||
58 | void pcibios_report_status(u_int status_mask, int warn) | |
59 | { | |
60 | struct list_head *l; | |
61 | ||
62 | list_for_each(l, &pci_root_buses) { | |
63 | struct pci_bus *bus = pci_bus_b(l); | |
64 | ||
65 | pcibios_bus_report_status(bus, status_mask, warn); | |
66 | } | |
67 | } | |
68 | ||
69 | /* | |
70 | * We don't use this to fix the device, but initialisation of it. | |
71 | * It's not the correct use for this, but it works. | |
72 | * Note that the arbiter/ISA bridge appears to be buggy, specifically in | |
73 | * the following area: | |
74 | * 1. park on CPU | |
75 | * 2. ISA bridge ping-pong | |
76 | * 3. ISA bridge master handling of target RETRY | |
77 | * | |
78 | * Bug 3 is responsible for the sound DMA grinding to a halt. We now | |
79 | * live with bug 2. | |
80 | */ | |
81 | static void __devinit pci_fixup_83c553(struct pci_dev *dev) | |
82 | { | |
83 | /* | |
84 | * Set memory region to start at address 0, and enable IO | |
85 | */ | |
86 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
87 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO); | |
88 | ||
89 | dev->resource[0].end -= dev->resource[0].start; | |
90 | dev->resource[0].start = 0; | |
91 | ||
92 | /* | |
93 | * All memory requests from ISA to be channelled to PCI | |
94 | */ | |
95 | pci_write_config_byte(dev, 0x48, 0xff); | |
96 | ||
97 | /* | |
98 | * Enable ping-pong on bus master to ISA bridge transactions. | |
99 | * This improves the sound DMA substantially. The fixed | |
100 | * priority arbiter also helps (see below). | |
101 | */ | |
102 | pci_write_config_byte(dev, 0x42, 0x01); | |
103 | ||
104 | /* | |
105 | * Enable PCI retry | |
106 | */ | |
107 | pci_write_config_byte(dev, 0x40, 0x22); | |
108 | ||
109 | /* | |
110 | * We used to set the arbiter to "park on last master" (bit | |
111 | * 1 set), but unfortunately the CyberPro does not park the | |
112 | * bus. We must therefore park on CPU. Unfortunately, this | |
113 | * may trigger yet another bug in the 553. | |
114 | */ | |
115 | pci_write_config_byte(dev, 0x83, 0x02); | |
116 | ||
117 | /* | |
118 | * Make the ISA DMA request lowest priority, and disable | |
119 | * rotating priorities completely. | |
120 | */ | |
121 | pci_write_config_byte(dev, 0x80, 0x11); | |
122 | pci_write_config_byte(dev, 0x81, 0x00); | |
123 | ||
124 | /* | |
125 | * Route INTA input to IRQ 11, and set IRQ11 to be level | |
126 | * sensitive. | |
127 | */ | |
128 | pci_write_config_word(dev, 0x44, 0xb000); | |
129 | outb(0x08, 0x4d1); | |
130 | } | |
131 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553); | |
132 | ||
133 | static void __devinit pci_fixup_unassign(struct pci_dev *dev) | |
134 | { | |
135 | dev->resource[0].end -= dev->resource[0].start; | |
136 | dev->resource[0].start = 0; | |
137 | } | |
138 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign); | |
139 | ||
140 | /* | |
141 | * Prevent the PCI layer from seeing the resources allocated to this device | |
142 | * if it is the host bridge by marking it as such. These resources are of | |
143 | * no consequence to the PCI layer (they are handled elsewhere). | |
144 | */ | |
145 | static void __devinit pci_fixup_dec21285(struct pci_dev *dev) | |
146 | { | |
147 | int i; | |
148 | ||
149 | if (dev->devfn == 0) { | |
150 | dev->class &= 0xff; | |
151 | dev->class |= PCI_CLASS_BRIDGE_HOST << 8; | |
152 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
153 | dev->resource[i].start = 0; | |
154 | dev->resource[i].end = 0; | |
155 | dev->resource[i].flags = 0; | |
156 | } | |
157 | } | |
158 | } | |
159 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); | |
160 | ||
161 | /* | |
162 | * Same as above. The PrPMC800 carrier board for the PrPMC1100 | |
163 | * card maps the host-bridge @ 00:01:00 for some reason and it | |
164 | * ends up getting scanned. Note that we only want to do this | |
165 | * fixup when we find the IXP4xx on a PrPMC system, which is why | |
166 | * we check the machine type. We could be running on a board | |
167 | * with an IXP4xx target device and we don't want to kill the | |
168 | * resources in that case. | |
169 | */ | |
170 | static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev) | |
171 | { | |
172 | int i; | |
173 | ||
174 | if (machine_is_prpmc1100()) { | |
175 | dev->class &= 0xff; | |
176 | dev->class |= PCI_CLASS_BRIDGE_HOST << 8; | |
177 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
178 | dev->resource[i].start = 0; | |
179 | dev->resource[i].end = 0; | |
180 | dev->resource[i].flags = 0; | |
181 | } | |
182 | } | |
183 | } | |
184 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100); | |
185 | ||
186 | /* | |
187 | * PCI IDE controllers use non-standard I/O port decoding, respect it. | |
188 | */ | |
189 | static void __devinit pci_fixup_ide_bases(struct pci_dev *dev) | |
190 | { | |
191 | struct resource *r; | |
192 | int i; | |
193 | ||
194 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) | |
195 | return; | |
196 | ||
197 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
198 | r = dev->resource + i; | |
199 | if ((r->start & ~0x80) == 0x374) { | |
200 | r->start |= 2; | |
201 | r->end = r->start; | |
202 | } | |
203 | } | |
204 | } | |
205 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); | |
206 | ||
207 | /* | |
208 | * Put the DEC21142 to sleep | |
209 | */ | |
210 | static void __devinit pci_fixup_dec21142(struct pci_dev *dev) | |
211 | { | |
212 | pci_write_config_dword(dev, 0x40, 0x80000000); | |
213 | } | |
214 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142); | |
215 | ||
216 | /* | |
217 | * The CY82C693 needs some rather major fixups to ensure that it does | |
218 | * the right thing. Idea from the Alpha people, with a few additions. | |
219 | * | |
220 | * We ensure that the IDE base registers are set to 1f0/3f4 for the | |
221 | * primary bus, and 170/374 for the secondary bus. Also, hide them | |
222 | * from the PCI subsystem view as well so we won't try to perform | |
223 | * our own auto-configuration on them. | |
224 | * | |
225 | * In addition, we ensure that the PCI IDE interrupts are routed to | |
226 | * IRQ 14 and IRQ 15 respectively. | |
227 | * | |
228 | * The above gets us to a point where the IDE on this device is | |
229 | * functional. However, The CY82C693U _does not work_ in bus | |
230 | * master mode without locking the PCI bus solid. | |
231 | */ | |
232 | static void __devinit pci_fixup_cy82c693(struct pci_dev *dev) | |
233 | { | |
234 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
235 | u32 base0, base1; | |
236 | ||
237 | if (dev->class & 0x80) { /* primary */ | |
238 | base0 = 0x1f0; | |
239 | base1 = 0x3f4; | |
240 | } else { /* secondary */ | |
241 | base0 = 0x170; | |
242 | base1 = 0x374; | |
243 | } | |
244 | ||
245 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, | |
246 | base0 | PCI_BASE_ADDRESS_SPACE_IO); | |
247 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, | |
248 | base1 | PCI_BASE_ADDRESS_SPACE_IO); | |
249 | ||
250 | dev->resource[0].start = 0; | |
251 | dev->resource[0].end = 0; | |
252 | dev->resource[0].flags = 0; | |
253 | ||
254 | dev->resource[1].start = 0; | |
255 | dev->resource[1].end = 0; | |
256 | dev->resource[1].flags = 0; | |
257 | } else if (PCI_FUNC(dev->devfn) == 0) { | |
258 | /* | |
259 | * Setup IDE IRQ routing. | |
260 | */ | |
261 | pci_write_config_byte(dev, 0x4b, 14); | |
262 | pci_write_config_byte(dev, 0x4c, 15); | |
263 | ||
264 | /* | |
265 | * Disable FREQACK handshake, enable USB. | |
266 | */ | |
267 | pci_write_config_byte(dev, 0x4d, 0x41); | |
268 | ||
269 | /* | |
270 | * Enable PCI retry, and PCI post-write buffer. | |
271 | */ | |
272 | pci_write_config_byte(dev, 0x44, 0x17); | |
273 | ||
274 | /* | |
275 | * Enable ISA master and DMA post write buffering. | |
276 | */ | |
277 | pci_write_config_byte(dev, 0x45, 0x03); | |
278 | } | |
279 | } | |
280 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); | |
281 | ||
a8fc0789 MR |
282 | static void __init pci_fixup_it8152(struct pci_dev *dev) |
283 | { | |
284 | int i; | |
285 | /* fixup for ITE 8152 devices */ | |
286 | /* FIXME: add defines for class 0x68000 and 0x80103 */ | |
287 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST || | |
288 | dev->class == 0x68000 || | |
289 | dev->class == 0x80103) { | |
290 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
291 | dev->resource[i].start = 0; | |
292 | dev->resource[i].end = 0; | |
293 | dev->resource[i].flags = 0; | |
294 | } | |
295 | } | |
296 | } | |
297 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); | |
298 | ||
299 | ||
300 | ||
1da177e4 LT |
301 | void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) |
302 | { | |
303 | if (debug_pci) | |
304 | printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev)); | |
305 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
306 | } | |
307 | ||
308 | /* | |
309 | * If the bus contains any of these devices, then we must not turn on | |
310 | * parity checking of any kind. Currently this is CyberPro 20x0 only. | |
311 | */ | |
312 | static inline int pdev_bad_for_parity(struct pci_dev *dev) | |
313 | { | |
a8fc0789 MR |
314 | return ((dev->vendor == PCI_VENDOR_ID_INTERG && |
315 | (dev->device == PCI_DEVICE_ID_INTERG_2000 || | |
316 | dev->device == PCI_DEVICE_ID_INTERG_2010)) || | |
317 | (dev->vendor == PCI_VENDOR_ID_ITE && | |
318 | dev->device == PCI_DEVICE_ID_ITE_8152)); | |
319 | ||
1da177e4 LT |
320 | } |
321 | ||
322 | /* | |
323 | * Adjust the device resources from bus-centric to Linux-centric. | |
324 | */ | |
325 | static void __devinit | |
326 | pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev) | |
327 | { | |
e31dd6e4 | 328 | resource_size_t offset; |
1da177e4 LT |
329 | int i; |
330 | ||
331 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
332 | if (dev->resource[i].start == 0) | |
333 | continue; | |
334 | if (dev->resource[i].flags & IORESOURCE_MEM) | |
335 | offset = root->mem_offset; | |
336 | else | |
337 | offset = root->io_offset; | |
338 | ||
339 | dev->resource[i].start += offset; | |
340 | dev->resource[i].end += offset; | |
341 | } | |
342 | } | |
343 | ||
344 | static void __devinit | |
345 | pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root) | |
346 | { | |
347 | struct pci_dev *dev = bus->self; | |
348 | int i; | |
349 | ||
350 | if (!dev) { | |
351 | /* | |
352 | * Assign root bus resources. | |
353 | */ | |
354 | for (i = 0; i < 3; i++) | |
355 | bus->resource[i] = root->resource[i]; | |
356 | } | |
357 | } | |
358 | ||
359 | /* | |
360 | * pcibios_fixup_bus - Called after each bus is probed, | |
361 | * but before its children are examined. | |
362 | */ | |
46edfc54 | 363 | void pcibios_fixup_bus(struct pci_bus *bus) |
1da177e4 LT |
364 | { |
365 | struct pci_sys_data *root = bus->sysdata; | |
366 | struct pci_dev *dev; | |
367 | u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK; | |
368 | ||
369 | pbus_assign_bus_resources(bus, root); | |
370 | ||
371 | /* | |
372 | * Walk the devices on this bus, working out what we can | |
373 | * and can't support. | |
374 | */ | |
375 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
376 | u16 status; | |
377 | ||
378 | pdev_fixup_device_resources(root, dev); | |
379 | ||
380 | pci_read_config_word(dev, PCI_STATUS, &status); | |
381 | ||
382 | /* | |
383 | * If any device on this bus does not support fast back | |
384 | * to back transfers, then the bus as a whole is not able | |
385 | * to support them. Having fast back to back transfers | |
386 | * on saves us one PCI cycle per transaction. | |
387 | */ | |
388 | if (!(status & PCI_STATUS_FAST_BACK)) | |
389 | features &= ~PCI_COMMAND_FAST_BACK; | |
390 | ||
391 | if (pdev_bad_for_parity(dev)) | |
392 | features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); | |
393 | ||
394 | switch (dev->class >> 8) { | |
1da177e4 LT |
395 | case PCI_CLASS_BRIDGE_PCI: |
396 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status); | |
397 | status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT; | |
398 | status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK); | |
399 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status); | |
400 | break; | |
401 | ||
402 | case PCI_CLASS_BRIDGE_CARDBUS: | |
403 | pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status); | |
404 | status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT; | |
405 | pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status); | |
406 | break; | |
407 | } | |
408 | } | |
409 | ||
410 | /* | |
411 | * Now walk the devices again, this time setting them up. | |
412 | */ | |
413 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
414 | u16 cmd; | |
415 | ||
416 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
417 | cmd |= features; | |
418 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
419 | ||
420 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, | |
421 | L1_CACHE_BYTES >> 2); | |
422 | } | |
423 | ||
424 | /* | |
425 | * Propagate the flags to the PCI bridge. | |
426 | */ | |
427 | if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
428 | if (features & PCI_COMMAND_FAST_BACK) | |
429 | bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK; | |
430 | if (features & PCI_COMMAND_PARITY) | |
431 | bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY; | |
432 | } | |
433 | ||
434 | /* | |
435 | * Report what we did for this bus | |
436 | */ | |
437 | printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n", | |
438 | bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); | |
439 | } | |
440 | ||
441 | /* | |
442 | * Convert from Linux-centric to bus-centric addresses for bridge devices. | |
443 | */ | |
46edfc54 | 444 | void |
1da177e4 LT |
445 | pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
446 | struct resource *res) | |
447 | { | |
448 | struct pci_sys_data *root = dev->sysdata; | |
449 | unsigned long offset = 0; | |
450 | ||
451 | if (res->flags & IORESOURCE_IO) | |
452 | offset = root->io_offset; | |
453 | if (res->flags & IORESOURCE_MEM) | |
454 | offset = root->mem_offset; | |
455 | ||
456 | region->start = res->start - offset; | |
457 | region->end = res->end - offset; | |
458 | } | |
459 | ||
43c34735 DB |
460 | void __devinit |
461 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
462 | struct pci_bus_region *region) | |
463 | { | |
464 | struct pci_sys_data *root = dev->sysdata; | |
465 | unsigned long offset = 0; | |
466 | ||
467 | if (res->flags & IORESOURCE_IO) | |
468 | offset = root->io_offset; | |
469 | if (res->flags & IORESOURCE_MEM) | |
470 | offset = root->mem_offset; | |
471 | ||
472 | res->start = region->start + offset; | |
473 | res->end = region->end + offset; | |
474 | } | |
475 | ||
1da177e4 LT |
476 | #ifdef CONFIG_HOTPLUG |
477 | EXPORT_SYMBOL(pcibios_fixup_bus); | |
478 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
43c34735 | 479 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 LT |
480 | #endif |
481 | ||
482 | /* | |
483 | * This is the standard PCI-PCI bridge swizzling algorithm: | |
484 | * | |
485 | * Dev: 0 1 2 3 | |
486 | * A A B C D | |
487 | * B B C D A | |
488 | * C C D A B | |
489 | * D D A B C | |
490 | * ^^^^^^^^^^ irq pin on bridge | |
491 | */ | |
492 | u8 __devinit pci_std_swizzle(struct pci_dev *dev, u8 *pinp) | |
493 | { | |
494 | int pin = *pinp - 1; | |
495 | ||
496 | while (dev->bus->self) { | |
497 | pin = (pin + PCI_SLOT(dev->devfn)) & 3; | |
498 | /* | |
499 | * move up the chain of bridges, | |
500 | * swizzling as we go. | |
501 | */ | |
502 | dev = dev->bus->self; | |
503 | } | |
504 | *pinp = pin + 1; | |
505 | ||
506 | return PCI_SLOT(dev->devfn); | |
507 | } | |
508 | ||
509 | /* | |
510 | * Swizzle the device pin each time we cross a bridge. | |
511 | * This might update pin and returns the slot number. | |
512 | */ | |
513 | static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin) | |
514 | { | |
515 | struct pci_sys_data *sys = dev->sysdata; | |
516 | int slot = 0, oldpin = *pin; | |
517 | ||
518 | if (sys->swizzle) | |
519 | slot = sys->swizzle(dev, pin); | |
520 | ||
521 | if (debug_pci) | |
522 | printk("PCI: %s swizzling pin %d => pin %d slot %d\n", | |
523 | pci_name(dev), oldpin, *pin, slot); | |
524 | ||
525 | return slot; | |
526 | } | |
527 | ||
528 | /* | |
529 | * Map a slot/pin to an IRQ. | |
530 | */ | |
531 | static int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
532 | { | |
533 | struct pci_sys_data *sys = dev->sysdata; | |
534 | int irq = -1; | |
535 | ||
536 | if (sys->map_irq) | |
537 | irq = sys->map_irq(dev, slot, pin); | |
538 | ||
539 | if (debug_pci) | |
540 | printk("PCI: %s mapping slot %d pin %d => irq %d\n", | |
541 | pci_name(dev), slot, pin, irq); | |
542 | ||
543 | return irq; | |
544 | } | |
545 | ||
546 | static void __init pcibios_init_hw(struct hw_pci *hw) | |
547 | { | |
548 | struct pci_sys_data *sys = NULL; | |
549 | int ret; | |
550 | int nr, busnr; | |
551 | ||
552 | for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { | |
d2a02b93 | 553 | sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL); |
1da177e4 LT |
554 | if (!sys) |
555 | panic("PCI: unable to allocate sys data!"); | |
556 | ||
1da177e4 LT |
557 | sys->hw = hw; |
558 | sys->busnr = busnr; | |
559 | sys->swizzle = hw->swizzle; | |
560 | sys->map_irq = hw->map_irq; | |
561 | sys->resource[0] = &ioport_resource; | |
562 | sys->resource[1] = &iomem_resource; | |
563 | ||
564 | ret = hw->setup(nr, sys); | |
565 | ||
566 | if (ret > 0) { | |
567 | sys->bus = hw->scan(nr, sys); | |
568 | ||
569 | if (!sys->bus) | |
570 | panic("PCI: unable to scan bus!"); | |
571 | ||
572 | busnr = sys->bus->subordinate + 1; | |
573 | ||
574 | list_add(&sys->node, &hw->buses); | |
575 | } else { | |
576 | kfree(sys); | |
577 | if (ret < 0) | |
578 | break; | |
579 | } | |
580 | } | |
581 | } | |
582 | ||
583 | void __init pci_common_init(struct hw_pci *hw) | |
584 | { | |
585 | struct pci_sys_data *sys; | |
586 | ||
587 | INIT_LIST_HEAD(&hw->buses); | |
588 | ||
589 | if (hw->preinit) | |
590 | hw->preinit(); | |
591 | pcibios_init_hw(hw); | |
592 | if (hw->postinit) | |
593 | hw->postinit(); | |
594 | ||
595 | pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq); | |
596 | ||
597 | list_for_each_entry(sys, &hw->buses, node) { | |
598 | struct pci_bus *bus = sys->bus; | |
599 | ||
600 | if (!use_firmware) { | |
601 | /* | |
602 | * Size the bridge windows. | |
603 | */ | |
604 | pci_bus_size_bridges(bus); | |
605 | ||
606 | /* | |
607 | * Assign resources. | |
608 | */ | |
609 | pci_bus_assign_resources(bus); | |
610 | } | |
611 | ||
612 | /* | |
613 | * Tell drivers about devices found. | |
614 | */ | |
615 | pci_bus_add_devices(bus); | |
616 | } | |
617 | } | |
618 | ||
619 | char * __init pcibios_setup(char *str) | |
620 | { | |
621 | if (!strcmp(str, "debug")) { | |
622 | debug_pci = 1; | |
623 | return NULL; | |
624 | } else if (!strcmp(str, "firmware")) { | |
625 | use_firmware = 1; | |
626 | return NULL; | |
627 | } | |
628 | return str; | |
629 | } | |
630 | ||
631 | /* | |
632 | * From arch/i386/kernel/pci-i386.c: | |
633 | * | |
634 | * We need to avoid collisions with `mirrored' VGA ports | |
635 | * and other strange ISA hardware, so we always want the | |
636 | * addresses to be allocated in the 0x000-0x0ff region | |
637 | * modulo 0x400. | |
638 | * | |
639 | * Why? Because some silly external IO cards only decode | |
640 | * the low 10 bits of the IO address. The 0x00-0xff region | |
641 | * is reserved for motherboard devices that decode all 16 | |
642 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
643 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
644 | * which might be mirrored at 0x0100-0x03ff.. | |
645 | */ | |
646 | void pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 647 | resource_size_t size, resource_size_t align) |
1da177e4 | 648 | { |
e31dd6e4 | 649 | resource_size_t start = res->start; |
1da177e4 LT |
650 | |
651 | if (res->flags & IORESOURCE_IO && start & 0x300) | |
652 | start = (start + 0x3ff) & ~0x3ff; | |
653 | ||
654 | res->start = (start + align - 1) & ~(align - 1); | |
655 | } | |
656 | ||
657 | /** | |
658 | * pcibios_enable_device - Enable I/O and memory. | |
659 | * @dev: PCI device to be enabled | |
660 | */ | |
661 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
662 | { | |
663 | u16 cmd, old_cmd; | |
664 | int idx; | |
665 | struct resource *r; | |
666 | ||
667 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
668 | old_cmd = cmd; | |
669 | for (idx = 0; idx < 6; idx++) { | |
670 | /* Only set up the requested stuff */ | |
671 | if (!(mask & (1 << idx))) | |
672 | continue; | |
673 | ||
674 | r = dev->resource + idx; | |
675 | if (!r->start && r->end) { | |
676 | printk(KERN_ERR "PCI: Device %s not available because" | |
677 | " of resource collisions\n", pci_name(dev)); | |
678 | return -EINVAL; | |
679 | } | |
680 | if (r->flags & IORESOURCE_IO) | |
681 | cmd |= PCI_COMMAND_IO; | |
682 | if (r->flags & IORESOURCE_MEM) | |
683 | cmd |= PCI_COMMAND_MEMORY; | |
684 | } | |
685 | ||
686 | /* | |
687 | * Bridges (eg, cardbus bridges) need to be fully enabled | |
688 | */ | |
689 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) | |
690 | cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY; | |
691 | ||
692 | if (cmd != old_cmd) { | |
693 | printk("PCI: enabling device %s (%04x -> %04x)\n", | |
694 | pci_name(dev), old_cmd, cmd); | |
695 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
696 | } | |
697 | return 0; | |
698 | } | |
699 | ||
700 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
701 | enum pci_mmap_state mmap_state, int write_combine) | |
702 | { | |
703 | struct pci_sys_data *root = dev->sysdata; | |
704 | unsigned long phys; | |
705 | ||
706 | if (mmap_state == pci_mmap_io) { | |
707 | return -EINVAL; | |
708 | } else { | |
709 | phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT); | |
710 | } | |
711 | ||
712 | /* | |
713 | * Mark this as IO | |
714 | */ | |
1da177e4 LT |
715 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
716 | ||
717 | if (remap_pfn_range(vma, vma->vm_start, phys, | |
718 | vma->vm_end - vma->vm_start, | |
719 | vma->vm_page_prot)) | |
720 | return -EAGAIN; | |
721 | ||
722 | return 0; | |
723 | } |