Commit | Line | Data |
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9eb8f674 GL |
1 | /* |
2 | * linux/arch/arm/kernel/devtree.c | |
3 | * | |
4 | * Copyright (C) 2009 Canonical Ltd. <jeremy.kerr@canonical.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
ecea4ab6 | 12 | #include <linux/export.h> |
9eb8f674 GL |
13 | #include <linux/errno.h> |
14 | #include <linux/types.h> | |
15 | #include <linux/bootmem.h> | |
16 | #include <linux/memblock.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/of_fdt.h> | |
19 | #include <linux/of_irq.h> | |
20 | #include <linux/of_platform.h> | |
6c3ff8b1 | 21 | #include <linux/smp.h> |
9eb8f674 | 22 | |
a0ae0240 | 23 | #include <asm/cputype.h> |
9eb8f674 GL |
24 | #include <asm/setup.h> |
25 | #include <asm/page.h> | |
a0ae0240 | 26 | #include <asm/smp_plat.h> |
93c02ab4 GL |
27 | #include <asm/mach/arch.h> |
28 | #include <asm/mach-types.h> | |
9eb8f674 GL |
29 | |
30 | void __init early_init_dt_add_memory_arch(u64 base, u64 size) | |
31 | { | |
32 | arm_add_memory(base, size); | |
33 | } | |
34 | ||
93c02ab4 GL |
35 | void __init arm_dt_memblock_reserve(void) |
36 | { | |
37 | u64 *reserve_map, base, size; | |
38 | ||
39 | if (!initial_boot_params) | |
40 | return; | |
41 | ||
42 | /* Reserve the dtb region */ | |
43 | memblock_reserve(virt_to_phys(initial_boot_params), | |
44 | be32_to_cpu(initial_boot_params->totalsize)); | |
45 | ||
46 | /* | |
47 | * Process the reserve map. This will probably overlap the initrd | |
48 | * and dtb locations which are already reserved, but overlaping | |
49 | * doesn't hurt anything | |
50 | */ | |
51 | reserve_map = ((void*)initial_boot_params) + | |
52 | be32_to_cpu(initial_boot_params->off_mem_rsvmap); | |
53 | while (1) { | |
54 | base = be64_to_cpup(reserve_map++); | |
55 | size = be64_to_cpup(reserve_map++); | |
56 | if (!size) | |
57 | break; | |
58 | memblock_reserve(base, size); | |
59 | } | |
60 | } | |
61 | ||
6c3ff8b1 SB |
62 | #ifdef CONFIG_SMP |
63 | extern struct of_cpu_method __cpu_method_of_table_begin[]; | |
64 | extern struct of_cpu_method __cpu_method_of_table_end[]; | |
65 | ||
66 | static int __init set_smp_ops_by_method(struct device_node *node) | |
67 | { | |
68 | const char *method; | |
69 | struct of_cpu_method *m = __cpu_method_of_table_begin; | |
70 | ||
71 | if (of_property_read_string(node, "enable-method", &method)) | |
72 | return 0; | |
73 | ||
74 | for (; m < __cpu_method_of_table_end; m++) | |
75 | if (!strcmp(m->method, method)) { | |
76 | smp_set_ops(m->ops); | |
77 | return 1; | |
78 | } | |
79 | ||
80 | return 0; | |
81 | } | |
82 | #else | |
83 | static inline int set_smp_ops_by_method(struct device_node *node) | |
84 | { | |
85 | return 1; | |
86 | } | |
87 | #endif | |
88 | ||
89 | ||
a0ae0240 LP |
90 | /* |
91 | * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree | |
92 | * and builds the cpu logical map array containing MPIDR values related to | |
93 | * logical cpus | |
94 | * | |
95 | * Updates the cpu possible mask with the number of parsed cpu nodes | |
96 | */ | |
97 | void __init arm_dt_init_cpu_maps(void) | |
98 | { | |
99 | /* | |
100 | * Temp logical map is initialized with UINT_MAX values that are | |
101 | * considered invalid logical map entries since the logical map must | |
102 | * contain a list of MPIDR[23:0] values where MPIDR[31:24] must | |
103 | * read as 0. | |
104 | */ | |
105 | struct device_node *cpu, *cpus; | |
6c3ff8b1 | 106 | int found_method = 0; |
a0ae0240 LP |
107 | u32 i, j, cpuidx = 1; |
108 | u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; | |
109 | ||
18d7f152 | 110 | u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID }; |
a0ae0240 LP |
111 | bool bootcpu_valid = false; |
112 | cpus = of_find_node_by_path("/cpus"); | |
113 | ||
114 | if (!cpus) | |
115 | return; | |
116 | ||
117 | for_each_child_of_node(cpus, cpu) { | |
118 | u32 hwid; | |
119 | ||
1ba9bf0a LP |
120 | if (of_node_cmp(cpu->type, "cpu")) |
121 | continue; | |
122 | ||
a0ae0240 LP |
123 | pr_debug(" * %s...\n", cpu->full_name); |
124 | /* | |
125 | * A device tree containing CPU nodes with missing "reg" | |
126 | * properties is considered invalid to build the | |
127 | * cpu_logical_map. | |
128 | */ | |
129 | if (of_property_read_u32(cpu, "reg", &hwid)) { | |
130 | pr_debug(" * %s missing reg property\n", | |
131 | cpu->full_name); | |
132 | return; | |
133 | } | |
134 | ||
135 | /* | |
136 | * 8 MSBs must be set to 0 in the DT since the reg property | |
137 | * defines the MPIDR[23:0]. | |
138 | */ | |
139 | if (hwid & ~MPIDR_HWID_BITMASK) | |
140 | return; | |
141 | ||
142 | /* | |
143 | * Duplicate MPIDRs are a recipe for disaster. | |
144 | * Scan all initialized entries and check for | |
145 | * duplicates. If any is found just bail out. | |
146 | * temp values were initialized to UINT_MAX | |
147 | * to avoid matching valid MPIDR[23:0] values. | |
148 | */ | |
149 | for (j = 0; j < cpuidx; j++) | |
150 | if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg " | |
151 | "properties in the DT\n")) | |
152 | return; | |
153 | ||
154 | /* | |
155 | * Build a stashed array of MPIDR values. Numbering scheme | |
156 | * requires that if detected the boot CPU must be assigned | |
157 | * logical id 0. Other CPUs get sequential indexes starting | |
158 | * from 1. If a CPU node with a reg property matching the | |
159 | * boot CPU MPIDR is detected, this is recorded so that the | |
160 | * logical map built from DT is validated and can be used | |
161 | * to override the map created in smp_setup_processor_id(). | |
162 | */ | |
163 | if (hwid == mpidr) { | |
164 | i = 0; | |
165 | bootcpu_valid = true; | |
166 | } else { | |
167 | i = cpuidx++; | |
168 | } | |
169 | ||
ce7b1756 LP |
170 | if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than " |
171 | "max cores %u, capping them\n", | |
172 | cpuidx, nr_cpu_ids)) { | |
173 | cpuidx = nr_cpu_ids; | |
a0ae0240 | 174 | break; |
ce7b1756 LP |
175 | } |
176 | ||
177 | tmp_map[i] = hwid; | |
6c3ff8b1 SB |
178 | |
179 | if (!found_method) | |
180 | found_method = set_smp_ops_by_method(cpu); | |
a0ae0240 LP |
181 | } |
182 | ||
6c3ff8b1 SB |
183 | /* |
184 | * Fallback to an enable-method in the cpus node if nothing found in | |
185 | * a cpu node. | |
186 | */ | |
187 | if (!found_method) | |
188 | set_smp_ops_by_method(cpus); | |
189 | ||
8d5bc1a6 OJ |
190 | if (!bootcpu_valid) { |
191 | pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n"); | |
a0ae0240 | 192 | return; |
8d5bc1a6 | 193 | } |
a0ae0240 LP |
194 | |
195 | /* | |
196 | * Since the boot CPU node contains proper data, and all nodes have | |
197 | * a reg property, the DT CPU list can be considered valid and the | |
198 | * logical map created in smp_setup_processor_id() can be overridden | |
199 | */ | |
200 | for (i = 0; i < cpuidx; i++) { | |
201 | set_cpu_possible(i, true); | |
202 | cpu_logical_map(i) = tmp_map[i]; | |
203 | pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i)); | |
204 | } | |
205 | } | |
206 | ||
973e02c1 SK |
207 | bool arch_match_cpu_phys_id(int cpu, u64 phys_id) |
208 | { | |
e44ef891 | 209 | return phys_id == cpu_logical_map(cpu); |
973e02c1 SK |
210 | } |
211 | ||
6d67a9f6 RH |
212 | static const void * __init arch_get_next_mach(const char *const **match) |
213 | { | |
214 | static const struct machine_desc *mdesc = __arch_info_begin; | |
215 | const struct machine_desc *m = mdesc; | |
216 | ||
217 | if (m >= __arch_info_end) | |
218 | return NULL; | |
219 | ||
220 | mdesc++; | |
221 | *match = m->dt_compat; | |
222 | return m; | |
223 | } | |
224 | ||
93c02ab4 GL |
225 | /** |
226 | * setup_machine_fdt - Machine setup when an dtb was passed to the kernel | |
227 | * @dt_phys: physical address of dt blob | |
228 | * | |
229 | * If a dtb was passed to the kernel in r2, then use it to choose the | |
230 | * correct machine_desc and to setup the system. | |
231 | */ | |
ff69a4c8 | 232 | const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) |
93c02ab4 | 233 | { |
ff69a4c8 | 234 | const struct machine_desc *mdesc, *mdesc_best = NULL; |
93c02ab4 | 235 | |
883a106b AB |
236 | #ifdef CONFIG_ARCH_MULTIPLATFORM |
237 | DT_MACHINE_START(GENERIC_DT, "Generic DT based system") | |
238 | MACHINE_END | |
239 | ||
ff69a4c8 | 240 | mdesc_best = &__mach_desc_GENERIC_DT; |
883a106b AB |
241 | #endif |
242 | ||
56dc1f47 | 243 | if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) |
f506cd48 NP |
244 | return NULL; |
245 | ||
6d67a9f6 | 246 | mdesc = of_flat_dt_match_machine(mdesc_best, arch_get_next_mach); |
93c02ab4 | 247 | |
6d67a9f6 | 248 | if (!mdesc) { |
93c02ab4 GL |
249 | const char *prop; |
250 | long size; | |
6d67a9f6 | 251 | unsigned long dt_root; |
93c02ab4 GL |
252 | |
253 | early_print("\nError: unrecognized/unsupported " | |
254 | "device tree compatible list:\n[ "); | |
255 | ||
6d67a9f6 | 256 | dt_root = of_get_flat_dt_root(); |
93c02ab4 GL |
257 | prop = of_get_flat_dt_prop(dt_root, "compatible", &size); |
258 | while (size > 0) { | |
259 | early_print("'%s' ", prop); | |
260 | size -= strlen(prop) + 1; | |
261 | prop += strlen(prop) + 1; | |
262 | } | |
263 | early_print("]\n\n"); | |
264 | ||
265 | dump_machine_table(); /* does not return */ | |
266 | } | |
267 | ||
93c02ab4 | 268 | /* Change machine number to match the mdesc we're using */ |
6d67a9f6 | 269 | __machine_arch_type = mdesc->nr; |
93c02ab4 | 270 | |
6d67a9f6 | 271 | return mdesc; |
93c02ab4 | 272 | } |