Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
6f6f6a70 | 18 | #include <asm/assembler.h> |
f09b9979 | 19 | #include <asm/memory.h> |
753790e7 RK |
20 | #include <asm/glue-df.h> |
21 | #include <asm/glue-pf.h> | |
1da177e4 | 22 | #include <asm/vfpmacros.h> |
243c8654 | 23 | #ifndef CONFIG_MULTI_IRQ_HANDLER |
a09e64fb | 24 | #include <mach/entry-macro.S> |
243c8654 | 25 | #endif |
d6551e88 | 26 | #include <asm/thread_notify.h> |
c4c5716e | 27 | #include <asm/unwind.h> |
cc20d429 | 28 | #include <asm/unistd.h> |
f159f4ed | 29 | #include <asm/tls.h> |
9f97da78 | 30 | #include <asm/system_info.h> |
1da177e4 LT |
31 | |
32 | #include "entry-header.S" | |
cd544ce7 | 33 | #include <asm/entry-macro-multi.S> |
a0266c21 | 34 | #include <asm/probes.h> |
1da177e4 | 35 | |
187a51ad | 36 | /* |
d9600c99 | 37 | * Interrupt handling. |
187a51ad RK |
38 | */ |
39 | .macro irq_handler | |
52108641 | 40 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
d9600c99 | 41 | ldr r1, =handle_arch_irq |
52108641 | 42 | mov r0, sp |
52108641 | 43 | adr lr, BSYM(9997f) |
abeb24ae MZ |
44 | ldr pc, [r1] |
45 | #else | |
cd544ce7 | 46 | arch_irq_handler_default |
abeb24ae | 47 | #endif |
f00ec48f | 48 | 9997: |
187a51ad RK |
49 | .endm |
50 | ||
ac8b9c1c | 51 | .macro pabt_helper |
8dfe7ac9 | 52 | @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 |
ac8b9c1c | 53 | #ifdef MULTI_PABORT |
0402bece | 54 | ldr ip, .LCprocfns |
ac8b9c1c | 55 | mov lr, pc |
0402bece | 56 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
ac8b9c1c RK |
57 | #else |
58 | bl CPU_PABORT_HANDLER | |
59 | #endif | |
60 | .endm | |
61 | ||
62 | .macro dabt_helper | |
63 | ||
64 | @ | |
65 | @ Call the processor-specific abort handler: | |
66 | @ | |
da740472 | 67 | @ r2 - pt_regs |
3e287bec RK |
68 | @ r4 - aborted context pc |
69 | @ r5 - aborted context psr | |
ac8b9c1c RK |
70 | @ |
71 | @ The abort handler must return the aborted address in r0, and | |
72 | @ the fault status register in r1. r9 must be preserved. | |
73 | @ | |
74 | #ifdef MULTI_DABORT | |
0402bece | 75 | ldr ip, .LCprocfns |
ac8b9c1c | 76 | mov lr, pc |
0402bece | 77 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
ac8b9c1c RK |
78 | #else |
79 | bl CPU_DABORT_HANDLER | |
80 | #endif | |
81 | .endm | |
82 | ||
785d3cd2 NP |
83 | #ifdef CONFIG_KPROBES |
84 | .section .kprobes.text,"ax",%progbits | |
85 | #else | |
86 | .text | |
87 | #endif | |
88 | ||
1da177e4 LT |
89 | /* |
90 | * Invalid mode handlers | |
91 | */ | |
ccea7a19 RK |
92 | .macro inv_entry, reason |
93 | sub sp, sp, #S_FRAME_SIZE | |
b86040a5 CM |
94 | ARM( stmib sp, {r1 - lr} ) |
95 | THUMB( stmia sp, {r0 - r12} ) | |
96 | THUMB( str sp, [sp, #S_SP] ) | |
97 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
98 | mov r1, #\reason |
99 | .endm | |
100 | ||
101 | __pabt_invalid: | |
ccea7a19 RK |
102 | inv_entry BAD_PREFETCH |
103 | b common_invalid | |
93ed3970 | 104 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
105 | |
106 | __dabt_invalid: | |
ccea7a19 RK |
107 | inv_entry BAD_DATA |
108 | b common_invalid | |
93ed3970 | 109 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
110 | |
111 | __irq_invalid: | |
ccea7a19 RK |
112 | inv_entry BAD_IRQ |
113 | b common_invalid | |
93ed3970 | 114 | ENDPROC(__irq_invalid) |
1da177e4 LT |
115 | |
116 | __und_invalid: | |
ccea7a19 RK |
117 | inv_entry BAD_UNDEFINSTR |
118 | ||
119 | @ | |
120 | @ XXX fall through to common_invalid | |
121 | @ | |
122 | ||
123 | @ | |
124 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
125 | @ | |
126 | common_invalid: | |
127 | zero_fp | |
128 | ||
129 | ldmia r0, {r4 - r6} | |
130 | add r0, sp, #S_PC @ here for interlock avoidance | |
131 | mov r7, #-1 @ "" "" "" "" | |
132 | str r4, [sp] @ save preserved r0 | |
133 | stmia r0, {r5 - r7} @ lr_<exception>, | |
134 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 135 | |
1da177e4 | 136 | mov r0, sp |
1da177e4 | 137 | b bad_mode |
93ed3970 | 138 | ENDPROC(__und_invalid) |
1da177e4 LT |
139 | |
140 | /* | |
141 | * SVC mode handlers | |
142 | */ | |
2dede2d8 NP |
143 | |
144 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
145 | #define SPFIX(code...) code | |
146 | #else | |
147 | #define SPFIX(code...) | |
148 | #endif | |
149 | ||
c0e7f7ee | 150 | .macro svc_entry, stack_hole=0, trace=1 |
c4c5716e CM |
151 | UNWIND(.fnstart ) |
152 | UNWIND(.save {r0 - pc} ) | |
b86040a5 CM |
153 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
154 | #ifdef CONFIG_THUMB2_KERNEL | |
155 | SPFIX( str r0, [sp] ) @ temporarily saved | |
156 | SPFIX( mov r0, sp ) | |
157 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
158 | SPFIX( ldr r0, [sp] ) @ restored | |
159 | #else | |
2dede2d8 | 160 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
161 | #endif |
162 | SPFIX( subeq sp, sp, #4 ) | |
163 | stmia sp, {r1 - r12} | |
ccea7a19 | 164 | |
b059bdc3 RK |
165 | ldmia r0, {r3 - r5} |
166 | add r7, sp, #S_SP - 4 @ here for interlock avoidance | |
167 | mov r6, #-1 @ "" "" "" "" | |
168 | add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) | |
169 | SPFIX( addeq r2, r2, #4 ) | |
170 | str r3, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
171 | @ from the exception stack |
172 | ||
b059bdc3 | 173 | mov r3, lr |
1da177e4 LT |
174 | |
175 | @ | |
176 | @ We are now ready to fill in the remaining blanks on the stack: | |
177 | @ | |
b059bdc3 RK |
178 | @ r2 - sp_svc |
179 | @ r3 - lr_svc | |
180 | @ r4 - lr_<exception>, already fixed up for correct return/restart | |
181 | @ r5 - spsr_<exception> | |
182 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 | 183 | @ |
b059bdc3 | 184 | stmia r7, {r2 - r6} |
1da177e4 | 185 | |
c0e7f7ee | 186 | .if \trace |
02fe2845 RK |
187 | #ifdef CONFIG_TRACE_IRQFLAGS |
188 | bl trace_hardirqs_off | |
189 | #endif | |
c0e7f7ee | 190 | .endif |
f2741b78 | 191 | .endm |
1da177e4 | 192 | |
f2741b78 RK |
193 | .align 5 |
194 | __dabt_svc: | |
195 | svc_entry | |
1da177e4 | 196 | mov r2, sp |
da740472 | 197 | dabt_helper |
e16b31bf | 198 | THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR |
b059bdc3 | 199 | svc_exit r5 @ return from exception |
c4c5716e | 200 | UNWIND(.fnend ) |
93ed3970 | 201 | ENDPROC(__dabt_svc) |
1da177e4 LT |
202 | |
203 | .align 5 | |
204 | __irq_svc: | |
ccea7a19 | 205 | svc_entry |
187a51ad | 206 | irq_handler |
1613cc11 | 207 | |
1da177e4 | 208 | #ifdef CONFIG_PREEMPT |
1613cc11 RK |
209 | get_thread_info tsk |
210 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
706fdd9f | 211 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
212 | teq r8, #0 @ if preempt count != 0 |
213 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
214 | tst r0, #_TIF_NEED_RESCHED |
215 | blne svc_preempt | |
1da177e4 | 216 | #endif |
30891c90 | 217 | |
9b56febe | 218 | svc_exit r5, irq = 1 @ return from exception |
c4c5716e | 219 | UNWIND(.fnend ) |
93ed3970 | 220 | ENDPROC(__irq_svc) |
1da177e4 LT |
221 | |
222 | .ltorg | |
223 | ||
224 | #ifdef CONFIG_PREEMPT | |
225 | svc_preempt: | |
28fab1a2 | 226 | mov r8, lr |
1da177e4 | 227 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 228 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 229 | tst r0, #_TIF_NEED_RESCHED |
6ebbf2ce | 230 | reteq r8 @ go again |
1da177e4 LT |
231 | b 1b |
232 | #endif | |
233 | ||
15ac49b6 RK |
234 | __und_fault: |
235 | @ Correct the PC such that it is pointing at the instruction | |
236 | @ which caused the fault. If the faulting instruction was ARM | |
237 | @ the PC will be pointing at the next instruction, and have to | |
238 | @ subtract 4. Otherwise, it is Thumb, and the PC will be | |
239 | @ pointing at the second half of the Thumb instruction. We | |
240 | @ have to subtract 2. | |
241 | ldr r2, [r0, #S_PC] | |
242 | sub r2, r2, r1 | |
243 | str r2, [r0, #S_PC] | |
244 | b do_undefinstr | |
245 | ENDPROC(__und_fault) | |
246 | ||
1da177e4 LT |
247 | .align 5 |
248 | __und_svc: | |
d30a0c8b NP |
249 | #ifdef CONFIG_KPROBES |
250 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
251 | @ it obviously needs free stack space which then will belong to | |
252 | @ the saved context. | |
a0266c21 | 253 | svc_entry MAX_STACK_SIZE |
d30a0c8b | 254 | #else |
ccea7a19 | 255 | svc_entry |
d30a0c8b | 256 | #endif |
1da177e4 LT |
257 | @ |
258 | @ call emulation code, which returns using r9 if it has emulated | |
259 | @ the instruction, or the more conventional lr if we are to treat | |
260 | @ this as a real undefined instruction | |
261 | @ | |
262 | @ r0 - instruction | |
263 | @ | |
15ac49b6 | 264 | #ifndef CONFIG_THUMB2_KERNEL |
b059bdc3 | 265 | ldr r0, [r4, #-4] |
83e686ea | 266 | #else |
15ac49b6 | 267 | mov r1, #2 |
b059bdc3 | 268 | ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 |
85519189 | 269 | cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 |
15ac49b6 RK |
270 | blo __und_svc_fault |
271 | ldrh r9, [r4] @ bottom 16 bits | |
272 | add r4, r4, #2 | |
273 | str r4, [sp, #S_PC] | |
274 | orr r0, r9, r0, lsl #16 | |
83e686ea | 275 | #endif |
15ac49b6 | 276 | adr r9, BSYM(__und_svc_finish) |
b059bdc3 | 277 | mov r2, r4 |
1da177e4 LT |
278 | bl call_fpe |
279 | ||
15ac49b6 RK |
280 | mov r1, #4 @ PC correction to apply |
281 | __und_svc_fault: | |
1da177e4 | 282 | mov r0, sp @ struct pt_regs *regs |
15ac49b6 | 283 | bl __und_fault |
1da177e4 | 284 | |
15ac49b6 | 285 | __und_svc_finish: |
b059bdc3 RK |
286 | ldr r5, [sp, #S_PSR] @ Get SVC cpsr |
287 | svc_exit r5 @ return from exception | |
c4c5716e | 288 | UNWIND(.fnend ) |
93ed3970 | 289 | ENDPROC(__und_svc) |
1da177e4 LT |
290 | |
291 | .align 5 | |
292 | __pabt_svc: | |
ccea7a19 | 293 | svc_entry |
4fb28474 | 294 | mov r2, sp @ regs |
8dfe7ac9 | 295 | pabt_helper |
b059bdc3 | 296 | svc_exit r5 @ return from exception |
c4c5716e | 297 | UNWIND(.fnend ) |
93ed3970 | 298 | ENDPROC(__pabt_svc) |
1da177e4 | 299 | |
c0e7f7ee DT |
300 | .align 5 |
301 | __fiq_svc: | |
302 | svc_entry trace=0 | |
303 | mov r0, sp @ struct pt_regs *regs | |
304 | bl handle_fiq_as_nmi | |
305 | svc_exit_via_fiq | |
306 | UNWIND(.fnend ) | |
307 | ENDPROC(__fiq_svc) | |
308 | ||
1da177e4 | 309 | .align 5 |
49f680ea RK |
310 | .LCcralign: |
311 | .word cr_alignment | |
48d7927b | 312 | #ifdef MULTI_DABORT |
1da177e4 LT |
313 | .LCprocfns: |
314 | .word processor | |
315 | #endif | |
316 | .LCfp: | |
317 | .word fp_enter | |
1da177e4 | 318 | |
c0e7f7ee DT |
319 | /* |
320 | * Abort mode handlers | |
321 | */ | |
322 | ||
323 | @ | |
324 | @ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode | |
325 | @ and reuses the same macros. However in abort mode we must also | |
326 | @ save/restore lr_abt and spsr_abt to make nested aborts safe. | |
327 | @ | |
328 | .align 5 | |
329 | __fiq_abt: | |
330 | svc_entry trace=0 | |
331 | ||
332 | ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
333 | THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
334 | THUMB( msr cpsr_c, r0 ) | |
335 | mov r1, lr @ Save lr_abt | |
336 | mrs r2, spsr @ Save spsr_abt, abort is now safe | |
337 | ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
338 | THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
339 | THUMB( msr cpsr_c, r0 ) | |
340 | stmfd sp!, {r1 - r2} | |
341 | ||
342 | add r0, sp, #8 @ struct pt_regs *regs | |
343 | bl handle_fiq_as_nmi | |
344 | ||
345 | ldmfd sp!, {r1 - r2} | |
346 | ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
347 | THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
348 | THUMB( msr cpsr_c, r0 ) | |
349 | mov lr, r1 @ Restore lr_abt, abort is unsafe | |
350 | msr spsr_cxsf, r2 @ Restore spsr_abt | |
351 | ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
352 | THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
353 | THUMB( msr cpsr_c, r0 ) | |
354 | ||
355 | svc_exit_via_fiq | |
356 | UNWIND(.fnend ) | |
357 | ENDPROC(__fiq_abt) | |
358 | ||
1da177e4 LT |
359 | /* |
360 | * User mode handlers | |
2dede2d8 NP |
361 | * |
362 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 363 | */ |
2dede2d8 NP |
364 | |
365 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
366 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
367 | #endif | |
368 | ||
c0e7f7ee | 369 | .macro usr_entry, trace=1 |
c4c5716e CM |
370 | UNWIND(.fnstart ) |
371 | UNWIND(.cantunwind ) @ don't unwind the user space | |
ccea7a19 | 372 | sub sp, sp, #S_FRAME_SIZE |
b86040a5 CM |
373 | ARM( stmib sp, {r1 - r12} ) |
374 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 | 375 | |
195b58ad RK |
376 | ATRAP( mrc p15, 0, r7, c1, c0, 0) |
377 | ATRAP( ldr r8, .LCcralign) | |
378 | ||
b059bdc3 | 379 | ldmia r0, {r3 - r5} |
ccea7a19 | 380 | add r0, sp, #S_PC @ here for interlock avoidance |
b059bdc3 | 381 | mov r6, #-1 @ "" "" "" "" |
ccea7a19 | 382 | |
b059bdc3 | 383 | str r3, [sp] @ save the "real" r0 copied |
ccea7a19 | 384 | @ from the exception stack |
1da177e4 | 385 | |
195b58ad RK |
386 | ATRAP( ldr r8, [r8, #0]) |
387 | ||
1da177e4 LT |
388 | @ |
389 | @ We are now ready to fill in the remaining blanks on the stack: | |
390 | @ | |
b059bdc3 RK |
391 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
392 | @ r5 - spsr_<exception> | |
393 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 LT |
394 | @ |
395 | @ Also, separately save sp_usr and lr_usr | |
396 | @ | |
b059bdc3 | 397 | stmia r0, {r4 - r6} |
b86040a5 CM |
398 | ARM( stmdb r0, {sp, lr}^ ) |
399 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 | 400 | |
1da177e4 | 401 | @ Enable the alignment trap while in kernel mode |
195b58ad RK |
402 | ATRAP( teq r8, r7) |
403 | ATRAP( mcrne p15, 0, r8, c1, c0, 0) | |
1da177e4 LT |
404 | |
405 | @ | |
406 | @ Clear FP to mark the first stack frame | |
407 | @ | |
408 | zero_fp | |
f2741b78 | 409 | |
c0e7f7ee | 410 | .if \trace |
f2741b78 RK |
411 | #ifdef CONFIG_IRQSOFF_TRACER |
412 | bl trace_hardirqs_off | |
413 | #endif | |
b0088480 | 414 | ct_user_exit save = 0 |
c0e7f7ee | 415 | .endif |
1da177e4 LT |
416 | .endm |
417 | ||
b49c0f24 | 418 | .macro kuser_cmpxchg_check |
1b16c4bc RK |
419 | #if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) && \ |
420 | !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
b49c0f24 NP |
421 | #ifndef CONFIG_MMU |
422 | #warning "NPTL on non MMU needs fixing" | |
423 | #else | |
424 | @ Make sure our user space atomic helper is restarted | |
425 | @ if it was interrupted in a critical region. Here we | |
426 | @ perform a quick test inline since it should be false | |
427 | @ 99.9999% of the time. The rest is done out of line. | |
b059bdc3 | 428 | cmp r4, #TASK_SIZE |
40fb79c8 | 429 | blhs kuser_cmpxchg64_fixup |
b49c0f24 NP |
430 | #endif |
431 | #endif | |
432 | .endm | |
433 | ||
1da177e4 LT |
434 | .align 5 |
435 | __dabt_usr: | |
ccea7a19 | 436 | usr_entry |
b49c0f24 | 437 | kuser_cmpxchg_check |
1da177e4 | 438 | mov r2, sp |
da740472 RK |
439 | dabt_helper |
440 | b ret_from_exception | |
c4c5716e | 441 | UNWIND(.fnend ) |
93ed3970 | 442 | ENDPROC(__dabt_usr) |
1da177e4 LT |
443 | |
444 | .align 5 | |
445 | __irq_usr: | |
ccea7a19 | 446 | usr_entry |
bc089602 | 447 | kuser_cmpxchg_check |
187a51ad | 448 | irq_handler |
1613cc11 | 449 | get_thread_info tsk |
1da177e4 | 450 | mov why, #0 |
9fc2552a | 451 | b ret_to_user_from_irq |
c4c5716e | 452 | UNWIND(.fnend ) |
93ed3970 | 453 | ENDPROC(__irq_usr) |
1da177e4 LT |
454 | |
455 | .ltorg | |
456 | ||
457 | .align 5 | |
458 | __und_usr: | |
ccea7a19 | 459 | usr_entry |
bc089602 | 460 | |
b059bdc3 RK |
461 | mov r2, r4 |
462 | mov r3, r5 | |
1da177e4 | 463 | |
15ac49b6 RK |
464 | @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the |
465 | @ faulting instruction depending on Thumb mode. | |
466 | @ r3 = regs->ARM_cpsr | |
1da177e4 | 467 | @ |
15ac49b6 RK |
468 | @ The emulation code returns using r9 if it has emulated the |
469 | @ instruction, or the more conventional lr if we are to treat | |
470 | @ this as a real undefined instruction | |
1da177e4 | 471 | @ |
b86040a5 | 472 | adr r9, BSYM(ret_from_exception) |
15ac49b6 | 473 | |
1417a6b8 CM |
474 | @ IRQs must be enabled before attempting to read the instruction from |
475 | @ user space since that could cause a page/translation fault if the | |
476 | @ page table was modified by another CPU. | |
477 | enable_irq | |
478 | ||
cb170a45 | 479 | tst r3, #PSR_T_BIT @ Thumb mode? |
15ac49b6 RK |
480 | bne __und_usr_thumb |
481 | sub r4, r2, #4 @ ARM instr at LR - 4 | |
482 | 1: ldrt r0, [r4] | |
457c2403 BD |
483 | ARM_BE8(rev r0, r0) @ little endian instruction |
484 | ||
15ac49b6 RK |
485 | @ r0 = 32-bit ARM instruction which caused the exception |
486 | @ r2 = PC value for the following instruction (:= regs->ARM_pc) | |
487 | @ r4 = PC value for the faulting instruction | |
488 | @ lr = 32-bit undefined instruction function | |
489 | adr lr, BSYM(__und_usr_fault_32) | |
490 | b call_fpe | |
491 | ||
492 | __und_usr_thumb: | |
cb170a45 | 493 | @ Thumb instruction |
15ac49b6 | 494 | sub r4, r2, #2 @ First half of thumb instr at LR - 2 |
ef4c5368 DM |
495 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
496 | /* | |
497 | * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms | |
498 | * can never be supported in a single kernel, this code is not applicable at | |
499 | * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be | |
500 | * made about .arch directives. | |
501 | */ | |
502 | #if __LINUX_ARM_ARCH__ < 7 | |
503 | /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ | |
504 | #define NEED_CPU_ARCHITECTURE | |
505 | ldr r5, .LCcpu_architecture | |
506 | ldr r5, [r5] | |
507 | cmp r5, #CPU_ARCH_ARMv7 | |
15ac49b6 | 508 | blo __und_usr_fault_16 @ 16bit undefined instruction |
ef4c5368 DM |
509 | /* |
510 | * The following code won't get run unless the running CPU really is v7, so | |
511 | * coding round the lack of ldrht on older arches is pointless. Temporarily | |
512 | * override the assembler target arch with the minimum required instead: | |
513 | */ | |
514 | .arch armv6t2 | |
515 | #endif | |
15ac49b6 | 516 | 2: ldrht r5, [r4] |
f8fe23ec | 517 | ARM_BE8(rev16 r5, r5) @ little endian instruction |
85519189 | 518 | cmp r5, #0xe800 @ 32bit instruction if xx != 0 |
15ac49b6 RK |
519 | blo __und_usr_fault_16 @ 16bit undefined instruction |
520 | 3: ldrht r0, [r2] | |
f8fe23ec | 521 | ARM_BE8(rev16 r0, r0) @ little endian instruction |
cb170a45 | 522 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 |
15ac49b6 | 523 | str r2, [sp, #S_PC] @ it's a 2x16bit instr, update |
cb170a45 | 524 | orr r0, r0, r5, lsl #16 |
15ac49b6 RK |
525 | adr lr, BSYM(__und_usr_fault_32) |
526 | @ r0 = the two 16-bit Thumb instructions which caused the exception | |
527 | @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) | |
528 | @ r4 = PC value for the first 16-bit Thumb instruction | |
529 | @ lr = 32bit undefined instruction function | |
ef4c5368 DM |
530 | |
531 | #if __LINUX_ARM_ARCH__ < 7 | |
532 | /* If the target arch was overridden, change it back: */ | |
533 | #ifdef CONFIG_CPU_32v6K | |
534 | .arch armv6k | |
cb170a45 | 535 | #else |
ef4c5368 DM |
536 | .arch armv6 |
537 | #endif | |
538 | #endif /* __LINUX_ARM_ARCH__ < 7 */ | |
539 | #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ | |
15ac49b6 | 540 | b __und_usr_fault_16 |
cb170a45 | 541 | #endif |
15ac49b6 | 542 | UNWIND(.fnend) |
93ed3970 | 543 | ENDPROC(__und_usr) |
cb170a45 | 544 | |
1da177e4 | 545 | /* |
15ac49b6 | 546 | * The out of line fixup for the ldrt instructions above. |
1da177e4 | 547 | */ |
c4a84ae3 | 548 | .pushsection .text.fixup, "ax" |
667d1b48 | 549 | .align 2 |
3780f7ab | 550 | 4: str r4, [sp, #S_PC] @ retry current instruction |
6ebbf2ce | 551 | ret r9 |
4260415f RK |
552 | .popsection |
553 | .pushsection __ex_table,"a" | |
cb170a45 | 554 | .long 1b, 4b |
c89cefed | 555 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
cb170a45 PB |
556 | .long 2b, 4b |
557 | .long 3b, 4b | |
558 | #endif | |
4260415f | 559 | .popsection |
1da177e4 LT |
560 | |
561 | /* | |
562 | * Check whether the instruction is a co-processor instruction. | |
563 | * If yes, we need to call the relevant co-processor handler. | |
564 | * | |
565 | * Note that we don't do a full check here for the co-processor | |
566 | * instructions; all instructions with bit 27 set are well | |
567 | * defined. The only instructions that should fault are the | |
568 | * co-processor instructions. However, we have to watch out | |
569 | * for the ARM6/ARM7 SWI bug. | |
570 | * | |
b5872db4 CM |
571 | * NEON is a special case that has to be handled here. Not all |
572 | * NEON instructions are co-processor instructions, so we have | |
573 | * to make a special case of checking for them. Plus, there's | |
574 | * five groups of them, so we have a table of mask/opcode pairs | |
575 | * to check against, and if any match then we branch off into the | |
576 | * NEON handler code. | |
577 | * | |
1da177e4 | 578 | * Emulators may wish to make use of the following registers: |
15ac49b6 RK |
579 | * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) |
580 | * r2 = PC value to resume execution after successful emulation | |
db6ccbb6 | 581 | * r9 = normal "successful" return address |
15ac49b6 | 582 | * r10 = this threads thread_info structure |
db6ccbb6 | 583 | * lr = unrecognised instruction return address |
1417a6b8 | 584 | * IRQs enabled, FIQs enabled. |
1da177e4 | 585 | */ |
cb170a45 PB |
586 | @ |
587 | @ Fall-through from Thumb-2 __und_usr | |
588 | @ | |
589 | #ifdef CONFIG_NEON | |
d3f79584 | 590 | get_thread_info r10 @ get current thread |
cb170a45 PB |
591 | adr r6, .LCneon_thumb_opcodes |
592 | b 2f | |
593 | #endif | |
1da177e4 | 594 | call_fpe: |
d3f79584 | 595 | get_thread_info r10 @ get current thread |
b5872db4 | 596 | #ifdef CONFIG_NEON |
cb170a45 | 597 | adr r6, .LCneon_arm_opcodes |
d3f79584 | 598 | 2: ldr r5, [r6], #4 @ mask value |
b5872db4 | 599 | ldr r7, [r6], #4 @ opcode bits matching in mask |
d3f79584 RK |
600 | cmp r5, #0 @ end mask? |
601 | beq 1f | |
602 | and r8, r0, r5 | |
b5872db4 CM |
603 | cmp r8, r7 @ NEON instruction? |
604 | bne 2b | |
b5872db4 CM |
605 | mov r7, #1 |
606 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
607 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
608 | b do_vfp @ let VFP handler handle this | |
609 | 1: | |
610 | #endif | |
1da177e4 | 611 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 612 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
6ebbf2ce | 613 | reteq lr |
1da177e4 | 614 | and r8, r0, #0x00000f00 @ mask out CP number |
b86040a5 | 615 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
616 | mov r7, #1 |
617 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
618 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
619 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
620 | #ifdef CONFIG_IWMMXT |
621 | @ Test if we need to give access to iWMMXt coprocessors | |
622 | ldr r5, [r10, #TI_FLAGS] | |
623 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
624 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
625 | bcs iwmmxt_task_enable | |
626 | #endif | |
b86040a5 CM |
627 | ARM( add pc, pc, r8, lsr #6 ) |
628 | THUMB( lsl r8, r8, #2 ) | |
629 | THUMB( add pc, r8 ) | |
630 | nop | |
631 | ||
6ebbf2ce | 632 | ret.w lr @ CP#0 |
b86040a5 CM |
633 | W(b) do_fpe @ CP#1 (FPE) |
634 | W(b) do_fpe @ CP#2 (FPE) | |
6ebbf2ce | 635 | ret.w lr @ CP#3 |
c17fad11 LB |
636 | #ifdef CONFIG_CRUNCH |
637 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
638 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
639 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
640 | #else | |
6ebbf2ce RK |
641 | ret.w lr @ CP#4 |
642 | ret.w lr @ CP#5 | |
643 | ret.w lr @ CP#6 | |
c17fad11 | 644 | #endif |
6ebbf2ce RK |
645 | ret.w lr @ CP#7 |
646 | ret.w lr @ CP#8 | |
647 | ret.w lr @ CP#9 | |
1da177e4 | 648 | #ifdef CONFIG_VFP |
b86040a5 CM |
649 | W(b) do_vfp @ CP#10 (VFP) |
650 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 651 | #else |
6ebbf2ce RK |
652 | ret.w lr @ CP#10 (VFP) |
653 | ret.w lr @ CP#11 (VFP) | |
1da177e4 | 654 | #endif |
6ebbf2ce RK |
655 | ret.w lr @ CP#12 |
656 | ret.w lr @ CP#13 | |
657 | ret.w lr @ CP#14 (Debug) | |
658 | ret.w lr @ CP#15 (Control) | |
1da177e4 | 659 | |
ef4c5368 DM |
660 | #ifdef NEED_CPU_ARCHITECTURE |
661 | .align 2 | |
662 | .LCcpu_architecture: | |
663 | .word __cpu_architecture | |
664 | #endif | |
665 | ||
b5872db4 CM |
666 | #ifdef CONFIG_NEON |
667 | .align 6 | |
668 | ||
cb170a45 | 669 | .LCneon_arm_opcodes: |
b5872db4 CM |
670 | .word 0xfe000000 @ mask |
671 | .word 0xf2000000 @ opcode | |
672 | ||
673 | .word 0xff100000 @ mask | |
674 | .word 0xf4000000 @ opcode | |
675 | ||
cb170a45 PB |
676 | .word 0x00000000 @ mask |
677 | .word 0x00000000 @ opcode | |
678 | ||
679 | .LCneon_thumb_opcodes: | |
680 | .word 0xef000000 @ mask | |
681 | .word 0xef000000 @ opcode | |
682 | ||
683 | .word 0xff100000 @ mask | |
684 | .word 0xf9000000 @ opcode | |
685 | ||
b5872db4 CM |
686 | .word 0x00000000 @ mask |
687 | .word 0x00000000 @ opcode | |
688 | #endif | |
689 | ||
1da177e4 LT |
690 | do_fpe: |
691 | ldr r4, .LCfp | |
692 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
693 | ldr pc, [r4] @ Call FP module USR entry point | |
694 | ||
695 | /* | |
696 | * The FP module is called with these registers set: | |
697 | * r0 = instruction | |
698 | * r2 = PC+4 | |
699 | * r9 = normal "successful" return address | |
700 | * r10 = FP workspace | |
701 | * lr = unrecognised FP instruction return address | |
702 | */ | |
703 | ||
124efc27 | 704 | .pushsection .data |
1da177e4 | 705 | ENTRY(fp_enter) |
db6ccbb6 | 706 | .word no_fp |
124efc27 | 707 | .popsection |
1da177e4 | 708 | |
83e686ea | 709 | ENTRY(no_fp) |
6ebbf2ce | 710 | ret lr |
83e686ea | 711 | ENDPROC(no_fp) |
db6ccbb6 | 712 | |
15ac49b6 RK |
713 | __und_usr_fault_32: |
714 | mov r1, #4 | |
715 | b 1f | |
716 | __und_usr_fault_16: | |
717 | mov r1, #2 | |
1417a6b8 | 718 | 1: mov r0, sp |
b86040a5 | 719 | adr lr, BSYM(ret_from_exception) |
15ac49b6 RK |
720 | b __und_fault |
721 | ENDPROC(__und_usr_fault_32) | |
722 | ENDPROC(__und_usr_fault_16) | |
1da177e4 LT |
723 | |
724 | .align 5 | |
725 | __pabt_usr: | |
ccea7a19 | 726 | usr_entry |
4fb28474 | 727 | mov r2, sp @ regs |
8dfe7ac9 | 728 | pabt_helper |
c4c5716e | 729 | UNWIND(.fnend ) |
1da177e4 LT |
730 | /* fall through */ |
731 | /* | |
732 | * This is the return code to user mode for abort handlers | |
733 | */ | |
734 | ENTRY(ret_from_exception) | |
c4c5716e CM |
735 | UNWIND(.fnstart ) |
736 | UNWIND(.cantunwind ) | |
1da177e4 LT |
737 | get_thread_info tsk |
738 | mov why, #0 | |
739 | b ret_to_user | |
c4c5716e | 740 | UNWIND(.fnend ) |
93ed3970 CM |
741 | ENDPROC(__pabt_usr) |
742 | ENDPROC(ret_from_exception) | |
1da177e4 | 743 | |
c0e7f7ee DT |
744 | .align 5 |
745 | __fiq_usr: | |
746 | usr_entry trace=0 | |
747 | kuser_cmpxchg_check | |
748 | mov r0, sp @ struct pt_regs *regs | |
749 | bl handle_fiq_as_nmi | |
750 | get_thread_info tsk | |
751 | restore_user_regs fast = 0, offset = 0 | |
752 | UNWIND(.fnend ) | |
753 | ENDPROC(__fiq_usr) | |
754 | ||
1da177e4 LT |
755 | /* |
756 | * Register switch for ARMv3 and ARMv4 processors | |
757 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
758 | * previous and next are guaranteed not to be the same. | |
759 | */ | |
760 | ENTRY(__switch_to) | |
c4c5716e CM |
761 | UNWIND(.fnstart ) |
762 | UNWIND(.cantunwind ) | |
1da177e4 | 763 | add ip, r1, #TI_CPU_SAVE |
b86040a5 CM |
764 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
765 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
766 | THUMB( str sp, [ip], #4 ) | |
767 | THUMB( str lr, [ip], #4 ) | |
a4780ade AH |
768 | ldr r4, [r2, #TI_TP_VALUE] |
769 | ldr r5, [r2, #TI_TP_VALUE + 4] | |
247055aa | 770 | #ifdef CONFIG_CPU_USE_DOMAINS |
d6551e88 | 771 | ldr r6, [r2, #TI_CPU_DOMAIN] |
afeb90ca | 772 | #endif |
a4780ade | 773 | switch_tls r1, r4, r5, r3, r7 |
df0698be NP |
774 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
775 | ldr r7, [r2, #TI_TASK] | |
776 | ldr r8, =__stack_chk_guard | |
777 | ldr r7, [r7, #TSK_STACK_CANARY] | |
778 | #endif | |
247055aa | 779 | #ifdef CONFIG_CPU_USE_DOMAINS |
1da177e4 | 780 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 781 | #endif |
d6551e88 RK |
782 | mov r5, r0 |
783 | add r4, r2, #TI_CPU_SAVE | |
784 | ldr r0, =thread_notify_head | |
785 | mov r1, #THREAD_NOTIFY_SWITCH | |
786 | bl atomic_notifier_call_chain | |
df0698be NP |
787 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
788 | str r7, [r8] | |
789 | #endif | |
b86040a5 | 790 | THUMB( mov ip, r4 ) |
d6551e88 | 791 | mov r0, r5 |
b86040a5 CM |
792 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
793 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
794 | THUMB( ldr sp, [ip], #4 ) | |
795 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 796 | UNWIND(.fnend ) |
93ed3970 | 797 | ENDPROC(__switch_to) |
1da177e4 LT |
798 | |
799 | __INIT | |
2d2669b6 NP |
800 | |
801 | /* | |
802 | * User helpers. | |
803 | * | |
2d2669b6 NP |
804 | * Each segment is 32-byte aligned and will be moved to the top of the high |
805 | * vector page. New segments (if ever needed) must be added in front of | |
806 | * existing ones. This mechanism should be used only for things that are | |
807 | * really small and justified, and not be abused freely. | |
808 | * | |
37b83046 | 809 | * See Documentation/arm/kernel_user_helpers.txt for formal definitions. |
2d2669b6 | 810 | */ |
b86040a5 | 811 | THUMB( .arm ) |
2d2669b6 | 812 | |
ba9b5d76 NP |
813 | .macro usr_ret, reg |
814 | #ifdef CONFIG_ARM_THUMB | |
815 | bx \reg | |
816 | #else | |
6ebbf2ce | 817 | ret \reg |
ba9b5d76 NP |
818 | #endif |
819 | .endm | |
820 | ||
5b43e7a3 RK |
821 | .macro kuser_pad, sym, size |
822 | .if (. - \sym) & 3 | |
823 | .rept 4 - (. - \sym) & 3 | |
824 | .byte 0 | |
825 | .endr | |
826 | .endif | |
827 | .rept (\size - (. - \sym)) / 4 | |
828 | .word 0xe7fddef1 | |
829 | .endr | |
830 | .endm | |
831 | ||
f6f91b0d | 832 | #ifdef CONFIG_KUSER_HELPERS |
2d2669b6 NP |
833 | .align 5 |
834 | .globl __kuser_helper_start | |
835 | __kuser_helper_start: | |
836 | ||
7c612bfd | 837 | /* |
40fb79c8 NP |
838 | * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular |
839 | * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. | |
7c612bfd NP |
840 | */ |
841 | ||
40fb79c8 NP |
842 | __kuser_cmpxchg64: @ 0xffff0f60 |
843 | ||
844 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
845 | ||
846 | /* | |
847 | * Poor you. No fast solution possible... | |
848 | * The kernel itself must perform the operation. | |
849 | * A special ghost syscall is used for that (see traps.c). | |
850 | */ | |
851 | stmfd sp!, {r7, lr} | |
852 | ldr r7, 1f @ it's 20 bits | |
853 | swi __ARM_NR_cmpxchg64 | |
854 | ldmfd sp!, {r7, pc} | |
855 | 1: .word __ARM_NR_cmpxchg64 | |
856 | ||
857 | #elif defined(CONFIG_CPU_32v6K) | |
858 | ||
859 | stmfd sp!, {r4, r5, r6, r7} | |
860 | ldrd r4, r5, [r0] @ load old val | |
861 | ldrd r6, r7, [r1] @ load new val | |
862 | smp_dmb arm | |
863 | 1: ldrexd r0, r1, [r2] @ load current val | |
864 | eors r3, r0, r4 @ compare with oldval (1) | |
865 | eoreqs r3, r1, r5 @ compare with oldval (2) | |
866 | strexdeq r3, r6, r7, [r2] @ store newval if eq | |
867 | teqeq r3, #1 @ success? | |
868 | beq 1b @ if no then retry | |
ed3768a8 | 869 | smp_dmb arm |
40fb79c8 NP |
870 | rsbs r0, r3, #0 @ set returned val and C flag |
871 | ldmfd sp!, {r4, r5, r6, r7} | |
5a97d0ae | 872 | usr_ret lr |
40fb79c8 NP |
873 | |
874 | #elif !defined(CONFIG_SMP) | |
875 | ||
876 | #ifdef CONFIG_MMU | |
877 | ||
878 | /* | |
879 | * The only thing that can break atomicity in this cmpxchg64 | |
880 | * implementation is either an IRQ or a data abort exception | |
881 | * causing another process/thread to be scheduled in the middle of | |
882 | * the critical sequence. The same strategy as for cmpxchg is used. | |
883 | */ | |
884 | stmfd sp!, {r4, r5, r6, lr} | |
885 | ldmia r0, {r4, r5} @ load old val | |
886 | ldmia r1, {r6, lr} @ load new val | |
887 | 1: ldmia r2, {r0, r1} @ load current val | |
888 | eors r3, r0, r4 @ compare with oldval (1) | |
889 | eoreqs r3, r1, r5 @ compare with oldval (2) | |
890 | 2: stmeqia r2, {r6, lr} @ store newval if eq | |
891 | rsbs r0, r3, #0 @ set return val and C flag | |
892 | ldmfd sp!, {r4, r5, r6, pc} | |
893 | ||
894 | .text | |
895 | kuser_cmpxchg64_fixup: | |
896 | @ Called from kuser_cmpxchg_fixup. | |
3ad55155 | 897 | @ r4 = address of interrupted insn (must be preserved). |
40fb79c8 NP |
898 | @ sp = saved regs. r7 and r8 are clobbered. |
899 | @ 1b = first critical insn, 2b = last critical insn. | |
3ad55155 | 900 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
40fb79c8 NP |
901 | mov r7, #0xffff0fff |
902 | sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) | |
3ad55155 | 903 | subs r8, r4, r7 |
40fb79c8 NP |
904 | rsbcss r8, r8, #(2b - 1b) |
905 | strcs r7, [sp, #S_PC] | |
906 | #if __LINUX_ARM_ARCH__ < 6 | |
907 | bcc kuser_cmpxchg32_fixup | |
908 | #endif | |
6ebbf2ce | 909 | ret lr |
40fb79c8 NP |
910 | .previous |
911 | ||
912 | #else | |
913 | #warning "NPTL on non MMU needs fixing" | |
914 | mov r0, #-1 | |
915 | adds r0, r0, #0 | |
ba9b5d76 | 916 | usr_ret lr |
40fb79c8 NP |
917 | #endif |
918 | ||
919 | #else | |
920 | #error "incoherent kernel configuration" | |
921 | #endif | |
922 | ||
5b43e7a3 | 923 | kuser_pad __kuser_cmpxchg64, 64 |
7c612bfd | 924 | |
7c612bfd | 925 | __kuser_memory_barrier: @ 0xffff0fa0 |
ed3768a8 | 926 | smp_dmb arm |
ba9b5d76 | 927 | usr_ret lr |
7c612bfd | 928 | |
5b43e7a3 | 929 | kuser_pad __kuser_memory_barrier, 32 |
2d2669b6 NP |
930 | |
931 | __kuser_cmpxchg: @ 0xffff0fc0 | |
932 | ||
dcef1f63 | 933 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 934 | |
dcef1f63 NP |
935 | /* |
936 | * Poor you. No fast solution possible... | |
937 | * The kernel itself must perform the operation. | |
938 | * A special ghost syscall is used for that (see traps.c). | |
939 | */ | |
5e097445 | 940 | stmfd sp!, {r7, lr} |
55afd264 | 941 | ldr r7, 1f @ it's 20 bits |
cc20d429 | 942 | swi __ARM_NR_cmpxchg |
5e097445 | 943 | ldmfd sp!, {r7, pc} |
cc20d429 | 944 | 1: .word __ARM_NR_cmpxchg |
dcef1f63 NP |
945 | |
946 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 947 | |
b49c0f24 NP |
948 | #ifdef CONFIG_MMU |
949 | ||
2d2669b6 | 950 | /* |
b49c0f24 NP |
951 | * The only thing that can break atomicity in this cmpxchg |
952 | * implementation is either an IRQ or a data abort exception | |
953 | * causing another process/thread to be scheduled in the middle | |
954 | * of the critical sequence. To prevent this, code is added to | |
955 | * the IRQ and data abort exception handlers to set the pc back | |
956 | * to the beginning of the critical section if it is found to be | |
957 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 958 | */ |
b49c0f24 NP |
959 | 1: ldr r3, [r2] @ load current val |
960 | subs r3, r3, r0 @ compare with oldval | |
961 | 2: streq r1, [r2] @ store newval if eq | |
962 | rsbs r0, r3, #0 @ set return val and C flag | |
963 | usr_ret lr | |
964 | ||
965 | .text | |
40fb79c8 | 966 | kuser_cmpxchg32_fixup: |
b49c0f24 | 967 | @ Called from kuser_cmpxchg_check macro. |
b059bdc3 | 968 | @ r4 = address of interrupted insn (must be preserved). |
b49c0f24 NP |
969 | @ sp = saved regs. r7 and r8 are clobbered. |
970 | @ 1b = first critical insn, 2b = last critical insn. | |
b059bdc3 | 971 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
b49c0f24 NP |
972 | mov r7, #0xffff0fff |
973 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
b059bdc3 | 974 | subs r8, r4, r7 |
b49c0f24 NP |
975 | rsbcss r8, r8, #(2b - 1b) |
976 | strcs r7, [sp, #S_PC] | |
6ebbf2ce | 977 | ret lr |
b49c0f24 NP |
978 | .previous |
979 | ||
49bca4c2 NP |
980 | #else |
981 | #warning "NPTL on non MMU needs fixing" | |
982 | mov r0, #-1 | |
983 | adds r0, r0, #0 | |
ba9b5d76 | 984 | usr_ret lr |
b49c0f24 | 985 | #endif |
2d2669b6 NP |
986 | |
987 | #else | |
988 | ||
ed3768a8 | 989 | smp_dmb arm |
b49c0f24 | 990 | 1: ldrex r3, [r2] |
2d2669b6 NP |
991 | subs r3, r3, r0 |
992 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
993 | teqeq r3, #1 |
994 | beq 1b | |
2d2669b6 | 995 | rsbs r0, r3, #0 |
b49c0f24 | 996 | /* beware -- each __kuser slot must be 8 instructions max */ |
f00ec48f RK |
997 | ALT_SMP(b __kuser_memory_barrier) |
998 | ALT_UP(usr_ret lr) | |
2d2669b6 NP |
999 | |
1000 | #endif | |
1001 | ||
5b43e7a3 | 1002 | kuser_pad __kuser_cmpxchg, 32 |
2d2669b6 | 1003 | |
2d2669b6 | 1004 | __kuser_get_tls: @ 0xffff0fe0 |
f159f4ed | 1005 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
ba9b5d76 | 1006 | usr_ret lr |
f159f4ed | 1007 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
5b43e7a3 RK |
1008 | kuser_pad __kuser_get_tls, 16 |
1009 | .rep 3 | |
f159f4ed TL |
1010 | .word 0 @ 0xffff0ff0 software TLS value, then |
1011 | .endr @ pad up to __kuser_helper_version | |
2d2669b6 | 1012 | |
2d2669b6 NP |
1013 | __kuser_helper_version: @ 0xffff0ffc |
1014 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
1015 | ||
1016 | .globl __kuser_helper_end | |
1017 | __kuser_helper_end: | |
1018 | ||
f6f91b0d RK |
1019 | #endif |
1020 | ||
b86040a5 | 1021 | THUMB( .thumb ) |
2d2669b6 | 1022 | |
1da177e4 LT |
1023 | /* |
1024 | * Vector stubs. | |
1025 | * | |
19accfd3 RK |
1026 | * This code is copied to 0xffff1000 so we can use branches in the |
1027 | * vectors, rather than ldr's. Note that this code must not exceed | |
1028 | * a page size. | |
1da177e4 LT |
1029 | * |
1030 | * Common stub entry macro: | |
1031 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
1032 | * |
1033 | * SP points to a minimal amount of processor-private memory, the address | |
1034 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 1035 | */ |
b7ec4795 | 1036 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
1037 | .align 5 |
1038 | ||
1039 | vector_\name: | |
1da177e4 LT |
1040 | .if \correction |
1041 | sub lr, lr, #\correction | |
1042 | .endif | |
ccea7a19 RK |
1043 | |
1044 | @ | |
1045 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
1046 | @ (parent CPSR) | |
1047 | @ | |
1048 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 1049 | mrs lr, spsr |
ccea7a19 RK |
1050 | str lr, [sp, #8] @ save spsr |
1051 | ||
1da177e4 | 1052 | @ |
ccea7a19 | 1053 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 1054 | @ |
ccea7a19 | 1055 | mrs r0, cpsr |
b86040a5 | 1056 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 1057 | msr spsr_cxsf, r0 |
1da177e4 | 1058 | |
ccea7a19 RK |
1059 | @ |
1060 | @ the branch table must immediately follow this code | |
1061 | @ | |
ccea7a19 | 1062 | and lr, lr, #0x0f |
b86040a5 CM |
1063 | THUMB( adr r0, 1f ) |
1064 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 1065 | mov r0, sp |
b86040a5 | 1066 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 1067 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 1068 | ENDPROC(vector_\name) |
88987ef9 CM |
1069 | |
1070 | .align 2 | |
1071 | @ handler addresses follow this label | |
1072 | 1: | |
1da177e4 LT |
1073 | .endm |
1074 | ||
b9b32bf7 | 1075 | .section .stubs, "ax", %progbits |
1da177e4 | 1076 | __stubs_start: |
19accfd3 RK |
1077 | @ This must be the first word |
1078 | .word vector_swi | |
1079 | ||
1080 | vector_rst: | |
1081 | ARM( swi SYS_ERROR0 ) | |
1082 | THUMB( svc #0 ) | |
1083 | THUMB( nop ) | |
1084 | b vector_und | |
1085 | ||
1da177e4 LT |
1086 | /* |
1087 | * Interrupt dispatcher | |
1088 | */ | |
b7ec4795 | 1089 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1090 | |
1091 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1092 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1093 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1094 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1095 | .long __irq_invalid @ 4 | |
1096 | .long __irq_invalid @ 5 | |
1097 | .long __irq_invalid @ 6 | |
1098 | .long __irq_invalid @ 7 | |
1099 | .long __irq_invalid @ 8 | |
1100 | .long __irq_invalid @ 9 | |
1101 | .long __irq_invalid @ a | |
1102 | .long __irq_invalid @ b | |
1103 | .long __irq_invalid @ c | |
1104 | .long __irq_invalid @ d | |
1105 | .long __irq_invalid @ e | |
1106 | .long __irq_invalid @ f | |
1107 | ||
1108 | /* | |
1109 | * Data abort dispatcher | |
1110 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1111 | */ | |
b7ec4795 | 1112 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1113 | |
1114 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1115 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1116 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1117 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1118 | .long __dabt_invalid @ 4 | |
1119 | .long __dabt_invalid @ 5 | |
1120 | .long __dabt_invalid @ 6 | |
1121 | .long __dabt_invalid @ 7 | |
1122 | .long __dabt_invalid @ 8 | |
1123 | .long __dabt_invalid @ 9 | |
1124 | .long __dabt_invalid @ a | |
1125 | .long __dabt_invalid @ b | |
1126 | .long __dabt_invalid @ c | |
1127 | .long __dabt_invalid @ d | |
1128 | .long __dabt_invalid @ e | |
1129 | .long __dabt_invalid @ f | |
1130 | ||
1131 | /* | |
1132 | * Prefetch abort dispatcher | |
1133 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1134 | */ | |
b7ec4795 | 1135 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1136 | |
1137 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1138 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1139 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1140 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1141 | .long __pabt_invalid @ 4 | |
1142 | .long __pabt_invalid @ 5 | |
1143 | .long __pabt_invalid @ 6 | |
1144 | .long __pabt_invalid @ 7 | |
1145 | .long __pabt_invalid @ 8 | |
1146 | .long __pabt_invalid @ 9 | |
1147 | .long __pabt_invalid @ a | |
1148 | .long __pabt_invalid @ b | |
1149 | .long __pabt_invalid @ c | |
1150 | .long __pabt_invalid @ d | |
1151 | .long __pabt_invalid @ e | |
1152 | .long __pabt_invalid @ f | |
1153 | ||
1154 | /* | |
1155 | * Undef instr entry dispatcher | |
1156 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1157 | */ | |
b7ec4795 | 1158 | vector_stub und, UND_MODE |
1da177e4 LT |
1159 | |
1160 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1161 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1162 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1163 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1164 | .long __und_invalid @ 4 | |
1165 | .long __und_invalid @ 5 | |
1166 | .long __und_invalid @ 6 | |
1167 | .long __und_invalid @ 7 | |
1168 | .long __und_invalid @ 8 | |
1169 | .long __und_invalid @ 9 | |
1170 | .long __und_invalid @ a | |
1171 | .long __und_invalid @ b | |
1172 | .long __und_invalid @ c | |
1173 | .long __und_invalid @ d | |
1174 | .long __und_invalid @ e | |
1175 | .long __und_invalid @ f | |
1176 | ||
1177 | .align 5 | |
1178 | ||
19accfd3 RK |
1179 | /*============================================================================= |
1180 | * Address exception handler | |
1181 | *----------------------------------------------------------------------------- | |
1182 | * These aren't too critical. | |
1183 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1184 | */ | |
1185 | ||
1186 | vector_addrexcptn: | |
1187 | b vector_addrexcptn | |
1188 | ||
1da177e4 | 1189 | /*============================================================================= |
c0e7f7ee | 1190 | * FIQ "NMI" handler |
1da177e4 | 1191 | *----------------------------------------------------------------------------- |
c0e7f7ee DT |
1192 | * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 |
1193 | * systems. | |
1da177e4 | 1194 | */ |
c0e7f7ee DT |
1195 | vector_stub fiq, FIQ_MODE, 4 |
1196 | ||
1197 | .long __fiq_usr @ 0 (USR_26 / USR_32) | |
1198 | .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) | |
1199 | .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) | |
1200 | .long __fiq_svc @ 3 (SVC_26 / SVC_32) | |
1201 | .long __fiq_svc @ 4 | |
1202 | .long __fiq_svc @ 5 | |
1203 | .long __fiq_svc @ 6 | |
1204 | .long __fiq_abt @ 7 | |
1205 | .long __fiq_svc @ 8 | |
1206 | .long __fiq_svc @ 9 | |
1207 | .long __fiq_svc @ a | |
1208 | .long __fiq_svc @ b | |
1209 | .long __fiq_svc @ c | |
1210 | .long __fiq_svc @ d | |
1211 | .long __fiq_svc @ e | |
1212 | .long __fiq_svc @ f | |
1da177e4 | 1213 | |
e39e3f3e RK |
1214 | .globl vector_fiq_offset |
1215 | .equ vector_fiq_offset, vector_fiq | |
1216 | ||
b9b32bf7 | 1217 | .section .vectors, "ax", %progbits |
7933523d | 1218 | __vectors_start: |
b9b32bf7 RK |
1219 | W(b) vector_rst |
1220 | W(b) vector_und | |
1221 | W(ldr) pc, __vectors_start + 0x1000 | |
1222 | W(b) vector_pabt | |
1223 | W(b) vector_dabt | |
1224 | W(b) vector_addrexcptn | |
1225 | W(b) vector_irq | |
1226 | W(b) vector_fiq | |
1da177e4 LT |
1227 | |
1228 | .data | |
1229 | ||
1da177e4 | 1230 | .globl cr_alignment |
1da177e4 LT |
1231 | cr_alignment: |
1232 | .space 4 | |
52108641 | 1233 | |
1234 | #ifdef CONFIG_MULTI_IRQ_HANDLER | |
1235 | .globl handle_arch_irq | |
1236 | handle_arch_irq: | |
1237 | .space 4 | |
1238 | #endif |