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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
6f6f6a70 | 18 | #include <asm/assembler.h> |
f09b9979 | 19 | #include <asm/memory.h> |
753790e7 RK |
20 | #include <asm/glue-df.h> |
21 | #include <asm/glue-pf.h> | |
1da177e4 | 22 | #include <asm/vfpmacros.h> |
243c8654 | 23 | #ifndef CONFIG_MULTI_IRQ_HANDLER |
a09e64fb | 24 | #include <mach/entry-macro.S> |
243c8654 | 25 | #endif |
d6551e88 | 26 | #include <asm/thread_notify.h> |
c4c5716e | 27 | #include <asm/unwind.h> |
cc20d429 | 28 | #include <asm/unistd.h> |
f159f4ed | 29 | #include <asm/tls.h> |
9f97da78 | 30 | #include <asm/system_info.h> |
1da177e4 LT |
31 | |
32 | #include "entry-header.S" | |
cd544ce7 | 33 | #include <asm/entry-macro-multi.S> |
1da177e4 | 34 | |
187a51ad | 35 | /* |
d9600c99 | 36 | * Interrupt handling. |
187a51ad RK |
37 | */ |
38 | .macro irq_handler | |
52108641 | 39 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
d9600c99 | 40 | ldr r1, =handle_arch_irq |
52108641 | 41 | mov r0, sp |
52108641 | 42 | adr lr, BSYM(9997f) |
abeb24ae MZ |
43 | ldr pc, [r1] |
44 | #else | |
cd544ce7 | 45 | arch_irq_handler_default |
abeb24ae | 46 | #endif |
f00ec48f | 47 | 9997: |
187a51ad RK |
48 | .endm |
49 | ||
ac8b9c1c | 50 | .macro pabt_helper |
8dfe7ac9 | 51 | @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 |
ac8b9c1c | 52 | #ifdef MULTI_PABORT |
0402bece | 53 | ldr ip, .LCprocfns |
ac8b9c1c | 54 | mov lr, pc |
0402bece | 55 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
ac8b9c1c RK |
56 | #else |
57 | bl CPU_PABORT_HANDLER | |
58 | #endif | |
59 | .endm | |
60 | ||
61 | .macro dabt_helper | |
62 | ||
63 | @ | |
64 | @ Call the processor-specific abort handler: | |
65 | @ | |
da740472 | 66 | @ r2 - pt_regs |
3e287bec RK |
67 | @ r4 - aborted context pc |
68 | @ r5 - aborted context psr | |
ac8b9c1c RK |
69 | @ |
70 | @ The abort handler must return the aborted address in r0, and | |
71 | @ the fault status register in r1. r9 must be preserved. | |
72 | @ | |
73 | #ifdef MULTI_DABORT | |
0402bece | 74 | ldr ip, .LCprocfns |
ac8b9c1c | 75 | mov lr, pc |
0402bece | 76 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
ac8b9c1c RK |
77 | #else |
78 | bl CPU_DABORT_HANDLER | |
79 | #endif | |
80 | .endm | |
81 | ||
785d3cd2 NP |
82 | #ifdef CONFIG_KPROBES |
83 | .section .kprobes.text,"ax",%progbits | |
84 | #else | |
85 | .text | |
86 | #endif | |
87 | ||
1da177e4 LT |
88 | /* |
89 | * Invalid mode handlers | |
90 | */ | |
ccea7a19 RK |
91 | .macro inv_entry, reason |
92 | sub sp, sp, #S_FRAME_SIZE | |
b86040a5 CM |
93 | ARM( stmib sp, {r1 - lr} ) |
94 | THUMB( stmia sp, {r0 - r12} ) | |
95 | THUMB( str sp, [sp, #S_SP] ) | |
96 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
97 | mov r1, #\reason |
98 | .endm | |
99 | ||
100 | __pabt_invalid: | |
ccea7a19 RK |
101 | inv_entry BAD_PREFETCH |
102 | b common_invalid | |
93ed3970 | 103 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
104 | |
105 | __dabt_invalid: | |
ccea7a19 RK |
106 | inv_entry BAD_DATA |
107 | b common_invalid | |
93ed3970 | 108 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
109 | |
110 | __irq_invalid: | |
ccea7a19 RK |
111 | inv_entry BAD_IRQ |
112 | b common_invalid | |
93ed3970 | 113 | ENDPROC(__irq_invalid) |
1da177e4 LT |
114 | |
115 | __und_invalid: | |
ccea7a19 RK |
116 | inv_entry BAD_UNDEFINSTR |
117 | ||
118 | @ | |
119 | @ XXX fall through to common_invalid | |
120 | @ | |
121 | ||
122 | @ | |
123 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
124 | @ | |
125 | common_invalid: | |
126 | zero_fp | |
127 | ||
128 | ldmia r0, {r4 - r6} | |
129 | add r0, sp, #S_PC @ here for interlock avoidance | |
130 | mov r7, #-1 @ "" "" "" "" | |
131 | str r4, [sp] @ save preserved r0 | |
132 | stmia r0, {r5 - r7} @ lr_<exception>, | |
133 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 134 | |
1da177e4 | 135 | mov r0, sp |
1da177e4 | 136 | b bad_mode |
93ed3970 | 137 | ENDPROC(__und_invalid) |
1da177e4 LT |
138 | |
139 | /* | |
140 | * SVC mode handlers | |
141 | */ | |
2dede2d8 NP |
142 | |
143 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
144 | #define SPFIX(code...) code | |
145 | #else | |
146 | #define SPFIX(code...) | |
147 | #endif | |
148 | ||
d30a0c8b | 149 | .macro svc_entry, stack_hole=0 |
c4c5716e CM |
150 | UNWIND(.fnstart ) |
151 | UNWIND(.save {r0 - pc} ) | |
b86040a5 CM |
152 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
153 | #ifdef CONFIG_THUMB2_KERNEL | |
154 | SPFIX( str r0, [sp] ) @ temporarily saved | |
155 | SPFIX( mov r0, sp ) | |
156 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
157 | SPFIX( ldr r0, [sp] ) @ restored | |
158 | #else | |
2dede2d8 | 159 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
160 | #endif |
161 | SPFIX( subeq sp, sp, #4 ) | |
162 | stmia sp, {r1 - r12} | |
ccea7a19 | 163 | |
b059bdc3 RK |
164 | ldmia r0, {r3 - r5} |
165 | add r7, sp, #S_SP - 4 @ here for interlock avoidance | |
166 | mov r6, #-1 @ "" "" "" "" | |
167 | add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) | |
168 | SPFIX( addeq r2, r2, #4 ) | |
169 | str r3, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
170 | @ from the exception stack |
171 | ||
b059bdc3 | 172 | mov r3, lr |
1da177e4 LT |
173 | |
174 | @ | |
175 | @ We are now ready to fill in the remaining blanks on the stack: | |
176 | @ | |
b059bdc3 RK |
177 | @ r2 - sp_svc |
178 | @ r3 - lr_svc | |
179 | @ r4 - lr_<exception>, already fixed up for correct return/restart | |
180 | @ r5 - spsr_<exception> | |
181 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 | 182 | @ |
b059bdc3 | 183 | stmia r7, {r2 - r6} |
1da177e4 | 184 | |
02fe2845 RK |
185 | #ifdef CONFIG_TRACE_IRQFLAGS |
186 | bl trace_hardirqs_off | |
187 | #endif | |
f2741b78 | 188 | .endm |
1da177e4 | 189 | |
f2741b78 RK |
190 | .align 5 |
191 | __dabt_svc: | |
192 | svc_entry | |
1da177e4 | 193 | mov r2, sp |
da740472 | 194 | dabt_helper |
b059bdc3 | 195 | svc_exit r5 @ return from exception |
c4c5716e | 196 | UNWIND(.fnend ) |
93ed3970 | 197 | ENDPROC(__dabt_svc) |
1da177e4 LT |
198 | |
199 | .align 5 | |
200 | __irq_svc: | |
ccea7a19 | 201 | svc_entry |
187a51ad | 202 | irq_handler |
1613cc11 | 203 | |
1da177e4 | 204 | #ifdef CONFIG_PREEMPT |
1613cc11 RK |
205 | get_thread_info tsk |
206 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
706fdd9f | 207 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
208 | teq r8, #0 @ if preempt count != 0 |
209 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
210 | tst r0, #_TIF_NEED_RESCHED |
211 | blne svc_preempt | |
1da177e4 | 212 | #endif |
30891c90 | 213 | |
9b56febe | 214 | svc_exit r5, irq = 1 @ return from exception |
c4c5716e | 215 | UNWIND(.fnend ) |
93ed3970 | 216 | ENDPROC(__irq_svc) |
1da177e4 LT |
217 | |
218 | .ltorg | |
219 | ||
220 | #ifdef CONFIG_PREEMPT | |
221 | svc_preempt: | |
28fab1a2 | 222 | mov r8, lr |
1da177e4 | 223 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 224 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 225 | tst r0, #_TIF_NEED_RESCHED |
28fab1a2 | 226 | moveq pc, r8 @ go again |
1da177e4 LT |
227 | b 1b |
228 | #endif | |
229 | ||
15ac49b6 RK |
230 | __und_fault: |
231 | @ Correct the PC such that it is pointing at the instruction | |
232 | @ which caused the fault. If the faulting instruction was ARM | |
233 | @ the PC will be pointing at the next instruction, and have to | |
234 | @ subtract 4. Otherwise, it is Thumb, and the PC will be | |
235 | @ pointing at the second half of the Thumb instruction. We | |
236 | @ have to subtract 2. | |
237 | ldr r2, [r0, #S_PC] | |
238 | sub r2, r2, r1 | |
239 | str r2, [r0, #S_PC] | |
240 | b do_undefinstr | |
241 | ENDPROC(__und_fault) | |
242 | ||
1da177e4 LT |
243 | .align 5 |
244 | __und_svc: | |
d30a0c8b NP |
245 | #ifdef CONFIG_KPROBES |
246 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
247 | @ it obviously needs free stack space which then will belong to | |
248 | @ the saved context. | |
249 | svc_entry 64 | |
250 | #else | |
ccea7a19 | 251 | svc_entry |
d30a0c8b | 252 | #endif |
1da177e4 LT |
253 | @ |
254 | @ call emulation code, which returns using r9 if it has emulated | |
255 | @ the instruction, or the more conventional lr if we are to treat | |
256 | @ this as a real undefined instruction | |
257 | @ | |
258 | @ r0 - instruction | |
259 | @ | |
15ac49b6 | 260 | #ifndef CONFIG_THUMB2_KERNEL |
b059bdc3 | 261 | ldr r0, [r4, #-4] |
83e686ea | 262 | #else |
15ac49b6 | 263 | mov r1, #2 |
b059bdc3 | 264 | ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 |
85519189 | 265 | cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 |
15ac49b6 RK |
266 | blo __und_svc_fault |
267 | ldrh r9, [r4] @ bottom 16 bits | |
268 | add r4, r4, #2 | |
269 | str r4, [sp, #S_PC] | |
270 | orr r0, r9, r0, lsl #16 | |
83e686ea | 271 | #endif |
15ac49b6 | 272 | adr r9, BSYM(__und_svc_finish) |
b059bdc3 | 273 | mov r2, r4 |
1da177e4 LT |
274 | bl call_fpe |
275 | ||
15ac49b6 RK |
276 | mov r1, #4 @ PC correction to apply |
277 | __und_svc_fault: | |
1da177e4 | 278 | mov r0, sp @ struct pt_regs *regs |
15ac49b6 | 279 | bl __und_fault |
1da177e4 | 280 | |
15ac49b6 | 281 | __und_svc_finish: |
b059bdc3 RK |
282 | ldr r5, [sp, #S_PSR] @ Get SVC cpsr |
283 | svc_exit r5 @ return from exception | |
c4c5716e | 284 | UNWIND(.fnend ) |
93ed3970 | 285 | ENDPROC(__und_svc) |
1da177e4 LT |
286 | |
287 | .align 5 | |
288 | __pabt_svc: | |
ccea7a19 | 289 | svc_entry |
4fb28474 | 290 | mov r2, sp @ regs |
8dfe7ac9 | 291 | pabt_helper |
b059bdc3 | 292 | svc_exit r5 @ return from exception |
c4c5716e | 293 | UNWIND(.fnend ) |
93ed3970 | 294 | ENDPROC(__pabt_svc) |
1da177e4 LT |
295 | |
296 | .align 5 | |
49f680ea RK |
297 | .LCcralign: |
298 | .word cr_alignment | |
48d7927b | 299 | #ifdef MULTI_DABORT |
1da177e4 LT |
300 | .LCprocfns: |
301 | .word processor | |
302 | #endif | |
303 | .LCfp: | |
304 | .word fp_enter | |
1da177e4 LT |
305 | |
306 | /* | |
307 | * User mode handlers | |
2dede2d8 NP |
308 | * |
309 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 310 | */ |
2dede2d8 NP |
311 | |
312 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
313 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
314 | #endif | |
315 | ||
ccea7a19 | 316 | .macro usr_entry |
c4c5716e CM |
317 | UNWIND(.fnstart ) |
318 | UNWIND(.cantunwind ) @ don't unwind the user space | |
ccea7a19 | 319 | sub sp, sp, #S_FRAME_SIZE |
b86040a5 CM |
320 | ARM( stmib sp, {r1 - r12} ) |
321 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 | 322 | |
b059bdc3 | 323 | ldmia r0, {r3 - r5} |
ccea7a19 | 324 | add r0, sp, #S_PC @ here for interlock avoidance |
b059bdc3 | 325 | mov r6, #-1 @ "" "" "" "" |
ccea7a19 | 326 | |
b059bdc3 | 327 | str r3, [sp] @ save the "real" r0 copied |
ccea7a19 | 328 | @ from the exception stack |
1da177e4 LT |
329 | |
330 | @ | |
331 | @ We are now ready to fill in the remaining blanks on the stack: | |
332 | @ | |
b059bdc3 RK |
333 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
334 | @ r5 - spsr_<exception> | |
335 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 LT |
336 | @ |
337 | @ Also, separately save sp_usr and lr_usr | |
338 | @ | |
b059bdc3 | 339 | stmia r0, {r4 - r6} |
b86040a5 CM |
340 | ARM( stmdb r0, {sp, lr}^ ) |
341 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 LT |
342 | |
343 | @ | |
344 | @ Enable the alignment trap while in kernel mode | |
345 | @ | |
49f680ea | 346 | alignment_trap r0 |
1da177e4 LT |
347 | |
348 | @ | |
349 | @ Clear FP to mark the first stack frame | |
350 | @ | |
351 | zero_fp | |
f2741b78 RK |
352 | |
353 | #ifdef CONFIG_IRQSOFF_TRACER | |
354 | bl trace_hardirqs_off | |
355 | #endif | |
b0088480 | 356 | ct_user_exit save = 0 |
1da177e4 LT |
357 | .endm |
358 | ||
b49c0f24 | 359 | .macro kuser_cmpxchg_check |
40fb79c8 | 360 | #if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
b49c0f24 NP |
361 | #ifndef CONFIG_MMU |
362 | #warning "NPTL on non MMU needs fixing" | |
363 | #else | |
364 | @ Make sure our user space atomic helper is restarted | |
365 | @ if it was interrupted in a critical region. Here we | |
366 | @ perform a quick test inline since it should be false | |
367 | @ 99.9999% of the time. The rest is done out of line. | |
b059bdc3 | 368 | cmp r4, #TASK_SIZE |
40fb79c8 | 369 | blhs kuser_cmpxchg64_fixup |
b49c0f24 NP |
370 | #endif |
371 | #endif | |
372 | .endm | |
373 | ||
1da177e4 LT |
374 | .align 5 |
375 | __dabt_usr: | |
ccea7a19 | 376 | usr_entry |
b49c0f24 | 377 | kuser_cmpxchg_check |
1da177e4 | 378 | mov r2, sp |
da740472 RK |
379 | dabt_helper |
380 | b ret_from_exception | |
c4c5716e | 381 | UNWIND(.fnend ) |
93ed3970 | 382 | ENDPROC(__dabt_usr) |
1da177e4 LT |
383 | |
384 | .align 5 | |
385 | __irq_usr: | |
ccea7a19 | 386 | usr_entry |
bc089602 | 387 | kuser_cmpxchg_check |
187a51ad | 388 | irq_handler |
1613cc11 | 389 | get_thread_info tsk |
1da177e4 | 390 | mov why, #0 |
9fc2552a | 391 | b ret_to_user_from_irq |
c4c5716e | 392 | UNWIND(.fnend ) |
93ed3970 | 393 | ENDPROC(__irq_usr) |
1da177e4 LT |
394 | |
395 | .ltorg | |
396 | ||
397 | .align 5 | |
398 | __und_usr: | |
ccea7a19 | 399 | usr_entry |
bc089602 | 400 | |
b059bdc3 RK |
401 | mov r2, r4 |
402 | mov r3, r5 | |
1da177e4 | 403 | |
15ac49b6 RK |
404 | @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the |
405 | @ faulting instruction depending on Thumb mode. | |
406 | @ r3 = regs->ARM_cpsr | |
1da177e4 | 407 | @ |
15ac49b6 RK |
408 | @ The emulation code returns using r9 if it has emulated the |
409 | @ instruction, or the more conventional lr if we are to treat | |
410 | @ this as a real undefined instruction | |
1da177e4 | 411 | @ |
b86040a5 | 412 | adr r9, BSYM(ret_from_exception) |
15ac49b6 | 413 | |
cb170a45 | 414 | tst r3, #PSR_T_BIT @ Thumb mode? |
15ac49b6 RK |
415 | bne __und_usr_thumb |
416 | sub r4, r2, #4 @ ARM instr at LR - 4 | |
417 | 1: ldrt r0, [r4] | |
26584853 | 418 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
15ac49b6 | 419 | rev r0, r0 @ little endian instruction |
26584853 | 420 | #endif |
15ac49b6 RK |
421 | @ r0 = 32-bit ARM instruction which caused the exception |
422 | @ r2 = PC value for the following instruction (:= regs->ARM_pc) | |
423 | @ r4 = PC value for the faulting instruction | |
424 | @ lr = 32-bit undefined instruction function | |
425 | adr lr, BSYM(__und_usr_fault_32) | |
426 | b call_fpe | |
427 | ||
428 | __und_usr_thumb: | |
cb170a45 | 429 | @ Thumb instruction |
15ac49b6 | 430 | sub r4, r2, #2 @ First half of thumb instr at LR - 2 |
ef4c5368 DM |
431 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
432 | /* | |
433 | * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms | |
434 | * can never be supported in a single kernel, this code is not applicable at | |
435 | * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be | |
436 | * made about .arch directives. | |
437 | */ | |
438 | #if __LINUX_ARM_ARCH__ < 7 | |
439 | /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ | |
440 | #define NEED_CPU_ARCHITECTURE | |
441 | ldr r5, .LCcpu_architecture | |
442 | ldr r5, [r5] | |
443 | cmp r5, #CPU_ARCH_ARMv7 | |
15ac49b6 | 444 | blo __und_usr_fault_16 @ 16bit undefined instruction |
ef4c5368 DM |
445 | /* |
446 | * The following code won't get run unless the running CPU really is v7, so | |
447 | * coding round the lack of ldrht on older arches is pointless. Temporarily | |
448 | * override the assembler target arch with the minimum required instead: | |
449 | */ | |
450 | .arch armv6t2 | |
451 | #endif | |
15ac49b6 | 452 | 2: ldrht r5, [r4] |
85519189 | 453 | cmp r5, #0xe800 @ 32bit instruction if xx != 0 |
15ac49b6 RK |
454 | blo __und_usr_fault_16 @ 16bit undefined instruction |
455 | 3: ldrht r0, [r2] | |
cb170a45 | 456 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 |
15ac49b6 | 457 | str r2, [sp, #S_PC] @ it's a 2x16bit instr, update |
cb170a45 | 458 | orr r0, r0, r5, lsl #16 |
15ac49b6 RK |
459 | adr lr, BSYM(__und_usr_fault_32) |
460 | @ r0 = the two 16-bit Thumb instructions which caused the exception | |
461 | @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) | |
462 | @ r4 = PC value for the first 16-bit Thumb instruction | |
463 | @ lr = 32bit undefined instruction function | |
ef4c5368 DM |
464 | |
465 | #if __LINUX_ARM_ARCH__ < 7 | |
466 | /* If the target arch was overridden, change it back: */ | |
467 | #ifdef CONFIG_CPU_32v6K | |
468 | .arch armv6k | |
cb170a45 | 469 | #else |
ef4c5368 DM |
470 | .arch armv6 |
471 | #endif | |
472 | #endif /* __LINUX_ARM_ARCH__ < 7 */ | |
473 | #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ | |
15ac49b6 | 474 | b __und_usr_fault_16 |
cb170a45 | 475 | #endif |
15ac49b6 | 476 | UNWIND(.fnend) |
93ed3970 | 477 | ENDPROC(__und_usr) |
cb170a45 | 478 | |
1da177e4 | 479 | /* |
15ac49b6 | 480 | * The out of line fixup for the ldrt instructions above. |
1da177e4 | 481 | */ |
4260415f | 482 | .pushsection .fixup, "ax" |
667d1b48 | 483 | .align 2 |
cb170a45 | 484 | 4: mov pc, r9 |
4260415f RK |
485 | .popsection |
486 | .pushsection __ex_table,"a" | |
cb170a45 | 487 | .long 1b, 4b |
c89cefed | 488 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
cb170a45 PB |
489 | .long 2b, 4b |
490 | .long 3b, 4b | |
491 | #endif | |
4260415f | 492 | .popsection |
1da177e4 LT |
493 | |
494 | /* | |
495 | * Check whether the instruction is a co-processor instruction. | |
496 | * If yes, we need to call the relevant co-processor handler. | |
497 | * | |
498 | * Note that we don't do a full check here for the co-processor | |
499 | * instructions; all instructions with bit 27 set are well | |
500 | * defined. The only instructions that should fault are the | |
501 | * co-processor instructions. However, we have to watch out | |
502 | * for the ARM6/ARM7 SWI bug. | |
503 | * | |
b5872db4 CM |
504 | * NEON is a special case that has to be handled here. Not all |
505 | * NEON instructions are co-processor instructions, so we have | |
506 | * to make a special case of checking for them. Plus, there's | |
507 | * five groups of them, so we have a table of mask/opcode pairs | |
508 | * to check against, and if any match then we branch off into the | |
509 | * NEON handler code. | |
510 | * | |
1da177e4 | 511 | * Emulators may wish to make use of the following registers: |
15ac49b6 RK |
512 | * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) |
513 | * r2 = PC value to resume execution after successful emulation | |
db6ccbb6 | 514 | * r9 = normal "successful" return address |
15ac49b6 | 515 | * r10 = this threads thread_info structure |
db6ccbb6 | 516 | * lr = unrecognised instruction return address |
15ac49b6 | 517 | * IRQs disabled, FIQs enabled. |
1da177e4 | 518 | */ |
cb170a45 PB |
519 | @ |
520 | @ Fall-through from Thumb-2 __und_usr | |
521 | @ | |
522 | #ifdef CONFIG_NEON | |
d3f79584 | 523 | get_thread_info r10 @ get current thread |
cb170a45 PB |
524 | adr r6, .LCneon_thumb_opcodes |
525 | b 2f | |
526 | #endif | |
1da177e4 | 527 | call_fpe: |
d3f79584 | 528 | get_thread_info r10 @ get current thread |
b5872db4 | 529 | #ifdef CONFIG_NEON |
cb170a45 | 530 | adr r6, .LCneon_arm_opcodes |
d3f79584 | 531 | 2: ldr r5, [r6], #4 @ mask value |
b5872db4 | 532 | ldr r7, [r6], #4 @ opcode bits matching in mask |
d3f79584 RK |
533 | cmp r5, #0 @ end mask? |
534 | beq 1f | |
535 | and r8, r0, r5 | |
b5872db4 CM |
536 | cmp r8, r7 @ NEON instruction? |
537 | bne 2b | |
b5872db4 CM |
538 | mov r7, #1 |
539 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
540 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
541 | b do_vfp @ let VFP handler handle this | |
542 | 1: | |
543 | #endif | |
1da177e4 | 544 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 545 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
1da177e4 | 546 | moveq pc, lr |
1da177e4 | 547 | and r8, r0, #0x00000f00 @ mask out CP number |
b86040a5 | 548 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
549 | mov r7, #1 |
550 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
551 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
552 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
553 | #ifdef CONFIG_IWMMXT |
554 | @ Test if we need to give access to iWMMXt coprocessors | |
555 | ldr r5, [r10, #TI_FLAGS] | |
556 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
557 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
558 | bcs iwmmxt_task_enable | |
559 | #endif | |
b86040a5 CM |
560 | ARM( add pc, pc, r8, lsr #6 ) |
561 | THUMB( lsl r8, r8, #2 ) | |
562 | THUMB( add pc, r8 ) | |
563 | nop | |
564 | ||
a771fe6e | 565 | movw_pc lr @ CP#0 |
b86040a5 CM |
566 | W(b) do_fpe @ CP#1 (FPE) |
567 | W(b) do_fpe @ CP#2 (FPE) | |
a771fe6e | 568 | movw_pc lr @ CP#3 |
c17fad11 LB |
569 | #ifdef CONFIG_CRUNCH |
570 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
571 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
572 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
573 | #else | |
a771fe6e CM |
574 | movw_pc lr @ CP#4 |
575 | movw_pc lr @ CP#5 | |
576 | movw_pc lr @ CP#6 | |
c17fad11 | 577 | #endif |
a771fe6e CM |
578 | movw_pc lr @ CP#7 |
579 | movw_pc lr @ CP#8 | |
580 | movw_pc lr @ CP#9 | |
1da177e4 | 581 | #ifdef CONFIG_VFP |
b86040a5 CM |
582 | W(b) do_vfp @ CP#10 (VFP) |
583 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 584 | #else |
a771fe6e CM |
585 | movw_pc lr @ CP#10 (VFP) |
586 | movw_pc lr @ CP#11 (VFP) | |
1da177e4 | 587 | #endif |
a771fe6e CM |
588 | movw_pc lr @ CP#12 |
589 | movw_pc lr @ CP#13 | |
590 | movw_pc lr @ CP#14 (Debug) | |
591 | movw_pc lr @ CP#15 (Control) | |
1da177e4 | 592 | |
ef4c5368 DM |
593 | #ifdef NEED_CPU_ARCHITECTURE |
594 | .align 2 | |
595 | .LCcpu_architecture: | |
596 | .word __cpu_architecture | |
597 | #endif | |
598 | ||
b5872db4 CM |
599 | #ifdef CONFIG_NEON |
600 | .align 6 | |
601 | ||
cb170a45 | 602 | .LCneon_arm_opcodes: |
b5872db4 CM |
603 | .word 0xfe000000 @ mask |
604 | .word 0xf2000000 @ opcode | |
605 | ||
606 | .word 0xff100000 @ mask | |
607 | .word 0xf4000000 @ opcode | |
608 | ||
cb170a45 PB |
609 | .word 0x00000000 @ mask |
610 | .word 0x00000000 @ opcode | |
611 | ||
612 | .LCneon_thumb_opcodes: | |
613 | .word 0xef000000 @ mask | |
614 | .word 0xef000000 @ opcode | |
615 | ||
616 | .word 0xff100000 @ mask | |
617 | .word 0xf9000000 @ opcode | |
618 | ||
b5872db4 CM |
619 | .word 0x00000000 @ mask |
620 | .word 0x00000000 @ opcode | |
621 | #endif | |
622 | ||
1da177e4 | 623 | do_fpe: |
5d25ac03 | 624 | enable_irq |
1da177e4 LT |
625 | ldr r4, .LCfp |
626 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
627 | ldr pc, [r4] @ Call FP module USR entry point | |
628 | ||
629 | /* | |
630 | * The FP module is called with these registers set: | |
631 | * r0 = instruction | |
632 | * r2 = PC+4 | |
633 | * r9 = normal "successful" return address | |
634 | * r10 = FP workspace | |
635 | * lr = unrecognised FP instruction return address | |
636 | */ | |
637 | ||
124efc27 | 638 | .pushsection .data |
1da177e4 | 639 | ENTRY(fp_enter) |
db6ccbb6 | 640 | .word no_fp |
124efc27 | 641 | .popsection |
1da177e4 | 642 | |
83e686ea CM |
643 | ENTRY(no_fp) |
644 | mov pc, lr | |
645 | ENDPROC(no_fp) | |
db6ccbb6 | 646 | |
15ac49b6 RK |
647 | __und_usr_fault_32: |
648 | mov r1, #4 | |
649 | b 1f | |
650 | __und_usr_fault_16: | |
651 | mov r1, #2 | |
652 | 1: enable_irq | |
1da177e4 | 653 | mov r0, sp |
b86040a5 | 654 | adr lr, BSYM(ret_from_exception) |
15ac49b6 RK |
655 | b __und_fault |
656 | ENDPROC(__und_usr_fault_32) | |
657 | ENDPROC(__und_usr_fault_16) | |
1da177e4 LT |
658 | |
659 | .align 5 | |
660 | __pabt_usr: | |
ccea7a19 | 661 | usr_entry |
4fb28474 | 662 | mov r2, sp @ regs |
8dfe7ac9 | 663 | pabt_helper |
c4c5716e | 664 | UNWIND(.fnend ) |
1da177e4 LT |
665 | /* fall through */ |
666 | /* | |
667 | * This is the return code to user mode for abort handlers | |
668 | */ | |
669 | ENTRY(ret_from_exception) | |
c4c5716e CM |
670 | UNWIND(.fnstart ) |
671 | UNWIND(.cantunwind ) | |
1da177e4 LT |
672 | get_thread_info tsk |
673 | mov why, #0 | |
674 | b ret_to_user | |
c4c5716e | 675 | UNWIND(.fnend ) |
93ed3970 CM |
676 | ENDPROC(__pabt_usr) |
677 | ENDPROC(ret_from_exception) | |
1da177e4 LT |
678 | |
679 | /* | |
680 | * Register switch for ARMv3 and ARMv4 processors | |
681 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
682 | * previous and next are guaranteed not to be the same. | |
683 | */ | |
684 | ENTRY(__switch_to) | |
c4c5716e CM |
685 | UNWIND(.fnstart ) |
686 | UNWIND(.cantunwind ) | |
1da177e4 | 687 | add ip, r1, #TI_CPU_SAVE |
b86040a5 CM |
688 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
689 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
690 | THUMB( str sp, [ip], #4 ) | |
691 | THUMB( str lr, [ip], #4 ) | |
a4780ade AH |
692 | ldr r4, [r2, #TI_TP_VALUE] |
693 | ldr r5, [r2, #TI_TP_VALUE + 4] | |
247055aa | 694 | #ifdef CONFIG_CPU_USE_DOMAINS |
d6551e88 | 695 | ldr r6, [r2, #TI_CPU_DOMAIN] |
afeb90ca | 696 | #endif |
a4780ade | 697 | switch_tls r1, r4, r5, r3, r7 |
df0698be NP |
698 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
699 | ldr r7, [r2, #TI_TASK] | |
700 | ldr r8, =__stack_chk_guard | |
701 | ldr r7, [r7, #TSK_STACK_CANARY] | |
702 | #endif | |
247055aa | 703 | #ifdef CONFIG_CPU_USE_DOMAINS |
1da177e4 | 704 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 705 | #endif |
d6551e88 RK |
706 | mov r5, r0 |
707 | add r4, r2, #TI_CPU_SAVE | |
708 | ldr r0, =thread_notify_head | |
709 | mov r1, #THREAD_NOTIFY_SWITCH | |
710 | bl atomic_notifier_call_chain | |
df0698be NP |
711 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
712 | str r7, [r8] | |
713 | #endif | |
b86040a5 | 714 | THUMB( mov ip, r4 ) |
d6551e88 | 715 | mov r0, r5 |
b86040a5 CM |
716 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
717 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
718 | THUMB( ldr sp, [ip], #4 ) | |
719 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 720 | UNWIND(.fnend ) |
93ed3970 | 721 | ENDPROC(__switch_to) |
1da177e4 LT |
722 | |
723 | __INIT | |
2d2669b6 NP |
724 | |
725 | /* | |
726 | * User helpers. | |
727 | * | |
2d2669b6 NP |
728 | * Each segment is 32-byte aligned and will be moved to the top of the high |
729 | * vector page. New segments (if ever needed) must be added in front of | |
730 | * existing ones. This mechanism should be used only for things that are | |
731 | * really small and justified, and not be abused freely. | |
732 | * | |
37b83046 | 733 | * See Documentation/arm/kernel_user_helpers.txt for formal definitions. |
2d2669b6 | 734 | */ |
b86040a5 | 735 | THUMB( .arm ) |
2d2669b6 | 736 | |
ba9b5d76 NP |
737 | .macro usr_ret, reg |
738 | #ifdef CONFIG_ARM_THUMB | |
739 | bx \reg | |
740 | #else | |
741 | mov pc, \reg | |
742 | #endif | |
743 | .endm | |
744 | ||
2d2669b6 NP |
745 | .align 5 |
746 | .globl __kuser_helper_start | |
747 | __kuser_helper_start: | |
748 | ||
7c612bfd | 749 | /* |
40fb79c8 NP |
750 | * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular |
751 | * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. | |
7c612bfd NP |
752 | */ |
753 | ||
40fb79c8 NP |
754 | __kuser_cmpxchg64: @ 0xffff0f60 |
755 | ||
756 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
757 | ||
758 | /* | |
759 | * Poor you. No fast solution possible... | |
760 | * The kernel itself must perform the operation. | |
761 | * A special ghost syscall is used for that (see traps.c). | |
762 | */ | |
763 | stmfd sp!, {r7, lr} | |
764 | ldr r7, 1f @ it's 20 bits | |
765 | swi __ARM_NR_cmpxchg64 | |
766 | ldmfd sp!, {r7, pc} | |
767 | 1: .word __ARM_NR_cmpxchg64 | |
768 | ||
769 | #elif defined(CONFIG_CPU_32v6K) | |
770 | ||
771 | stmfd sp!, {r4, r5, r6, r7} | |
772 | ldrd r4, r5, [r0] @ load old val | |
773 | ldrd r6, r7, [r1] @ load new val | |
774 | smp_dmb arm | |
775 | 1: ldrexd r0, r1, [r2] @ load current val | |
776 | eors r3, r0, r4 @ compare with oldval (1) | |
777 | eoreqs r3, r1, r5 @ compare with oldval (2) | |
778 | strexdeq r3, r6, r7, [r2] @ store newval if eq | |
779 | teqeq r3, #1 @ success? | |
780 | beq 1b @ if no then retry | |
ed3768a8 | 781 | smp_dmb arm |
40fb79c8 NP |
782 | rsbs r0, r3, #0 @ set returned val and C flag |
783 | ldmfd sp!, {r4, r5, r6, r7} | |
5a97d0ae | 784 | usr_ret lr |
40fb79c8 NP |
785 | |
786 | #elif !defined(CONFIG_SMP) | |
787 | ||
788 | #ifdef CONFIG_MMU | |
789 | ||
790 | /* | |
791 | * The only thing that can break atomicity in this cmpxchg64 | |
792 | * implementation is either an IRQ or a data abort exception | |
793 | * causing another process/thread to be scheduled in the middle of | |
794 | * the critical sequence. The same strategy as for cmpxchg is used. | |
795 | */ | |
796 | stmfd sp!, {r4, r5, r6, lr} | |
797 | ldmia r0, {r4, r5} @ load old val | |
798 | ldmia r1, {r6, lr} @ load new val | |
799 | 1: ldmia r2, {r0, r1} @ load current val | |
800 | eors r3, r0, r4 @ compare with oldval (1) | |
801 | eoreqs r3, r1, r5 @ compare with oldval (2) | |
802 | 2: stmeqia r2, {r6, lr} @ store newval if eq | |
803 | rsbs r0, r3, #0 @ set return val and C flag | |
804 | ldmfd sp!, {r4, r5, r6, pc} | |
805 | ||
806 | .text | |
807 | kuser_cmpxchg64_fixup: | |
808 | @ Called from kuser_cmpxchg_fixup. | |
3ad55155 | 809 | @ r4 = address of interrupted insn (must be preserved). |
40fb79c8 NP |
810 | @ sp = saved regs. r7 and r8 are clobbered. |
811 | @ 1b = first critical insn, 2b = last critical insn. | |
3ad55155 | 812 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
40fb79c8 NP |
813 | mov r7, #0xffff0fff |
814 | sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) | |
3ad55155 | 815 | subs r8, r4, r7 |
40fb79c8 NP |
816 | rsbcss r8, r8, #(2b - 1b) |
817 | strcs r7, [sp, #S_PC] | |
818 | #if __LINUX_ARM_ARCH__ < 6 | |
819 | bcc kuser_cmpxchg32_fixup | |
820 | #endif | |
821 | mov pc, lr | |
822 | .previous | |
823 | ||
824 | #else | |
825 | #warning "NPTL on non MMU needs fixing" | |
826 | mov r0, #-1 | |
827 | adds r0, r0, #0 | |
ba9b5d76 | 828 | usr_ret lr |
40fb79c8 NP |
829 | #endif |
830 | ||
831 | #else | |
832 | #error "incoherent kernel configuration" | |
833 | #endif | |
834 | ||
835 | /* pad to next slot */ | |
836 | .rept (16 - (. - __kuser_cmpxchg64)/4) | |
837 | .word 0 | |
838 | .endr | |
7c612bfd NP |
839 | |
840 | .align 5 | |
841 | ||
7c612bfd | 842 | __kuser_memory_barrier: @ 0xffff0fa0 |
ed3768a8 | 843 | smp_dmb arm |
ba9b5d76 | 844 | usr_ret lr |
7c612bfd NP |
845 | |
846 | .align 5 | |
2d2669b6 NP |
847 | |
848 | __kuser_cmpxchg: @ 0xffff0fc0 | |
849 | ||
dcef1f63 | 850 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 851 | |
dcef1f63 NP |
852 | /* |
853 | * Poor you. No fast solution possible... | |
854 | * The kernel itself must perform the operation. | |
855 | * A special ghost syscall is used for that (see traps.c). | |
856 | */ | |
5e097445 | 857 | stmfd sp!, {r7, lr} |
55afd264 | 858 | ldr r7, 1f @ it's 20 bits |
cc20d429 | 859 | swi __ARM_NR_cmpxchg |
5e097445 | 860 | ldmfd sp!, {r7, pc} |
cc20d429 | 861 | 1: .word __ARM_NR_cmpxchg |
dcef1f63 NP |
862 | |
863 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 864 | |
b49c0f24 NP |
865 | #ifdef CONFIG_MMU |
866 | ||
2d2669b6 | 867 | /* |
b49c0f24 NP |
868 | * The only thing that can break atomicity in this cmpxchg |
869 | * implementation is either an IRQ or a data abort exception | |
870 | * causing another process/thread to be scheduled in the middle | |
871 | * of the critical sequence. To prevent this, code is added to | |
872 | * the IRQ and data abort exception handlers to set the pc back | |
873 | * to the beginning of the critical section if it is found to be | |
874 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 875 | */ |
b49c0f24 NP |
876 | 1: ldr r3, [r2] @ load current val |
877 | subs r3, r3, r0 @ compare with oldval | |
878 | 2: streq r1, [r2] @ store newval if eq | |
879 | rsbs r0, r3, #0 @ set return val and C flag | |
880 | usr_ret lr | |
881 | ||
882 | .text | |
40fb79c8 | 883 | kuser_cmpxchg32_fixup: |
b49c0f24 | 884 | @ Called from kuser_cmpxchg_check macro. |
b059bdc3 | 885 | @ r4 = address of interrupted insn (must be preserved). |
b49c0f24 NP |
886 | @ sp = saved regs. r7 and r8 are clobbered. |
887 | @ 1b = first critical insn, 2b = last critical insn. | |
b059bdc3 | 888 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
b49c0f24 NP |
889 | mov r7, #0xffff0fff |
890 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
b059bdc3 | 891 | subs r8, r4, r7 |
b49c0f24 NP |
892 | rsbcss r8, r8, #(2b - 1b) |
893 | strcs r7, [sp, #S_PC] | |
894 | mov pc, lr | |
895 | .previous | |
896 | ||
49bca4c2 NP |
897 | #else |
898 | #warning "NPTL on non MMU needs fixing" | |
899 | mov r0, #-1 | |
900 | adds r0, r0, #0 | |
ba9b5d76 | 901 | usr_ret lr |
b49c0f24 | 902 | #endif |
2d2669b6 NP |
903 | |
904 | #else | |
905 | ||
ed3768a8 | 906 | smp_dmb arm |
b49c0f24 | 907 | 1: ldrex r3, [r2] |
2d2669b6 NP |
908 | subs r3, r3, r0 |
909 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
910 | teqeq r3, #1 |
911 | beq 1b | |
2d2669b6 | 912 | rsbs r0, r3, #0 |
b49c0f24 | 913 | /* beware -- each __kuser slot must be 8 instructions max */ |
f00ec48f RK |
914 | ALT_SMP(b __kuser_memory_barrier) |
915 | ALT_UP(usr_ret lr) | |
2d2669b6 NP |
916 | |
917 | #endif | |
918 | ||
919 | .align 5 | |
920 | ||
2d2669b6 | 921 | __kuser_get_tls: @ 0xffff0fe0 |
f159f4ed | 922 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
ba9b5d76 | 923 | usr_ret lr |
f159f4ed TL |
924 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
925 | .rep 4 | |
926 | .word 0 @ 0xffff0ff0 software TLS value, then | |
927 | .endr @ pad up to __kuser_helper_version | |
2d2669b6 | 928 | |
2d2669b6 NP |
929 | __kuser_helper_version: @ 0xffff0ffc |
930 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
931 | ||
932 | .globl __kuser_helper_end | |
933 | __kuser_helper_end: | |
934 | ||
b86040a5 | 935 | THUMB( .thumb ) |
2d2669b6 | 936 | |
1da177e4 LT |
937 | /* |
938 | * Vector stubs. | |
939 | * | |
7933523d RK |
940 | * This code is copied to 0xffff0200 so we can use branches in the |
941 | * vectors, rather than ldr's. Note that this code must not | |
942 | * exceed 0x300 bytes. | |
1da177e4 LT |
943 | * |
944 | * Common stub entry macro: | |
945 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
946 | * |
947 | * SP points to a minimal amount of processor-private memory, the address | |
948 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 949 | */ |
b7ec4795 | 950 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
951 | .align 5 |
952 | ||
953 | vector_\name: | |
1da177e4 LT |
954 | .if \correction |
955 | sub lr, lr, #\correction | |
956 | .endif | |
ccea7a19 RK |
957 | |
958 | @ | |
959 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
960 | @ (parent CPSR) | |
961 | @ | |
962 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 963 | mrs lr, spsr |
ccea7a19 RK |
964 | str lr, [sp, #8] @ save spsr |
965 | ||
1da177e4 | 966 | @ |
ccea7a19 | 967 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 968 | @ |
ccea7a19 | 969 | mrs r0, cpsr |
b86040a5 | 970 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 971 | msr spsr_cxsf, r0 |
1da177e4 | 972 | |
ccea7a19 RK |
973 | @ |
974 | @ the branch table must immediately follow this code | |
975 | @ | |
ccea7a19 | 976 | and lr, lr, #0x0f |
b86040a5 CM |
977 | THUMB( adr r0, 1f ) |
978 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 979 | mov r0, sp |
b86040a5 | 980 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 981 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 982 | ENDPROC(vector_\name) |
88987ef9 CM |
983 | |
984 | .align 2 | |
985 | @ handler addresses follow this label | |
986 | 1: | |
1da177e4 LT |
987 | .endm |
988 | ||
7933523d | 989 | .globl __stubs_start |
1da177e4 LT |
990 | __stubs_start: |
991 | /* | |
992 | * Interrupt dispatcher | |
993 | */ | |
b7ec4795 | 994 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
995 | |
996 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
997 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
998 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
999 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1000 | .long __irq_invalid @ 4 | |
1001 | .long __irq_invalid @ 5 | |
1002 | .long __irq_invalid @ 6 | |
1003 | .long __irq_invalid @ 7 | |
1004 | .long __irq_invalid @ 8 | |
1005 | .long __irq_invalid @ 9 | |
1006 | .long __irq_invalid @ a | |
1007 | .long __irq_invalid @ b | |
1008 | .long __irq_invalid @ c | |
1009 | .long __irq_invalid @ d | |
1010 | .long __irq_invalid @ e | |
1011 | .long __irq_invalid @ f | |
1012 | ||
1013 | /* | |
1014 | * Data abort dispatcher | |
1015 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1016 | */ | |
b7ec4795 | 1017 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1018 | |
1019 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1020 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1021 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1022 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1023 | .long __dabt_invalid @ 4 | |
1024 | .long __dabt_invalid @ 5 | |
1025 | .long __dabt_invalid @ 6 | |
1026 | .long __dabt_invalid @ 7 | |
1027 | .long __dabt_invalid @ 8 | |
1028 | .long __dabt_invalid @ 9 | |
1029 | .long __dabt_invalid @ a | |
1030 | .long __dabt_invalid @ b | |
1031 | .long __dabt_invalid @ c | |
1032 | .long __dabt_invalid @ d | |
1033 | .long __dabt_invalid @ e | |
1034 | .long __dabt_invalid @ f | |
1035 | ||
1036 | /* | |
1037 | * Prefetch abort dispatcher | |
1038 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1039 | */ | |
b7ec4795 | 1040 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1041 | |
1042 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1043 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1044 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1045 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1046 | .long __pabt_invalid @ 4 | |
1047 | .long __pabt_invalid @ 5 | |
1048 | .long __pabt_invalid @ 6 | |
1049 | .long __pabt_invalid @ 7 | |
1050 | .long __pabt_invalid @ 8 | |
1051 | .long __pabt_invalid @ 9 | |
1052 | .long __pabt_invalid @ a | |
1053 | .long __pabt_invalid @ b | |
1054 | .long __pabt_invalid @ c | |
1055 | .long __pabt_invalid @ d | |
1056 | .long __pabt_invalid @ e | |
1057 | .long __pabt_invalid @ f | |
1058 | ||
1059 | /* | |
1060 | * Undef instr entry dispatcher | |
1061 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1062 | */ | |
b7ec4795 | 1063 | vector_stub und, UND_MODE |
1da177e4 LT |
1064 | |
1065 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1066 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1067 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1068 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1069 | .long __und_invalid @ 4 | |
1070 | .long __und_invalid @ 5 | |
1071 | .long __und_invalid @ 6 | |
1072 | .long __und_invalid @ 7 | |
1073 | .long __und_invalid @ 8 | |
1074 | .long __und_invalid @ 9 | |
1075 | .long __und_invalid @ a | |
1076 | .long __und_invalid @ b | |
1077 | .long __und_invalid @ c | |
1078 | .long __und_invalid @ d | |
1079 | .long __und_invalid @ e | |
1080 | .long __und_invalid @ f | |
1081 | ||
1082 | .align 5 | |
1083 | ||
1084 | /*============================================================================= | |
1085 | * Undefined FIQs | |
1086 | *----------------------------------------------------------------------------- | |
1087 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1088 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1089 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1090 | * damage alert! I don't think that we can execute any code in here in any | |
1091 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1092 | * get out of that mode without clobbering one register. | |
1093 | */ | |
1094 | vector_fiq: | |
1da177e4 LT |
1095 | subs pc, lr, #4 |
1096 | ||
1097 | /*============================================================================= | |
1098 | * Address exception handler | |
1099 | *----------------------------------------------------------------------------- | |
1100 | * These aren't too critical. | |
1101 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1102 | */ | |
1103 | ||
1104 | vector_addrexcptn: | |
1105 | b vector_addrexcptn | |
1106 | ||
1107 | /* | |
1108 | * We group all the following data together to optimise | |
1109 | * for CPUs with separate I & D caches. | |
1110 | */ | |
1111 | .align 5 | |
1112 | ||
1113 | .LCvswi: | |
1114 | .word vector_swi | |
1115 | ||
7933523d | 1116 | .globl __stubs_end |
1da177e4 LT |
1117 | __stubs_end: |
1118 | ||
7933523d | 1119 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1120 | |
7933523d RK |
1121 | .globl __vectors_start |
1122 | __vectors_start: | |
b86040a5 CM |
1123 | ARM( swi SYS_ERROR0 ) |
1124 | THUMB( svc #0 ) | |
1125 | THUMB( nop ) | |
1126 | W(b) vector_und + stubs_offset | |
1127 | W(ldr) pc, .LCvswi + stubs_offset | |
1128 | W(b) vector_pabt + stubs_offset | |
1129 | W(b) vector_dabt + stubs_offset | |
1130 | W(b) vector_addrexcptn + stubs_offset | |
1131 | W(b) vector_irq + stubs_offset | |
1132 | W(b) vector_fiq + stubs_offset | |
7933523d RK |
1133 | |
1134 | .globl __vectors_end | |
1135 | __vectors_end: | |
1da177e4 LT |
1136 | |
1137 | .data | |
1138 | ||
1da177e4 LT |
1139 | .globl cr_alignment |
1140 | .globl cr_no_alignment | |
1141 | cr_alignment: | |
1142 | .space 4 | |
1143 | cr_no_alignment: | |
1144 | .space 4 | |
52108641 | 1145 | |
1146 | #ifdef CONFIG_MULTI_IRQ_HANDLER | |
1147 | .globl handle_arch_irq | |
1148 | handle_arch_irq: | |
1149 | .space 4 | |
1150 | #endif |