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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
f09b9979 | 18 | #include <asm/memory.h> |
753790e7 RK |
19 | #include <asm/glue-df.h> |
20 | #include <asm/glue-pf.h> | |
1da177e4 | 21 | #include <asm/vfpmacros.h> |
a09e64fb | 22 | #include <mach/entry-macro.S> |
d6551e88 | 23 | #include <asm/thread_notify.h> |
c4c5716e | 24 | #include <asm/unwind.h> |
cc20d429 | 25 | #include <asm/unistd.h> |
f159f4ed | 26 | #include <asm/tls.h> |
1da177e4 LT |
27 | |
28 | #include "entry-header.S" | |
cd544ce7 | 29 | #include <asm/entry-macro-multi.S> |
1da177e4 | 30 | |
187a51ad RK |
31 | /* |
32 | * Interrupt handling. Preserves r7, r8, r9 | |
33 | */ | |
34 | .macro irq_handler | |
52108641 | 35 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
36 | ldr r5, =handle_arch_irq | |
37 | mov r0, sp | |
38 | ldr r5, [r5] | |
39 | adr lr, BSYM(9997f) | |
40 | teq r5, #0 | |
41 | movne pc, r5 | |
37ee16ae | 42 | #endif |
cd544ce7 | 43 | arch_irq_handler_default |
f00ec48f | 44 | 9997: |
187a51ad RK |
45 | .endm |
46 | ||
ac8b9c1c RK |
47 | .macro pabt_helper |
48 | mov r0, r2 @ pass address of aborted instruction. | |
49 | #ifdef MULTI_PABORT | |
0402bece | 50 | ldr ip, .LCprocfns |
ac8b9c1c | 51 | mov lr, pc |
0402bece | 52 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
ac8b9c1c RK |
53 | #else |
54 | bl CPU_PABORT_HANDLER | |
55 | #endif | |
56 | .endm | |
57 | ||
58 | .macro dabt_helper | |
59 | ||
60 | @ | |
61 | @ Call the processor-specific abort handler: | |
62 | @ | |
63 | @ r2 - aborted context pc | |
64 | @ r3 - aborted context cpsr | |
65 | @ | |
66 | @ The abort handler must return the aborted address in r0, and | |
67 | @ the fault status register in r1. r9 must be preserved. | |
68 | @ | |
69 | #ifdef MULTI_DABORT | |
0402bece | 70 | ldr ip, .LCprocfns |
ac8b9c1c | 71 | mov lr, pc |
0402bece | 72 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
ac8b9c1c RK |
73 | #else |
74 | bl CPU_DABORT_HANDLER | |
75 | #endif | |
76 | .endm | |
77 | ||
785d3cd2 NP |
78 | #ifdef CONFIG_KPROBES |
79 | .section .kprobes.text,"ax",%progbits | |
80 | #else | |
81 | .text | |
82 | #endif | |
83 | ||
1da177e4 LT |
84 | /* |
85 | * Invalid mode handlers | |
86 | */ | |
ccea7a19 RK |
87 | .macro inv_entry, reason |
88 | sub sp, sp, #S_FRAME_SIZE | |
b86040a5 CM |
89 | ARM( stmib sp, {r1 - lr} ) |
90 | THUMB( stmia sp, {r0 - r12} ) | |
91 | THUMB( str sp, [sp, #S_SP] ) | |
92 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
93 | mov r1, #\reason |
94 | .endm | |
95 | ||
96 | __pabt_invalid: | |
ccea7a19 RK |
97 | inv_entry BAD_PREFETCH |
98 | b common_invalid | |
93ed3970 | 99 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
100 | |
101 | __dabt_invalid: | |
ccea7a19 RK |
102 | inv_entry BAD_DATA |
103 | b common_invalid | |
93ed3970 | 104 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
105 | |
106 | __irq_invalid: | |
ccea7a19 RK |
107 | inv_entry BAD_IRQ |
108 | b common_invalid | |
93ed3970 | 109 | ENDPROC(__irq_invalid) |
1da177e4 LT |
110 | |
111 | __und_invalid: | |
ccea7a19 RK |
112 | inv_entry BAD_UNDEFINSTR |
113 | ||
114 | @ | |
115 | @ XXX fall through to common_invalid | |
116 | @ | |
117 | ||
118 | @ | |
119 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
120 | @ | |
121 | common_invalid: | |
122 | zero_fp | |
123 | ||
124 | ldmia r0, {r4 - r6} | |
125 | add r0, sp, #S_PC @ here for interlock avoidance | |
126 | mov r7, #-1 @ "" "" "" "" | |
127 | str r4, [sp] @ save preserved r0 | |
128 | stmia r0, {r5 - r7} @ lr_<exception>, | |
129 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 130 | |
1da177e4 | 131 | mov r0, sp |
1da177e4 | 132 | b bad_mode |
93ed3970 | 133 | ENDPROC(__und_invalid) |
1da177e4 LT |
134 | |
135 | /* | |
136 | * SVC mode handlers | |
137 | */ | |
2dede2d8 NP |
138 | |
139 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
140 | #define SPFIX(code...) code | |
141 | #else | |
142 | #define SPFIX(code...) | |
143 | #endif | |
144 | ||
d30a0c8b | 145 | .macro svc_entry, stack_hole=0 |
c4c5716e CM |
146 | UNWIND(.fnstart ) |
147 | UNWIND(.save {r0 - pc} ) | |
b86040a5 CM |
148 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
149 | #ifdef CONFIG_THUMB2_KERNEL | |
150 | SPFIX( str r0, [sp] ) @ temporarily saved | |
151 | SPFIX( mov r0, sp ) | |
152 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
153 | SPFIX( ldr r0, [sp] ) @ restored | |
154 | #else | |
2dede2d8 | 155 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
156 | #endif |
157 | SPFIX( subeq sp, sp, #4 ) | |
158 | stmia sp, {r1 - r12} | |
ccea7a19 RK |
159 | |
160 | ldmia r0, {r1 - r3} | |
b86040a5 | 161 | add r5, sp, #S_SP - 4 @ here for interlock avoidance |
ccea7a19 | 162 | mov r4, #-1 @ "" "" "" "" |
b86040a5 CM |
163 | add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
164 | SPFIX( addeq r0, r0, #4 ) | |
165 | str r1, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
166 | @ from the exception stack |
167 | ||
1da177e4 LT |
168 | mov r1, lr |
169 | ||
170 | @ | |
171 | @ We are now ready to fill in the remaining blanks on the stack: | |
172 | @ | |
173 | @ r0 - sp_svc | |
174 | @ r1 - lr_svc | |
175 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
176 | @ r3 - spsr_<exception> | |
177 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
178 | @ | |
179 | stmia r5, {r0 - r4} | |
180 | .endm | |
181 | ||
182 | .align 5 | |
183 | __dabt_svc: | |
ccea7a19 | 184 | svc_entry |
1da177e4 LT |
185 | |
186 | @ | |
187 | @ get ready to re-enable interrupts if appropriate | |
188 | @ | |
189 | mrs r9, cpsr | |
190 | tst r3, #PSR_I_BIT | |
191 | biceq r9, r9, #PSR_I_BIT | |
192 | ||
ac8b9c1c | 193 | dabt_helper |
1da177e4 LT |
194 | |
195 | @ | |
196 | @ set desired IRQ state, then call main handler | |
197 | @ | |
7e202696 | 198 | debug_entry r1 |
1da177e4 LT |
199 | msr cpsr_c, r9 |
200 | mov r2, sp | |
201 | bl do_DataAbort | |
202 | ||
203 | @ | |
204 | @ IRQs off again before pulling preserved data off the stack | |
205 | @ | |
ac78884e | 206 | disable_irq_notrace |
1da177e4 LT |
207 | |
208 | @ | |
209 | @ restore SPSR and restart the instruction | |
210 | @ | |
b86040a5 CM |
211 | ldr r2, [sp, #S_PSR] |
212 | svc_exit r2 @ return from exception | |
c4c5716e | 213 | UNWIND(.fnend ) |
93ed3970 | 214 | ENDPROC(__dabt_svc) |
1da177e4 LT |
215 | |
216 | .align 5 | |
217 | __irq_svc: | |
ccea7a19 RK |
218 | svc_entry |
219 | ||
ac78884e RK |
220 | #ifdef CONFIG_TRACE_IRQFLAGS |
221 | bl trace_hardirqs_off | |
222 | #endif | |
ccea7a19 | 223 | |
187a51ad | 224 | irq_handler |
1613cc11 | 225 | |
1da177e4 | 226 | #ifdef CONFIG_PREEMPT |
1613cc11 RK |
227 | get_thread_info tsk |
228 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
706fdd9f | 229 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
230 | teq r8, #0 @ if preempt count != 0 |
231 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
232 | tst r0, #_TIF_NEED_RESCHED |
233 | blne svc_preempt | |
1da177e4 | 234 | #endif |
b86040a5 | 235 | ldr r4, [sp, #S_PSR] @ irqs are already disabled |
7ad1bcb2 | 236 | #ifdef CONFIG_TRACE_IRQFLAGS |
b86040a5 | 237 | tst r4, #PSR_I_BIT |
7ad1bcb2 RK |
238 | bleq trace_hardirqs_on |
239 | #endif | |
b86040a5 | 240 | svc_exit r4 @ return from exception |
c4c5716e | 241 | UNWIND(.fnend ) |
93ed3970 | 242 | ENDPROC(__irq_svc) |
1da177e4 LT |
243 | |
244 | .ltorg | |
245 | ||
246 | #ifdef CONFIG_PREEMPT | |
247 | svc_preempt: | |
28fab1a2 | 248 | mov r8, lr |
1da177e4 | 249 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 250 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 251 | tst r0, #_TIF_NEED_RESCHED |
28fab1a2 | 252 | moveq pc, r8 @ go again |
1da177e4 LT |
253 | b 1b |
254 | #endif | |
255 | ||
256 | .align 5 | |
257 | __und_svc: | |
d30a0c8b NP |
258 | #ifdef CONFIG_KPROBES |
259 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
260 | @ it obviously needs free stack space which then will belong to | |
261 | @ the saved context. | |
262 | svc_entry 64 | |
263 | #else | |
ccea7a19 | 264 | svc_entry |
d30a0c8b | 265 | #endif |
1da177e4 LT |
266 | |
267 | @ | |
268 | @ call emulation code, which returns using r9 if it has emulated | |
269 | @ the instruction, or the more conventional lr if we are to treat | |
270 | @ this as a real undefined instruction | |
271 | @ | |
272 | @ r0 - instruction | |
273 | @ | |
83e686ea | 274 | #ifndef CONFIG_THUMB2_KERNEL |
1da177e4 | 275 | ldr r0, [r2, #-4] |
83e686ea CM |
276 | #else |
277 | ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2 | |
278 | and r9, r0, #0xf800 | |
279 | cmp r9, #0xe800 @ 32-bit instruction if xx >= 0 | |
280 | ldrhhs r9, [r2] @ bottom 16 bits | |
281 | orrhs r0, r9, r0, lsl #16 | |
282 | #endif | |
b86040a5 | 283 | adr r9, BSYM(1f) |
1da177e4 LT |
284 | bl call_fpe |
285 | ||
286 | mov r0, sp @ struct pt_regs *regs | |
287 | bl do_undefinstr | |
288 | ||
289 | @ | |
290 | @ IRQs off again before pulling preserved data off the stack | |
291 | @ | |
ac78884e | 292 | 1: disable_irq_notrace |
1da177e4 LT |
293 | |
294 | @ | |
295 | @ restore SPSR and restart the instruction | |
296 | @ | |
b86040a5 CM |
297 | ldr r2, [sp, #S_PSR] @ Get SVC cpsr |
298 | svc_exit r2 @ return from exception | |
c4c5716e | 299 | UNWIND(.fnend ) |
93ed3970 | 300 | ENDPROC(__und_svc) |
1da177e4 LT |
301 | |
302 | .align 5 | |
303 | __pabt_svc: | |
ccea7a19 | 304 | svc_entry |
1da177e4 LT |
305 | |
306 | @ | |
307 | @ re-enable interrupts if appropriate | |
308 | @ | |
309 | mrs r9, cpsr | |
310 | tst r3, #PSR_I_BIT | |
311 | biceq r9, r9, #PSR_I_BIT | |
1da177e4 | 312 | |
ac8b9c1c | 313 | pabt_helper |
7e202696 | 314 | debug_entry r1 |
48d7927b | 315 | msr cpsr_c, r9 @ Maybe enable interrupts |
4fb28474 | 316 | mov r2, sp @ regs |
1da177e4 LT |
317 | bl do_PrefetchAbort @ call abort handler |
318 | ||
319 | @ | |
320 | @ IRQs off again before pulling preserved data off the stack | |
321 | @ | |
ac78884e | 322 | disable_irq_notrace |
1da177e4 LT |
323 | |
324 | @ | |
325 | @ restore SPSR and restart the instruction | |
326 | @ | |
b86040a5 CM |
327 | ldr r2, [sp, #S_PSR] |
328 | svc_exit r2 @ return from exception | |
c4c5716e | 329 | UNWIND(.fnend ) |
93ed3970 | 330 | ENDPROC(__pabt_svc) |
1da177e4 LT |
331 | |
332 | .align 5 | |
49f680ea RK |
333 | .LCcralign: |
334 | .word cr_alignment | |
48d7927b | 335 | #ifdef MULTI_DABORT |
1da177e4 LT |
336 | .LCprocfns: |
337 | .word processor | |
338 | #endif | |
339 | .LCfp: | |
340 | .word fp_enter | |
1da177e4 LT |
341 | |
342 | /* | |
343 | * User mode handlers | |
2dede2d8 NP |
344 | * |
345 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 346 | */ |
2dede2d8 NP |
347 | |
348 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
349 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
350 | #endif | |
351 | ||
ccea7a19 | 352 | .macro usr_entry |
c4c5716e CM |
353 | UNWIND(.fnstart ) |
354 | UNWIND(.cantunwind ) @ don't unwind the user space | |
ccea7a19 | 355 | sub sp, sp, #S_FRAME_SIZE |
b86040a5 CM |
356 | ARM( stmib sp, {r1 - r12} ) |
357 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 RK |
358 | |
359 | ldmia r0, {r1 - r3} | |
360 | add r0, sp, #S_PC @ here for interlock avoidance | |
361 | mov r4, #-1 @ "" "" "" "" | |
362 | ||
363 | str r1, [sp] @ save the "real" r0 copied | |
364 | @ from the exception stack | |
1da177e4 LT |
365 | |
366 | @ | |
367 | @ We are now ready to fill in the remaining blanks on the stack: | |
368 | @ | |
369 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
370 | @ r3 - spsr_<exception> | |
371 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
372 | @ | |
373 | @ Also, separately save sp_usr and lr_usr | |
374 | @ | |
ccea7a19 | 375 | stmia r0, {r2 - r4} |
b86040a5 CM |
376 | ARM( stmdb r0, {sp, lr}^ ) |
377 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 LT |
378 | |
379 | @ | |
380 | @ Enable the alignment trap while in kernel mode | |
381 | @ | |
49f680ea | 382 | alignment_trap r0 |
1da177e4 LT |
383 | |
384 | @ | |
385 | @ Clear FP to mark the first stack frame | |
386 | @ | |
387 | zero_fp | |
388 | .endm | |
389 | ||
b49c0f24 NP |
390 | .macro kuser_cmpxchg_check |
391 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
392 | #ifndef CONFIG_MMU | |
393 | #warning "NPTL on non MMU needs fixing" | |
394 | #else | |
395 | @ Make sure our user space atomic helper is restarted | |
396 | @ if it was interrupted in a critical region. Here we | |
397 | @ perform a quick test inline since it should be false | |
398 | @ 99.9999% of the time. The rest is done out of line. | |
399 | cmp r2, #TASK_SIZE | |
400 | blhs kuser_cmpxchg_fixup | |
401 | #endif | |
402 | #endif | |
403 | .endm | |
404 | ||
1da177e4 LT |
405 | .align 5 |
406 | __dabt_usr: | |
ccea7a19 | 407 | usr_entry |
b49c0f24 | 408 | kuser_cmpxchg_check |
ac8b9c1c | 409 | dabt_helper |
1da177e4 LT |
410 | |
411 | @ | |
412 | @ IRQs on, then call the main handler | |
413 | @ | |
7e202696 | 414 | debug_entry r1 |
1ec42c0c | 415 | enable_irq |
1da177e4 | 416 | mov r2, sp |
b86040a5 | 417 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 418 | b do_DataAbort |
c4c5716e | 419 | UNWIND(.fnend ) |
93ed3970 | 420 | ENDPROC(__dabt_usr) |
1da177e4 LT |
421 | |
422 | .align 5 | |
423 | __irq_usr: | |
ccea7a19 | 424 | usr_entry |
b49c0f24 | 425 | kuser_cmpxchg_check |
1da177e4 | 426 | |
9fc2552a ML |
427 | #ifdef CONFIG_IRQSOFF_TRACER |
428 | bl trace_hardirqs_off | |
429 | #endif | |
430 | ||
187a51ad | 431 | irq_handler |
1613cc11 | 432 | get_thread_info tsk |
1da177e4 | 433 | mov why, #0 |
9fc2552a | 434 | b ret_to_user_from_irq |
c4c5716e | 435 | UNWIND(.fnend ) |
93ed3970 | 436 | ENDPROC(__irq_usr) |
1da177e4 LT |
437 | |
438 | .ltorg | |
439 | ||
440 | .align 5 | |
441 | __und_usr: | |
ccea7a19 | 442 | usr_entry |
1da177e4 | 443 | |
1da177e4 LT |
444 | @ |
445 | @ fall through to the emulation code, which returns using r9 if | |
446 | @ it has emulated the instruction, or the more conventional lr | |
447 | @ if we are to treat this as a real undefined instruction | |
448 | @ | |
449 | @ r0 - instruction | |
450 | @ | |
b86040a5 CM |
451 | adr r9, BSYM(ret_from_exception) |
452 | adr lr, BSYM(__und_usr_unknown) | |
cb170a45 | 453 | tst r3, #PSR_T_BIT @ Thumb mode? |
b86040a5 | 454 | itet eq @ explicit IT needed for the 1f label |
cb170a45 PB |
455 | subeq r4, r2, #4 @ ARM instr at LR - 4 |
456 | subne r4, r2, #2 @ Thumb instr at LR - 2 | |
457 | 1: ldreqt r0, [r4] | |
26584853 CM |
458 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
459 | reveq r0, r0 @ little endian instruction | |
460 | #endif | |
cb170a45 PB |
461 | beq call_fpe |
462 | @ Thumb instruction | |
463 | #if __LINUX_ARM_ARCH__ >= 7 | |
b86040a5 CM |
464 | 2: |
465 | ARM( ldrht r5, [r4], #2 ) | |
466 | THUMB( ldrht r5, [r4] ) | |
467 | THUMB( add r4, r4, #2 ) | |
cb170a45 PB |
468 | and r0, r5, #0xf800 @ mask bits 111x x... .... .... |
469 | cmp r0, #0xe800 @ 32bit instruction if xx != 0 | |
470 | blo __und_usr_unknown | |
471 | 3: ldrht r0, [r4] | |
472 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 | |
473 | orr r0, r0, r5, lsl #16 | |
474 | #else | |
475 | b __und_usr_unknown | |
476 | #endif | |
c4c5716e | 477 | UNWIND(.fnend ) |
93ed3970 | 478 | ENDPROC(__und_usr) |
cb170a45 | 479 | |
1da177e4 LT |
480 | @ |
481 | @ fallthrough to call_fpe | |
482 | @ | |
483 | ||
484 | /* | |
485 | * The out of line fixup for the ldrt above. | |
486 | */ | |
4260415f | 487 | .pushsection .fixup, "ax" |
cb170a45 | 488 | 4: mov pc, r9 |
4260415f RK |
489 | .popsection |
490 | .pushsection __ex_table,"a" | |
cb170a45 PB |
491 | .long 1b, 4b |
492 | #if __LINUX_ARM_ARCH__ >= 7 | |
493 | .long 2b, 4b | |
494 | .long 3b, 4b | |
495 | #endif | |
4260415f | 496 | .popsection |
1da177e4 LT |
497 | |
498 | /* | |
499 | * Check whether the instruction is a co-processor instruction. | |
500 | * If yes, we need to call the relevant co-processor handler. | |
501 | * | |
502 | * Note that we don't do a full check here for the co-processor | |
503 | * instructions; all instructions with bit 27 set are well | |
504 | * defined. The only instructions that should fault are the | |
505 | * co-processor instructions. However, we have to watch out | |
506 | * for the ARM6/ARM7 SWI bug. | |
507 | * | |
b5872db4 CM |
508 | * NEON is a special case that has to be handled here. Not all |
509 | * NEON instructions are co-processor instructions, so we have | |
510 | * to make a special case of checking for them. Plus, there's | |
511 | * five groups of them, so we have a table of mask/opcode pairs | |
512 | * to check against, and if any match then we branch off into the | |
513 | * NEON handler code. | |
514 | * | |
1da177e4 LT |
515 | * Emulators may wish to make use of the following registers: |
516 | * r0 = instruction opcode. | |
517 | * r2 = PC+4 | |
db6ccbb6 | 518 | * r9 = normal "successful" return address |
1da177e4 | 519 | * r10 = this threads thread_info structure. |
db6ccbb6 | 520 | * lr = unrecognised instruction return address |
1da177e4 | 521 | */ |
cb170a45 PB |
522 | @ |
523 | @ Fall-through from Thumb-2 __und_usr | |
524 | @ | |
525 | #ifdef CONFIG_NEON | |
526 | adr r6, .LCneon_thumb_opcodes | |
527 | b 2f | |
528 | #endif | |
1da177e4 | 529 | call_fpe: |
b5872db4 | 530 | #ifdef CONFIG_NEON |
cb170a45 | 531 | adr r6, .LCneon_arm_opcodes |
b5872db4 CM |
532 | 2: |
533 | ldr r7, [r6], #4 @ mask value | |
534 | cmp r7, #0 @ end mask? | |
535 | beq 1f | |
536 | and r8, r0, r7 | |
537 | ldr r7, [r6], #4 @ opcode bits matching in mask | |
538 | cmp r8, r7 @ NEON instruction? | |
539 | bne 2b | |
540 | get_thread_info r10 | |
541 | mov r7, #1 | |
542 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
543 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
544 | b do_vfp @ let VFP handler handle this | |
545 | 1: | |
546 | #endif | |
1da177e4 | 547 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 548 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
1da177e4 LT |
549 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) |
550 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
551 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
552 | #endif | |
553 | moveq pc, lr | |
554 | get_thread_info r10 @ get current thread | |
555 | and r8, r0, #0x00000f00 @ mask out CP number | |
b86040a5 | 556 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
557 | mov r7, #1 |
558 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
559 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
560 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
561 | #ifdef CONFIG_IWMMXT |
562 | @ Test if we need to give access to iWMMXt coprocessors | |
563 | ldr r5, [r10, #TI_FLAGS] | |
564 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
565 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
566 | bcs iwmmxt_task_enable | |
567 | #endif | |
b86040a5 CM |
568 | ARM( add pc, pc, r8, lsr #6 ) |
569 | THUMB( lsl r8, r8, #2 ) | |
570 | THUMB( add pc, r8 ) | |
571 | nop | |
572 | ||
a771fe6e | 573 | movw_pc lr @ CP#0 |
b86040a5 CM |
574 | W(b) do_fpe @ CP#1 (FPE) |
575 | W(b) do_fpe @ CP#2 (FPE) | |
a771fe6e | 576 | movw_pc lr @ CP#3 |
c17fad11 LB |
577 | #ifdef CONFIG_CRUNCH |
578 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
579 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
580 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
581 | #else | |
a771fe6e CM |
582 | movw_pc lr @ CP#4 |
583 | movw_pc lr @ CP#5 | |
584 | movw_pc lr @ CP#6 | |
c17fad11 | 585 | #endif |
a771fe6e CM |
586 | movw_pc lr @ CP#7 |
587 | movw_pc lr @ CP#8 | |
588 | movw_pc lr @ CP#9 | |
1da177e4 | 589 | #ifdef CONFIG_VFP |
b86040a5 CM |
590 | W(b) do_vfp @ CP#10 (VFP) |
591 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 592 | #else |
a771fe6e CM |
593 | movw_pc lr @ CP#10 (VFP) |
594 | movw_pc lr @ CP#11 (VFP) | |
1da177e4 | 595 | #endif |
a771fe6e CM |
596 | movw_pc lr @ CP#12 |
597 | movw_pc lr @ CP#13 | |
598 | movw_pc lr @ CP#14 (Debug) | |
599 | movw_pc lr @ CP#15 (Control) | |
1da177e4 | 600 | |
b5872db4 CM |
601 | #ifdef CONFIG_NEON |
602 | .align 6 | |
603 | ||
cb170a45 | 604 | .LCneon_arm_opcodes: |
b5872db4 CM |
605 | .word 0xfe000000 @ mask |
606 | .word 0xf2000000 @ opcode | |
607 | ||
608 | .word 0xff100000 @ mask | |
609 | .word 0xf4000000 @ opcode | |
610 | ||
cb170a45 PB |
611 | .word 0x00000000 @ mask |
612 | .word 0x00000000 @ opcode | |
613 | ||
614 | .LCneon_thumb_opcodes: | |
615 | .word 0xef000000 @ mask | |
616 | .word 0xef000000 @ opcode | |
617 | ||
618 | .word 0xff100000 @ mask | |
619 | .word 0xf9000000 @ opcode | |
620 | ||
b5872db4 CM |
621 | .word 0x00000000 @ mask |
622 | .word 0x00000000 @ opcode | |
623 | #endif | |
624 | ||
1da177e4 | 625 | do_fpe: |
5d25ac03 | 626 | enable_irq |
1da177e4 LT |
627 | ldr r4, .LCfp |
628 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
629 | ldr pc, [r4] @ Call FP module USR entry point | |
630 | ||
631 | /* | |
632 | * The FP module is called with these registers set: | |
633 | * r0 = instruction | |
634 | * r2 = PC+4 | |
635 | * r9 = normal "successful" return address | |
636 | * r10 = FP workspace | |
637 | * lr = unrecognised FP instruction return address | |
638 | */ | |
639 | ||
124efc27 | 640 | .pushsection .data |
1da177e4 | 641 | ENTRY(fp_enter) |
db6ccbb6 | 642 | .word no_fp |
124efc27 | 643 | .popsection |
1da177e4 | 644 | |
83e686ea CM |
645 | ENTRY(no_fp) |
646 | mov pc, lr | |
647 | ENDPROC(no_fp) | |
db6ccbb6 RK |
648 | |
649 | __und_usr_unknown: | |
ecbab71c | 650 | enable_irq |
1da177e4 | 651 | mov r0, sp |
b86040a5 | 652 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 653 | b do_undefinstr |
93ed3970 | 654 | ENDPROC(__und_usr_unknown) |
1da177e4 LT |
655 | |
656 | .align 5 | |
657 | __pabt_usr: | |
ccea7a19 | 658 | usr_entry |
ac8b9c1c | 659 | pabt_helper |
7e202696 | 660 | debug_entry r1 |
1ec42c0c | 661 | enable_irq @ Enable interrupts |
4fb28474 | 662 | mov r2, sp @ regs |
1da177e4 | 663 | bl do_PrefetchAbort @ call abort handler |
c4c5716e | 664 | UNWIND(.fnend ) |
1da177e4 LT |
665 | /* fall through */ |
666 | /* | |
667 | * This is the return code to user mode for abort handlers | |
668 | */ | |
669 | ENTRY(ret_from_exception) | |
c4c5716e CM |
670 | UNWIND(.fnstart ) |
671 | UNWIND(.cantunwind ) | |
1da177e4 LT |
672 | get_thread_info tsk |
673 | mov why, #0 | |
674 | b ret_to_user | |
c4c5716e | 675 | UNWIND(.fnend ) |
93ed3970 CM |
676 | ENDPROC(__pabt_usr) |
677 | ENDPROC(ret_from_exception) | |
1da177e4 LT |
678 | |
679 | /* | |
680 | * Register switch for ARMv3 and ARMv4 processors | |
681 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
682 | * previous and next are guaranteed not to be the same. | |
683 | */ | |
684 | ENTRY(__switch_to) | |
c4c5716e CM |
685 | UNWIND(.fnstart ) |
686 | UNWIND(.cantunwind ) | |
1da177e4 LT |
687 | add ip, r1, #TI_CPU_SAVE |
688 | ldr r3, [r2, #TI_TP_VALUE] | |
b86040a5 CM |
689 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
690 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
691 | THUMB( str sp, [ip], #4 ) | |
692 | THUMB( str lr, [ip], #4 ) | |
247055aa | 693 | #ifdef CONFIG_CPU_USE_DOMAINS |
d6551e88 | 694 | ldr r6, [r2, #TI_CPU_DOMAIN] |
afeb90ca | 695 | #endif |
f159f4ed | 696 | set_tls r3, r4, r5 |
df0698be NP |
697 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
698 | ldr r7, [r2, #TI_TASK] | |
699 | ldr r8, =__stack_chk_guard | |
700 | ldr r7, [r7, #TSK_STACK_CANARY] | |
701 | #endif | |
247055aa | 702 | #ifdef CONFIG_CPU_USE_DOMAINS |
1da177e4 | 703 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 704 | #endif |
d6551e88 RK |
705 | mov r5, r0 |
706 | add r4, r2, #TI_CPU_SAVE | |
707 | ldr r0, =thread_notify_head | |
708 | mov r1, #THREAD_NOTIFY_SWITCH | |
709 | bl atomic_notifier_call_chain | |
df0698be NP |
710 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
711 | str r7, [r8] | |
712 | #endif | |
b86040a5 | 713 | THUMB( mov ip, r4 ) |
d6551e88 | 714 | mov r0, r5 |
b86040a5 CM |
715 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
716 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
717 | THUMB( ldr sp, [ip], #4 ) | |
718 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 719 | UNWIND(.fnend ) |
93ed3970 | 720 | ENDPROC(__switch_to) |
1da177e4 LT |
721 | |
722 | __INIT | |
2d2669b6 NP |
723 | |
724 | /* | |
725 | * User helpers. | |
726 | * | |
727 | * These are segment of kernel provided user code reachable from user space | |
728 | * at a fixed address in kernel memory. This is used to provide user space | |
729 | * with some operations which require kernel help because of unimplemented | |
730 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
731 | * this code to be executed directly in user mode for best efficiency but | |
732 | * which is too intimate with the kernel counter part to be left to user | |
733 | * libraries. In fact this code might even differ from one CPU to another | |
734 | * depending on the available instruction set and restrictions like on | |
735 | * SMP systems. In other words, the kernel reserves the right to change | |
736 | * this code as needed without warning. Only the entry points and their | |
737 | * results are guaranteed to be stable. | |
738 | * | |
739 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
740 | * vector page. New segments (if ever needed) must be added in front of | |
741 | * existing ones. This mechanism should be used only for things that are | |
742 | * really small and justified, and not be abused freely. | |
743 | * | |
744 | * User space is expected to implement those things inline when optimizing | |
745 | * for a processor that has the necessary native support, but only if such | |
746 | * resulting binaries are already to be incompatible with earlier ARM | |
747 | * processors due to the use of unsupported instructions other than what | |
748 | * is provided here. In other words don't make binaries unable to run on | |
749 | * earlier processors just for the sake of not using these kernel helpers | |
750 | * if your compiled code is not going to use the new instructions for other | |
751 | * purpose. | |
752 | */ | |
b86040a5 | 753 | THUMB( .arm ) |
2d2669b6 | 754 | |
ba9b5d76 NP |
755 | .macro usr_ret, reg |
756 | #ifdef CONFIG_ARM_THUMB | |
757 | bx \reg | |
758 | #else | |
759 | mov pc, \reg | |
760 | #endif | |
761 | .endm | |
762 | ||
2d2669b6 NP |
763 | .align 5 |
764 | .globl __kuser_helper_start | |
765 | __kuser_helper_start: | |
766 | ||
7c612bfd NP |
767 | /* |
768 | * Reference prototype: | |
769 | * | |
770 | * void __kernel_memory_barrier(void) | |
771 | * | |
772 | * Input: | |
773 | * | |
774 | * lr = return address | |
775 | * | |
776 | * Output: | |
777 | * | |
778 | * none | |
779 | * | |
780 | * Clobbered: | |
781 | * | |
b49c0f24 | 782 | * none |
7c612bfd NP |
783 | * |
784 | * Definition and user space usage example: | |
785 | * | |
786 | * typedef void (__kernel_dmb_t)(void); | |
787 | * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) | |
788 | * | |
789 | * Apply any needed memory barrier to preserve consistency with data modified | |
790 | * manually and __kuser_cmpxchg usage. | |
791 | * | |
792 | * This could be used as follows: | |
793 | * | |
794 | * #define __kernel_dmb() \ | |
795 | * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ | |
6896eec0 | 796 | * : : : "r0", "lr","cc" ) |
7c612bfd NP |
797 | */ |
798 | ||
799 | __kuser_memory_barrier: @ 0xffff0fa0 | |
ed3768a8 | 800 | smp_dmb arm |
ba9b5d76 | 801 | usr_ret lr |
7c612bfd NP |
802 | |
803 | .align 5 | |
804 | ||
2d2669b6 NP |
805 | /* |
806 | * Reference prototype: | |
807 | * | |
808 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
809 | * | |
810 | * Input: | |
811 | * | |
812 | * r0 = oldval | |
813 | * r1 = newval | |
814 | * r2 = ptr | |
815 | * lr = return address | |
816 | * | |
817 | * Output: | |
818 | * | |
819 | * r0 = returned value (zero or non-zero) | |
820 | * C flag = set if r0 == 0, clear if r0 != 0 | |
821 | * | |
822 | * Clobbered: | |
823 | * | |
824 | * r3, ip, flags | |
825 | * | |
826 | * Definition and user space usage example: | |
827 | * | |
828 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
829 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
830 | * | |
831 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
832 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
833 | * The C flag is also set if *ptr was changed to allow for assembly | |
834 | * optimization in the calling code. | |
835 | * | |
5964eae8 NP |
836 | * Notes: |
837 | * | |
838 | * - This routine already includes memory barriers as needed. | |
839 | * | |
2d2669b6 NP |
840 | * For example, a user space atomic_add implementation could look like this: |
841 | * | |
842 | * #define atomic_add(ptr, val) \ | |
843 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
844 | * register unsigned int __result asm("r1"); \ | |
845 | * asm volatile ( \ | |
846 | * "1: @ atomic_add\n\t" \ | |
847 | * "ldr r0, [r2]\n\t" \ | |
848 | * "mov r3, #0xffff0fff\n\t" \ | |
849 | * "add lr, pc, #4\n\t" \ | |
850 | * "add r1, r0, %2\n\t" \ | |
851 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
852 | * "bcc 1b" \ | |
853 | * : "=&r" (__result) \ | |
854 | * : "r" (__ptr), "rIL" (val) \ | |
855 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
856 | * __result; }) | |
857 | */ | |
858 | ||
859 | __kuser_cmpxchg: @ 0xffff0fc0 | |
860 | ||
dcef1f63 | 861 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 862 | |
dcef1f63 NP |
863 | /* |
864 | * Poor you. No fast solution possible... | |
865 | * The kernel itself must perform the operation. | |
866 | * A special ghost syscall is used for that (see traps.c). | |
867 | */ | |
5e097445 | 868 | stmfd sp!, {r7, lr} |
55afd264 | 869 | ldr r7, 1f @ it's 20 bits |
cc20d429 | 870 | swi __ARM_NR_cmpxchg |
5e097445 | 871 | ldmfd sp!, {r7, pc} |
cc20d429 | 872 | 1: .word __ARM_NR_cmpxchg |
dcef1f63 NP |
873 | |
874 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 875 | |
b49c0f24 NP |
876 | #ifdef CONFIG_MMU |
877 | ||
2d2669b6 | 878 | /* |
b49c0f24 NP |
879 | * The only thing that can break atomicity in this cmpxchg |
880 | * implementation is either an IRQ or a data abort exception | |
881 | * causing another process/thread to be scheduled in the middle | |
882 | * of the critical sequence. To prevent this, code is added to | |
883 | * the IRQ and data abort exception handlers to set the pc back | |
884 | * to the beginning of the critical section if it is found to be | |
885 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 886 | */ |
b49c0f24 NP |
887 | 1: ldr r3, [r2] @ load current val |
888 | subs r3, r3, r0 @ compare with oldval | |
889 | 2: streq r1, [r2] @ store newval if eq | |
890 | rsbs r0, r3, #0 @ set return val and C flag | |
891 | usr_ret lr | |
892 | ||
893 | .text | |
894 | kuser_cmpxchg_fixup: | |
895 | @ Called from kuser_cmpxchg_check macro. | |
896 | @ r2 = address of interrupted insn (must be preserved). | |
897 | @ sp = saved regs. r7 and r8 are clobbered. | |
898 | @ 1b = first critical insn, 2b = last critical insn. | |
899 | @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b. | |
900 | mov r7, #0xffff0fff | |
901 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
902 | subs r8, r2, r7 | |
903 | rsbcss r8, r8, #(2b - 1b) | |
904 | strcs r7, [sp, #S_PC] | |
905 | mov pc, lr | |
906 | .previous | |
907 | ||
49bca4c2 NP |
908 | #else |
909 | #warning "NPTL on non MMU needs fixing" | |
910 | mov r0, #-1 | |
911 | adds r0, r0, #0 | |
ba9b5d76 | 912 | usr_ret lr |
b49c0f24 | 913 | #endif |
2d2669b6 NP |
914 | |
915 | #else | |
916 | ||
ed3768a8 | 917 | smp_dmb arm |
b49c0f24 | 918 | 1: ldrex r3, [r2] |
2d2669b6 NP |
919 | subs r3, r3, r0 |
920 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
921 | teqeq r3, #1 |
922 | beq 1b | |
2d2669b6 | 923 | rsbs r0, r3, #0 |
b49c0f24 | 924 | /* beware -- each __kuser slot must be 8 instructions max */ |
f00ec48f RK |
925 | ALT_SMP(b __kuser_memory_barrier) |
926 | ALT_UP(usr_ret lr) | |
2d2669b6 NP |
927 | |
928 | #endif | |
929 | ||
930 | .align 5 | |
931 | ||
932 | /* | |
933 | * Reference prototype: | |
934 | * | |
935 | * int __kernel_get_tls(void) | |
936 | * | |
937 | * Input: | |
938 | * | |
939 | * lr = return address | |
940 | * | |
941 | * Output: | |
942 | * | |
943 | * r0 = TLS value | |
944 | * | |
945 | * Clobbered: | |
946 | * | |
b49c0f24 | 947 | * none |
2d2669b6 NP |
948 | * |
949 | * Definition and user space usage example: | |
950 | * | |
951 | * typedef int (__kernel_get_tls_t)(void); | |
952 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
953 | * | |
954 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
955 | * | |
956 | * This could be used as follows: | |
957 | * | |
958 | * #define __kernel_get_tls() \ | |
959 | * ({ register unsigned int __val asm("r0"); \ | |
960 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
961 | * : "=r" (__val) : : "lr","cc" ); \ | |
962 | * __val; }) | |
963 | */ | |
964 | ||
965 | __kuser_get_tls: @ 0xffff0fe0 | |
f159f4ed | 966 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
ba9b5d76 | 967 | usr_ret lr |
f159f4ed TL |
968 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
969 | .rep 4 | |
970 | .word 0 @ 0xffff0ff0 software TLS value, then | |
971 | .endr @ pad up to __kuser_helper_version | |
2d2669b6 NP |
972 | |
973 | /* | |
974 | * Reference declaration: | |
975 | * | |
976 | * extern unsigned int __kernel_helper_version; | |
977 | * | |
978 | * Definition and user space usage example: | |
979 | * | |
980 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
981 | * | |
982 | * User space may read this to determine the curent number of helpers | |
983 | * available. | |
984 | */ | |
985 | ||
986 | __kuser_helper_version: @ 0xffff0ffc | |
987 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
988 | ||
989 | .globl __kuser_helper_end | |
990 | __kuser_helper_end: | |
991 | ||
b86040a5 | 992 | THUMB( .thumb ) |
2d2669b6 | 993 | |
1da177e4 LT |
994 | /* |
995 | * Vector stubs. | |
996 | * | |
7933523d RK |
997 | * This code is copied to 0xffff0200 so we can use branches in the |
998 | * vectors, rather than ldr's. Note that this code must not | |
999 | * exceed 0x300 bytes. | |
1da177e4 LT |
1000 | * |
1001 | * Common stub entry macro: | |
1002 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
1003 | * |
1004 | * SP points to a minimal amount of processor-private memory, the address | |
1005 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 1006 | */ |
b7ec4795 | 1007 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
1008 | .align 5 |
1009 | ||
1010 | vector_\name: | |
1da177e4 LT |
1011 | .if \correction |
1012 | sub lr, lr, #\correction | |
1013 | .endif | |
ccea7a19 RK |
1014 | |
1015 | @ | |
1016 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
1017 | @ (parent CPSR) | |
1018 | @ | |
1019 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 1020 | mrs lr, spsr |
ccea7a19 RK |
1021 | str lr, [sp, #8] @ save spsr |
1022 | ||
1da177e4 | 1023 | @ |
ccea7a19 | 1024 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 1025 | @ |
ccea7a19 | 1026 | mrs r0, cpsr |
b86040a5 | 1027 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 1028 | msr spsr_cxsf, r0 |
1da177e4 | 1029 | |
ccea7a19 RK |
1030 | @ |
1031 | @ the branch table must immediately follow this code | |
1032 | @ | |
ccea7a19 | 1033 | and lr, lr, #0x0f |
b86040a5 CM |
1034 | THUMB( adr r0, 1f ) |
1035 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 1036 | mov r0, sp |
b86040a5 | 1037 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 1038 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 1039 | ENDPROC(vector_\name) |
88987ef9 CM |
1040 | |
1041 | .align 2 | |
1042 | @ handler addresses follow this label | |
1043 | 1: | |
1da177e4 LT |
1044 | .endm |
1045 | ||
7933523d | 1046 | .globl __stubs_start |
1da177e4 LT |
1047 | __stubs_start: |
1048 | /* | |
1049 | * Interrupt dispatcher | |
1050 | */ | |
b7ec4795 | 1051 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1052 | |
1053 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1054 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1055 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1056 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1057 | .long __irq_invalid @ 4 | |
1058 | .long __irq_invalid @ 5 | |
1059 | .long __irq_invalid @ 6 | |
1060 | .long __irq_invalid @ 7 | |
1061 | .long __irq_invalid @ 8 | |
1062 | .long __irq_invalid @ 9 | |
1063 | .long __irq_invalid @ a | |
1064 | .long __irq_invalid @ b | |
1065 | .long __irq_invalid @ c | |
1066 | .long __irq_invalid @ d | |
1067 | .long __irq_invalid @ e | |
1068 | .long __irq_invalid @ f | |
1069 | ||
1070 | /* | |
1071 | * Data abort dispatcher | |
1072 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1073 | */ | |
b7ec4795 | 1074 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1075 | |
1076 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1077 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1078 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1079 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1080 | .long __dabt_invalid @ 4 | |
1081 | .long __dabt_invalid @ 5 | |
1082 | .long __dabt_invalid @ 6 | |
1083 | .long __dabt_invalid @ 7 | |
1084 | .long __dabt_invalid @ 8 | |
1085 | .long __dabt_invalid @ 9 | |
1086 | .long __dabt_invalid @ a | |
1087 | .long __dabt_invalid @ b | |
1088 | .long __dabt_invalid @ c | |
1089 | .long __dabt_invalid @ d | |
1090 | .long __dabt_invalid @ e | |
1091 | .long __dabt_invalid @ f | |
1092 | ||
1093 | /* | |
1094 | * Prefetch abort dispatcher | |
1095 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1096 | */ | |
b7ec4795 | 1097 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1098 | |
1099 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1100 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1101 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1102 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1103 | .long __pabt_invalid @ 4 | |
1104 | .long __pabt_invalid @ 5 | |
1105 | .long __pabt_invalid @ 6 | |
1106 | .long __pabt_invalid @ 7 | |
1107 | .long __pabt_invalid @ 8 | |
1108 | .long __pabt_invalid @ 9 | |
1109 | .long __pabt_invalid @ a | |
1110 | .long __pabt_invalid @ b | |
1111 | .long __pabt_invalid @ c | |
1112 | .long __pabt_invalid @ d | |
1113 | .long __pabt_invalid @ e | |
1114 | .long __pabt_invalid @ f | |
1115 | ||
1116 | /* | |
1117 | * Undef instr entry dispatcher | |
1118 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1119 | */ | |
b7ec4795 | 1120 | vector_stub und, UND_MODE |
1da177e4 LT |
1121 | |
1122 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1123 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1124 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1125 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1126 | .long __und_invalid @ 4 | |
1127 | .long __und_invalid @ 5 | |
1128 | .long __und_invalid @ 6 | |
1129 | .long __und_invalid @ 7 | |
1130 | .long __und_invalid @ 8 | |
1131 | .long __und_invalid @ 9 | |
1132 | .long __und_invalid @ a | |
1133 | .long __und_invalid @ b | |
1134 | .long __und_invalid @ c | |
1135 | .long __und_invalid @ d | |
1136 | .long __und_invalid @ e | |
1137 | .long __und_invalid @ f | |
1138 | ||
1139 | .align 5 | |
1140 | ||
1141 | /*============================================================================= | |
1142 | * Undefined FIQs | |
1143 | *----------------------------------------------------------------------------- | |
1144 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1145 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1146 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1147 | * damage alert! I don't think that we can execute any code in here in any | |
1148 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1149 | * get out of that mode without clobbering one register. | |
1150 | */ | |
1151 | vector_fiq: | |
1152 | disable_fiq | |
1153 | subs pc, lr, #4 | |
1154 | ||
1155 | /*============================================================================= | |
1156 | * Address exception handler | |
1157 | *----------------------------------------------------------------------------- | |
1158 | * These aren't too critical. | |
1159 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1160 | */ | |
1161 | ||
1162 | vector_addrexcptn: | |
1163 | b vector_addrexcptn | |
1164 | ||
1165 | /* | |
1166 | * We group all the following data together to optimise | |
1167 | * for CPUs with separate I & D caches. | |
1168 | */ | |
1169 | .align 5 | |
1170 | ||
1171 | .LCvswi: | |
1172 | .word vector_swi | |
1173 | ||
7933523d | 1174 | .globl __stubs_end |
1da177e4 LT |
1175 | __stubs_end: |
1176 | ||
7933523d | 1177 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1178 | |
7933523d RK |
1179 | .globl __vectors_start |
1180 | __vectors_start: | |
b86040a5 CM |
1181 | ARM( swi SYS_ERROR0 ) |
1182 | THUMB( svc #0 ) | |
1183 | THUMB( nop ) | |
1184 | W(b) vector_und + stubs_offset | |
1185 | W(ldr) pc, .LCvswi + stubs_offset | |
1186 | W(b) vector_pabt + stubs_offset | |
1187 | W(b) vector_dabt + stubs_offset | |
1188 | W(b) vector_addrexcptn + stubs_offset | |
1189 | W(b) vector_irq + stubs_offset | |
1190 | W(b) vector_fiq + stubs_offset | |
7933523d RK |
1191 | |
1192 | .globl __vectors_end | |
1193 | __vectors_end: | |
1da177e4 LT |
1194 | |
1195 | .data | |
1196 | ||
1da177e4 LT |
1197 | .globl cr_alignment |
1198 | .globl cr_no_alignment | |
1199 | cr_alignment: | |
1200 | .space 4 | |
1201 | cr_no_alignment: | |
1202 | .space 4 | |
52108641 | 1203 | |
1204 | #ifdef CONFIG_MULTI_IRQ_HANDLER | |
1205 | .globl handle_arch_irq | |
1206 | handle_arch_irq: | |
1207 | .space 4 | |
1208 | #endif |