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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes | |
15 | * it to save wrong values... Be aware! | |
16 | */ | |
17 | #include <linux/config.h> | |
1da177e4 | 18 | |
f09b9979 | 19 | #include <asm/memory.h> |
1da177e4 | 20 | #include <asm/glue.h> |
1da177e4 | 21 | #include <asm/vfpmacros.h> |
bce495d8 | 22 | #include <asm/arch/entry-macro.S> |
d6551e88 | 23 | #include <asm/thread_notify.h> |
1da177e4 LT |
24 | |
25 | #include "entry-header.S" | |
26 | ||
187a51ad RK |
27 | /* |
28 | * Interrupt handling. Preserves r7, r8, r9 | |
29 | */ | |
30 | .macro irq_handler | |
31 | 1: get_irqnr_and_base r0, r6, r5, lr | |
32 | movne r1, sp | |
33 | @ | |
34 | @ routine called with r0 = irq number, r1 = struct pt_regs * | |
35 | @ | |
36 | adrne lr, 1b | |
37 | bne asm_do_IRQ | |
791be9b9 RK |
38 | |
39 | #ifdef CONFIG_SMP | |
40 | /* | |
41 | * XXX | |
42 | * | |
43 | * this macro assumes that irqstat (r6) and base (r5) are | |
44 | * preserved from get_irqnr_and_base above | |
45 | */ | |
46 | test_for_ipi r0, r6, r5, lr | |
47 | movne r0, sp | |
48 | adrne lr, 1b | |
49 | bne do_IPI | |
37ee16ae RK |
50 | |
51 | #ifdef CONFIG_LOCAL_TIMERS | |
52 | test_for_ltirq r0, r6, r5, lr | |
53 | movne r0, sp | |
54 | adrne lr, 1b | |
55 | bne do_local_timer | |
56 | #endif | |
791be9b9 RK |
57 | #endif |
58 | ||
187a51ad RK |
59 | .endm |
60 | ||
1da177e4 LT |
61 | /* |
62 | * Invalid mode handlers | |
63 | */ | |
ccea7a19 RK |
64 | .macro inv_entry, reason |
65 | sub sp, sp, #S_FRAME_SIZE | |
66 | stmib sp, {r1 - lr} | |
1da177e4 LT |
67 | mov r1, #\reason |
68 | .endm | |
69 | ||
70 | __pabt_invalid: | |
ccea7a19 RK |
71 | inv_entry BAD_PREFETCH |
72 | b common_invalid | |
1da177e4 LT |
73 | |
74 | __dabt_invalid: | |
ccea7a19 RK |
75 | inv_entry BAD_DATA |
76 | b common_invalid | |
1da177e4 LT |
77 | |
78 | __irq_invalid: | |
ccea7a19 RK |
79 | inv_entry BAD_IRQ |
80 | b common_invalid | |
1da177e4 LT |
81 | |
82 | __und_invalid: | |
ccea7a19 RK |
83 | inv_entry BAD_UNDEFINSTR |
84 | ||
85 | @ | |
86 | @ XXX fall through to common_invalid | |
87 | @ | |
88 | ||
89 | @ | |
90 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
91 | @ | |
92 | common_invalid: | |
93 | zero_fp | |
94 | ||
95 | ldmia r0, {r4 - r6} | |
96 | add r0, sp, #S_PC @ here for interlock avoidance | |
97 | mov r7, #-1 @ "" "" "" "" | |
98 | str r4, [sp] @ save preserved r0 | |
99 | stmia r0, {r5 - r7} @ lr_<exception>, | |
100 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 101 | |
1da177e4 | 102 | mov r0, sp |
ccea7a19 | 103 | and r2, r6, #0x1f |
1da177e4 LT |
104 | b bad_mode |
105 | ||
106 | /* | |
107 | * SVC mode handlers | |
108 | */ | |
2dede2d8 NP |
109 | |
110 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
111 | #define SPFIX(code...) code | |
112 | #else | |
113 | #define SPFIX(code...) | |
114 | #endif | |
115 | ||
ccea7a19 | 116 | .macro svc_entry |
1da177e4 | 117 | sub sp, sp, #S_FRAME_SIZE |
2dede2d8 NP |
118 | SPFIX( tst sp, #4 ) |
119 | SPFIX( bicne sp, sp, #4 ) | |
ccea7a19 RK |
120 | stmib sp, {r1 - r12} |
121 | ||
122 | ldmia r0, {r1 - r3} | |
123 | add r5, sp, #S_SP @ here for interlock avoidance | |
124 | mov r4, #-1 @ "" "" "" "" | |
125 | add r0, sp, #S_FRAME_SIZE @ "" "" "" "" | |
2dede2d8 | 126 | SPFIX( addne r0, r0, #4 ) |
ccea7a19 RK |
127 | str r1, [sp] @ save the "real" r0 copied |
128 | @ from the exception stack | |
129 | ||
1da177e4 LT |
130 | mov r1, lr |
131 | ||
132 | @ | |
133 | @ We are now ready to fill in the remaining blanks on the stack: | |
134 | @ | |
135 | @ r0 - sp_svc | |
136 | @ r1 - lr_svc | |
137 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
138 | @ r3 - spsr_<exception> | |
139 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
140 | @ | |
141 | stmia r5, {r0 - r4} | |
142 | .endm | |
143 | ||
144 | .align 5 | |
145 | __dabt_svc: | |
ccea7a19 | 146 | svc_entry |
1da177e4 LT |
147 | |
148 | @ | |
149 | @ get ready to re-enable interrupts if appropriate | |
150 | @ | |
151 | mrs r9, cpsr | |
152 | tst r3, #PSR_I_BIT | |
153 | biceq r9, r9, #PSR_I_BIT | |
154 | ||
155 | @ | |
156 | @ Call the processor-specific abort handler: | |
157 | @ | |
158 | @ r2 - aborted context pc | |
159 | @ r3 - aborted context cpsr | |
160 | @ | |
161 | @ The abort handler must return the aborted address in r0, and | |
162 | @ the fault status register in r1. r9 must be preserved. | |
163 | @ | |
164 | #ifdef MULTI_ABORT | |
165 | ldr r4, .LCprocfns | |
166 | mov lr, pc | |
167 | ldr pc, [r4] | |
168 | #else | |
169 | bl CPU_ABORT_HANDLER | |
170 | #endif | |
171 | ||
172 | @ | |
173 | @ set desired IRQ state, then call main handler | |
174 | @ | |
175 | msr cpsr_c, r9 | |
176 | mov r2, sp | |
177 | bl do_DataAbort | |
178 | ||
179 | @ | |
180 | @ IRQs off again before pulling preserved data off the stack | |
181 | @ | |
1ec42c0c | 182 | disable_irq |
1da177e4 LT |
183 | |
184 | @ | |
185 | @ restore SPSR and restart the instruction | |
186 | @ | |
187 | ldr r0, [sp, #S_PSR] | |
188 | msr spsr_cxsf, r0 | |
189 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
190 | ||
191 | .align 5 | |
192 | __irq_svc: | |
ccea7a19 RK |
193 | svc_entry |
194 | ||
1da177e4 | 195 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
196 | get_thread_info tsk |
197 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
198 | add r7, r8, #1 @ increment it | |
199 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 200 | #endif |
ccea7a19 | 201 | |
187a51ad | 202 | irq_handler |
1da177e4 | 203 | #ifdef CONFIG_PREEMPT |
706fdd9f | 204 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
1da177e4 LT |
205 | tst r0, #_TIF_NEED_RESCHED |
206 | blne svc_preempt | |
207 | preempt_return: | |
706fdd9f RK |
208 | ldr r0, [tsk, #TI_PREEMPT] @ read preempt value |
209 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count | |
1da177e4 | 210 | teq r0, r7 |
1da177e4 LT |
211 | strne r0, [r0, -r0] @ bug() |
212 | #endif | |
213 | ldr r0, [sp, #S_PSR] @ irqs are already disabled | |
214 | msr spsr_cxsf, r0 | |
215 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
216 | ||
217 | .ltorg | |
218 | ||
219 | #ifdef CONFIG_PREEMPT | |
220 | svc_preempt: | |
706fdd9f | 221 | teq r8, #0 @ was preempt count = 0 |
1da177e4 LT |
222 | ldreq r6, .LCirq_stat |
223 | movne pc, lr @ no | |
224 | ldr r0, [r6, #4] @ local_irq_count | |
225 | ldr r1, [r6, #8] @ local_bh_count | |
226 | adds r0, r0, r1 | |
227 | movne pc, lr | |
228 | mov r7, #0 @ preempt_schedule_irq | |
706fdd9f | 229 | str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 |
1da177e4 | 230 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 231 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 LT |
232 | tst r0, #_TIF_NEED_RESCHED |
233 | beq preempt_return @ go again | |
234 | b 1b | |
235 | #endif | |
236 | ||
237 | .align 5 | |
238 | __und_svc: | |
ccea7a19 | 239 | svc_entry |
1da177e4 LT |
240 | |
241 | @ | |
242 | @ call emulation code, which returns using r9 if it has emulated | |
243 | @ the instruction, or the more conventional lr if we are to treat | |
244 | @ this as a real undefined instruction | |
245 | @ | |
246 | @ r0 - instruction | |
247 | @ | |
248 | ldr r0, [r2, #-4] | |
249 | adr r9, 1f | |
250 | bl call_fpe | |
251 | ||
252 | mov r0, sp @ struct pt_regs *regs | |
253 | bl do_undefinstr | |
254 | ||
255 | @ | |
256 | @ IRQs off again before pulling preserved data off the stack | |
257 | @ | |
1ec42c0c | 258 | 1: disable_irq |
1da177e4 LT |
259 | |
260 | @ | |
261 | @ restore SPSR and restart the instruction | |
262 | @ | |
263 | ldr lr, [sp, #S_PSR] @ Get SVC cpsr | |
264 | msr spsr_cxsf, lr | |
265 | ldmia sp, {r0 - pc}^ @ Restore SVC registers | |
266 | ||
267 | .align 5 | |
268 | __pabt_svc: | |
ccea7a19 | 269 | svc_entry |
1da177e4 LT |
270 | |
271 | @ | |
272 | @ re-enable interrupts if appropriate | |
273 | @ | |
274 | mrs r9, cpsr | |
275 | tst r3, #PSR_I_BIT | |
276 | biceq r9, r9, #PSR_I_BIT | |
277 | msr cpsr_c, r9 | |
278 | ||
279 | @ | |
280 | @ set args, then call main handler | |
281 | @ | |
282 | @ r0 - address of faulting instruction | |
283 | @ r1 - pointer to registers on stack | |
284 | @ | |
285 | mov r0, r2 @ address (pc) | |
286 | mov r1, sp @ regs | |
287 | bl do_PrefetchAbort @ call abort handler | |
288 | ||
289 | @ | |
290 | @ IRQs off again before pulling preserved data off the stack | |
291 | @ | |
1ec42c0c | 292 | disable_irq |
1da177e4 LT |
293 | |
294 | @ | |
295 | @ restore SPSR and restart the instruction | |
296 | @ | |
297 | ldr r0, [sp, #S_PSR] | |
298 | msr spsr_cxsf, r0 | |
299 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
300 | ||
301 | .align 5 | |
49f680ea RK |
302 | .LCcralign: |
303 | .word cr_alignment | |
1da177e4 LT |
304 | #ifdef MULTI_ABORT |
305 | .LCprocfns: | |
306 | .word processor | |
307 | #endif | |
308 | .LCfp: | |
309 | .word fp_enter | |
310 | #ifdef CONFIG_PREEMPT | |
311 | .LCirq_stat: | |
312 | .word irq_stat | |
313 | #endif | |
314 | ||
315 | /* | |
316 | * User mode handlers | |
2dede2d8 NP |
317 | * |
318 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 319 | */ |
2dede2d8 NP |
320 | |
321 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
322 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
323 | #endif | |
324 | ||
ccea7a19 RK |
325 | .macro usr_entry |
326 | sub sp, sp, #S_FRAME_SIZE | |
327 | stmib sp, {r1 - r12} | |
328 | ||
329 | ldmia r0, {r1 - r3} | |
330 | add r0, sp, #S_PC @ here for interlock avoidance | |
331 | mov r4, #-1 @ "" "" "" "" | |
332 | ||
333 | str r1, [sp] @ save the "real" r0 copied | |
334 | @ from the exception stack | |
1da177e4 | 335 | |
dcef1f63 | 336 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
49bca4c2 NP |
337 | #ifndef CONFIG_MMU |
338 | #warning "NPTL on non MMU needs fixing" | |
339 | #else | |
2d2669b6 | 340 | @ make sure our user space atomic helper is aborted |
f09b9979 | 341 | cmp r2, #TASK_SIZE |
2d2669b6 | 342 | bichs r3, r3, #PSR_Z_BIT |
49bca4c2 | 343 | #endif |
2d2669b6 NP |
344 | #endif |
345 | ||
1da177e4 LT |
346 | @ |
347 | @ We are now ready to fill in the remaining blanks on the stack: | |
348 | @ | |
349 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
350 | @ r3 - spsr_<exception> | |
351 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
352 | @ | |
353 | @ Also, separately save sp_usr and lr_usr | |
354 | @ | |
ccea7a19 RK |
355 | stmia r0, {r2 - r4} |
356 | stmdb r0, {sp, lr}^ | |
1da177e4 LT |
357 | |
358 | @ | |
359 | @ Enable the alignment trap while in kernel mode | |
360 | @ | |
49f680ea | 361 | alignment_trap r0 |
1da177e4 LT |
362 | |
363 | @ | |
364 | @ Clear FP to mark the first stack frame | |
365 | @ | |
366 | zero_fp | |
367 | .endm | |
368 | ||
369 | .align 5 | |
370 | __dabt_usr: | |
ccea7a19 | 371 | usr_entry |
1da177e4 LT |
372 | |
373 | @ | |
374 | @ Call the processor-specific abort handler: | |
375 | @ | |
376 | @ r2 - aborted context pc | |
377 | @ r3 - aborted context cpsr | |
378 | @ | |
379 | @ The abort handler must return the aborted address in r0, and | |
380 | @ the fault status register in r1. | |
381 | @ | |
382 | #ifdef MULTI_ABORT | |
383 | ldr r4, .LCprocfns | |
384 | mov lr, pc | |
385 | ldr pc, [r4] | |
386 | #else | |
387 | bl CPU_ABORT_HANDLER | |
388 | #endif | |
389 | ||
390 | @ | |
391 | @ IRQs on, then call the main handler | |
392 | @ | |
1ec42c0c | 393 | enable_irq |
1da177e4 LT |
394 | mov r2, sp |
395 | adr lr, ret_from_exception | |
396 | b do_DataAbort | |
397 | ||
398 | .align 5 | |
399 | __irq_usr: | |
ccea7a19 | 400 | usr_entry |
1da177e4 | 401 | |
706fdd9f | 402 | get_thread_info tsk |
1da177e4 | 403 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
404 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
405 | add r7, r8, #1 @ increment it | |
406 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 407 | #endif |
ccea7a19 | 408 | |
187a51ad | 409 | irq_handler |
1da177e4 | 410 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
411 | ldr r0, [tsk, #TI_PREEMPT] |
412 | str r8, [tsk, #TI_PREEMPT] | |
1da177e4 | 413 | teq r0, r7 |
1da177e4 | 414 | strne r0, [r0, -r0] |
1da177e4 | 415 | #endif |
ccea7a19 | 416 | |
1da177e4 LT |
417 | mov why, #0 |
418 | b ret_to_user | |
419 | ||
420 | .ltorg | |
421 | ||
422 | .align 5 | |
423 | __und_usr: | |
ccea7a19 | 424 | usr_entry |
1da177e4 LT |
425 | |
426 | tst r3, #PSR_T_BIT @ Thumb mode? | |
427 | bne fpundefinstr @ ignore FP | |
428 | sub r4, r2, #4 | |
429 | ||
430 | @ | |
431 | @ fall through to the emulation code, which returns using r9 if | |
432 | @ it has emulated the instruction, or the more conventional lr | |
433 | @ if we are to treat this as a real undefined instruction | |
434 | @ | |
435 | @ r0 - instruction | |
436 | @ | |
437 | 1: ldrt r0, [r4] | |
438 | adr r9, ret_from_exception | |
439 | adr lr, fpundefinstr | |
440 | @ | |
441 | @ fallthrough to call_fpe | |
442 | @ | |
443 | ||
444 | /* | |
445 | * The out of line fixup for the ldrt above. | |
446 | */ | |
447 | .section .fixup, "ax" | |
448 | 2: mov pc, r9 | |
449 | .previous | |
450 | .section __ex_table,"a" | |
451 | .long 1b, 2b | |
452 | .previous | |
453 | ||
454 | /* | |
455 | * Check whether the instruction is a co-processor instruction. | |
456 | * If yes, we need to call the relevant co-processor handler. | |
457 | * | |
458 | * Note that we don't do a full check here for the co-processor | |
459 | * instructions; all instructions with bit 27 set are well | |
460 | * defined. The only instructions that should fault are the | |
461 | * co-processor instructions. However, we have to watch out | |
462 | * for the ARM6/ARM7 SWI bug. | |
463 | * | |
464 | * Emulators may wish to make use of the following registers: | |
465 | * r0 = instruction opcode. | |
466 | * r2 = PC+4 | |
467 | * r10 = this threads thread_info structure. | |
468 | */ | |
469 | call_fpe: | |
470 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 | |
471 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) | |
472 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
473 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
474 | #endif | |
475 | moveq pc, lr | |
476 | get_thread_info r10 @ get current thread | |
477 | and r8, r0, #0x00000f00 @ mask out CP number | |
478 | mov r7, #1 | |
479 | add r6, r10, #TI_USED_CP | |
480 | strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] | |
481 | #ifdef CONFIG_IWMMXT | |
482 | @ Test if we need to give access to iWMMXt coprocessors | |
483 | ldr r5, [r10, #TI_FLAGS] | |
484 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
485 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
486 | bcs iwmmxt_task_enable | |
487 | #endif | |
1da177e4 LT |
488 | add pc, pc, r8, lsr #6 |
489 | mov r0, r0 | |
490 | ||
491 | mov pc, lr @ CP#0 | |
492 | b do_fpe @ CP#1 (FPE) | |
493 | b do_fpe @ CP#2 (FPE) | |
494 | mov pc, lr @ CP#3 | |
495 | mov pc, lr @ CP#4 | |
496 | mov pc, lr @ CP#5 | |
497 | mov pc, lr @ CP#6 | |
498 | mov pc, lr @ CP#7 | |
499 | mov pc, lr @ CP#8 | |
500 | mov pc, lr @ CP#9 | |
501 | #ifdef CONFIG_VFP | |
502 | b do_vfp @ CP#10 (VFP) | |
503 | b do_vfp @ CP#11 (VFP) | |
504 | #else | |
505 | mov pc, lr @ CP#10 (VFP) | |
506 | mov pc, lr @ CP#11 (VFP) | |
507 | #endif | |
508 | mov pc, lr @ CP#12 | |
509 | mov pc, lr @ CP#13 | |
510 | mov pc, lr @ CP#14 (Debug) | |
511 | mov pc, lr @ CP#15 (Control) | |
512 | ||
513 | do_fpe: | |
5d25ac03 | 514 | enable_irq |
1da177e4 LT |
515 | ldr r4, .LCfp |
516 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
517 | ldr pc, [r4] @ Call FP module USR entry point | |
518 | ||
519 | /* | |
520 | * The FP module is called with these registers set: | |
521 | * r0 = instruction | |
522 | * r2 = PC+4 | |
523 | * r9 = normal "successful" return address | |
524 | * r10 = FP workspace | |
525 | * lr = unrecognised FP instruction return address | |
526 | */ | |
527 | ||
528 | .data | |
529 | ENTRY(fp_enter) | |
530 | .word fpundefinstr | |
531 | .text | |
532 | ||
533 | fpundefinstr: | |
534 | mov r0, sp | |
535 | adr lr, ret_from_exception | |
536 | b do_undefinstr | |
537 | ||
538 | .align 5 | |
539 | __pabt_usr: | |
ccea7a19 | 540 | usr_entry |
1da177e4 | 541 | |
1ec42c0c | 542 | enable_irq @ Enable interrupts |
1da177e4 LT |
543 | mov r0, r2 @ address (pc) |
544 | mov r1, sp @ regs | |
545 | bl do_PrefetchAbort @ call abort handler | |
546 | /* fall through */ | |
547 | /* | |
548 | * This is the return code to user mode for abort handlers | |
549 | */ | |
550 | ENTRY(ret_from_exception) | |
551 | get_thread_info tsk | |
552 | mov why, #0 | |
553 | b ret_to_user | |
554 | ||
555 | /* | |
556 | * Register switch for ARMv3 and ARMv4 processors | |
557 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
558 | * previous and next are guaranteed not to be the same. | |
559 | */ | |
560 | ENTRY(__switch_to) | |
561 | add ip, r1, #TI_CPU_SAVE | |
562 | ldr r3, [r2, #TI_TP_VALUE] | |
563 | stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack | |
d6551e88 RK |
564 | #ifdef CONFIG_MMU |
565 | ldr r6, [r2, #TI_CPU_DOMAIN] | |
afeb90ca | 566 | #endif |
b876386e | 567 | #if __LINUX_ARM_ARCH__ >= 6 |
43cc1981 | 568 | #ifdef CONFIG_CPU_32v6K |
b876386e RK |
569 | clrex |
570 | #else | |
73394322 | 571 | strex r5, r4, [ip] @ Clear exclusive monitor |
b876386e RK |
572 | #endif |
573 | #endif | |
1da177e4 LT |
574 | #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT) |
575 | mra r4, r5, acc0 | |
576 | stmia ip, {r4, r5} | |
577 | #endif | |
4b0e07a5 | 578 | #if defined(CONFIG_HAS_TLS_REG) |
2d2669b6 | 579 | mcr p15, 0, r3, c13, c0, 3 @ set TLS register |
4b0e07a5 | 580 | #elif !defined(CONFIG_TLS_REG_EMUL) |
1da177e4 | 581 | mov r4, #0xffff0fff |
2d2669b6 NP |
582 | str r3, [r4, #-15] @ TLS val at 0xffff0ff0 |
583 | #endif | |
afeb90ca | 584 | #ifdef CONFIG_MMU |
1da177e4 | 585 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
afeb90ca | 586 | #endif |
1da177e4 LT |
587 | #if defined(CONFIG_IWMMXT) |
588 | bl iwmmxt_task_switch | |
589 | #elif defined(CONFIG_CPU_XSCALE) | |
d6551e88 | 590 | add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra |
1da177e4 LT |
591 | ldmib r4, {r4, r5} |
592 | mar acc0, r4, r5 | |
593 | #endif | |
d6551e88 RK |
594 | mov r5, r0 |
595 | add r4, r2, #TI_CPU_SAVE | |
596 | ldr r0, =thread_notify_head | |
597 | mov r1, #THREAD_NOTIFY_SWITCH | |
598 | bl atomic_notifier_call_chain | |
599 | mov r0, r5 | |
600 | ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously | |
1da177e4 LT |
601 | |
602 | __INIT | |
2d2669b6 NP |
603 | |
604 | /* | |
605 | * User helpers. | |
606 | * | |
607 | * These are segment of kernel provided user code reachable from user space | |
608 | * at a fixed address in kernel memory. This is used to provide user space | |
609 | * with some operations which require kernel help because of unimplemented | |
610 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
611 | * this code to be executed directly in user mode for best efficiency but | |
612 | * which is too intimate with the kernel counter part to be left to user | |
613 | * libraries. In fact this code might even differ from one CPU to another | |
614 | * depending on the available instruction set and restrictions like on | |
615 | * SMP systems. In other words, the kernel reserves the right to change | |
616 | * this code as needed without warning. Only the entry points and their | |
617 | * results are guaranteed to be stable. | |
618 | * | |
619 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
620 | * vector page. New segments (if ever needed) must be added in front of | |
621 | * existing ones. This mechanism should be used only for things that are | |
622 | * really small and justified, and not be abused freely. | |
623 | * | |
624 | * User space is expected to implement those things inline when optimizing | |
625 | * for a processor that has the necessary native support, but only if such | |
626 | * resulting binaries are already to be incompatible with earlier ARM | |
627 | * processors due to the use of unsupported instructions other than what | |
628 | * is provided here. In other words don't make binaries unable to run on | |
629 | * earlier processors just for the sake of not using these kernel helpers | |
630 | * if your compiled code is not going to use the new instructions for other | |
631 | * purpose. | |
632 | */ | |
633 | ||
634 | .align 5 | |
635 | .globl __kuser_helper_start | |
636 | __kuser_helper_start: | |
637 | ||
7c612bfd NP |
638 | /* |
639 | * Reference prototype: | |
640 | * | |
641 | * void __kernel_memory_barrier(void) | |
642 | * | |
643 | * Input: | |
644 | * | |
645 | * lr = return address | |
646 | * | |
647 | * Output: | |
648 | * | |
649 | * none | |
650 | * | |
651 | * Clobbered: | |
652 | * | |
653 | * the Z flag might be lost | |
654 | * | |
655 | * Definition and user space usage example: | |
656 | * | |
657 | * typedef void (__kernel_dmb_t)(void); | |
658 | * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) | |
659 | * | |
660 | * Apply any needed memory barrier to preserve consistency with data modified | |
661 | * manually and __kuser_cmpxchg usage. | |
662 | * | |
663 | * This could be used as follows: | |
664 | * | |
665 | * #define __kernel_dmb() \ | |
666 | * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ | |
6896eec0 | 667 | * : : : "r0", "lr","cc" ) |
7c612bfd NP |
668 | */ |
669 | ||
670 | __kuser_memory_barrier: @ 0xffff0fa0 | |
671 | ||
672 | #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) | |
673 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
674 | #endif | |
675 | mov pc, lr | |
676 | ||
677 | .align 5 | |
678 | ||
2d2669b6 NP |
679 | /* |
680 | * Reference prototype: | |
681 | * | |
682 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
683 | * | |
684 | * Input: | |
685 | * | |
686 | * r0 = oldval | |
687 | * r1 = newval | |
688 | * r2 = ptr | |
689 | * lr = return address | |
690 | * | |
691 | * Output: | |
692 | * | |
693 | * r0 = returned value (zero or non-zero) | |
694 | * C flag = set if r0 == 0, clear if r0 != 0 | |
695 | * | |
696 | * Clobbered: | |
697 | * | |
698 | * r3, ip, flags | |
699 | * | |
700 | * Definition and user space usage example: | |
701 | * | |
702 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
703 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
704 | * | |
705 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
706 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
707 | * The C flag is also set if *ptr was changed to allow for assembly | |
708 | * optimization in the calling code. | |
709 | * | |
5964eae8 NP |
710 | * Notes: |
711 | * | |
712 | * - This routine already includes memory barriers as needed. | |
713 | * | |
714 | * - A failure might be transient, i.e. it is possible, although unlikely, | |
715 | * that "failure" be returned even if *ptr == oldval. | |
7c612bfd | 716 | * |
2d2669b6 NP |
717 | * For example, a user space atomic_add implementation could look like this: |
718 | * | |
719 | * #define atomic_add(ptr, val) \ | |
720 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
721 | * register unsigned int __result asm("r1"); \ | |
722 | * asm volatile ( \ | |
723 | * "1: @ atomic_add\n\t" \ | |
724 | * "ldr r0, [r2]\n\t" \ | |
725 | * "mov r3, #0xffff0fff\n\t" \ | |
726 | * "add lr, pc, #4\n\t" \ | |
727 | * "add r1, r0, %2\n\t" \ | |
728 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
729 | * "bcc 1b" \ | |
730 | * : "=&r" (__result) \ | |
731 | * : "r" (__ptr), "rIL" (val) \ | |
732 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
733 | * __result; }) | |
734 | */ | |
735 | ||
736 | __kuser_cmpxchg: @ 0xffff0fc0 | |
737 | ||
dcef1f63 | 738 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 739 | |
dcef1f63 NP |
740 | /* |
741 | * Poor you. No fast solution possible... | |
742 | * The kernel itself must perform the operation. | |
743 | * A special ghost syscall is used for that (see traps.c). | |
744 | */ | |
5e097445 NP |
745 | stmfd sp!, {r7, lr} |
746 | mov r7, #0xff00 @ 0xfff0 into r7 for EABI | |
747 | orr r7, r7, #0xf0 | |
dcef1f63 | 748 | swi #0x9ffff0 |
5e097445 | 749 | ldmfd sp!, {r7, pc} |
dcef1f63 NP |
750 | |
751 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 NP |
752 | |
753 | /* | |
754 | * Theory of operation: | |
755 | * | |
756 | * We set the Z flag before loading oldval. If ever an exception | |
757 | * occurs we can not be sure the loaded value will still be the same | |
758 | * when the exception returns, therefore the user exception handler | |
759 | * will clear the Z flag whenever the interrupted user code was | |
760 | * actually from the kernel address space (see the usr_entry macro). | |
761 | * | |
762 | * The post-increment on the str is used to prevent a race with an | |
763 | * exception happening just after the str instruction which would | |
764 | * clear the Z flag although the exchange was done. | |
765 | */ | |
49bca4c2 | 766 | #ifdef CONFIG_MMU |
2d2669b6 NP |
767 | teq ip, ip @ set Z flag |
768 | ldr ip, [r2] @ load current val | |
769 | add r3, r2, #1 @ prepare store ptr | |
770 | teqeq ip, r0 @ compare with oldval if still allowed | |
771 | streq r1, [r3, #-1]! @ store newval if still allowed | |
772 | subs r0, r2, r3 @ if r2 == r3 the str occured | |
49bca4c2 NP |
773 | #else |
774 | #warning "NPTL on non MMU needs fixing" | |
775 | mov r0, #-1 | |
776 | adds r0, r0, #0 | |
777 | #endif | |
2d2669b6 NP |
778 | mov pc, lr |
779 | ||
780 | #else | |
781 | ||
7c612bfd NP |
782 | #ifdef CONFIG_SMP |
783 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
784 | #endif | |
2d2669b6 NP |
785 | ldrex r3, [r2] |
786 | subs r3, r3, r0 | |
787 | strexeq r3, r1, [r2] | |
788 | rsbs r0, r3, #0 | |
7c612bfd NP |
789 | #ifdef CONFIG_SMP |
790 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
791 | #endif | |
2d2669b6 NP |
792 | mov pc, lr |
793 | ||
794 | #endif | |
795 | ||
796 | .align 5 | |
797 | ||
798 | /* | |
799 | * Reference prototype: | |
800 | * | |
801 | * int __kernel_get_tls(void) | |
802 | * | |
803 | * Input: | |
804 | * | |
805 | * lr = return address | |
806 | * | |
807 | * Output: | |
808 | * | |
809 | * r0 = TLS value | |
810 | * | |
811 | * Clobbered: | |
812 | * | |
813 | * the Z flag might be lost | |
814 | * | |
815 | * Definition and user space usage example: | |
816 | * | |
817 | * typedef int (__kernel_get_tls_t)(void); | |
818 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
819 | * | |
820 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
821 | * | |
822 | * This could be used as follows: | |
823 | * | |
824 | * #define __kernel_get_tls() \ | |
825 | * ({ register unsigned int __val asm("r0"); \ | |
826 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
827 | * : "=r" (__val) : : "lr","cc" ); \ | |
828 | * __val; }) | |
829 | */ | |
830 | ||
831 | __kuser_get_tls: @ 0xffff0fe0 | |
832 | ||
4b0e07a5 | 833 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) |
2d2669b6 NP |
834 | |
835 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 | |
836 | mov pc, lr | |
837 | ||
838 | #else | |
839 | ||
840 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register | |
841 | mov pc, lr | |
842 | ||
843 | #endif | |
844 | ||
845 | .rep 5 | |
846 | .word 0 @ pad up to __kuser_helper_version | |
847 | .endr | |
848 | ||
849 | /* | |
850 | * Reference declaration: | |
851 | * | |
852 | * extern unsigned int __kernel_helper_version; | |
853 | * | |
854 | * Definition and user space usage example: | |
855 | * | |
856 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
857 | * | |
858 | * User space may read this to determine the curent number of helpers | |
859 | * available. | |
860 | */ | |
861 | ||
862 | __kuser_helper_version: @ 0xffff0ffc | |
863 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
864 | ||
865 | .globl __kuser_helper_end | |
866 | __kuser_helper_end: | |
867 | ||
868 | ||
1da177e4 LT |
869 | /* |
870 | * Vector stubs. | |
871 | * | |
7933523d RK |
872 | * This code is copied to 0xffff0200 so we can use branches in the |
873 | * vectors, rather than ldr's. Note that this code must not | |
874 | * exceed 0x300 bytes. | |
1da177e4 LT |
875 | * |
876 | * Common stub entry macro: | |
877 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
878 | * |
879 | * SP points to a minimal amount of processor-private memory, the address | |
880 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 881 | */ |
b7ec4795 | 882 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
883 | .align 5 |
884 | ||
885 | vector_\name: | |
1da177e4 LT |
886 | .if \correction |
887 | sub lr, lr, #\correction | |
888 | .endif | |
ccea7a19 RK |
889 | |
890 | @ | |
891 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
892 | @ (parent CPSR) | |
893 | @ | |
894 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 895 | mrs lr, spsr |
ccea7a19 RK |
896 | str lr, [sp, #8] @ save spsr |
897 | ||
1da177e4 | 898 | @ |
ccea7a19 | 899 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 900 | @ |
ccea7a19 | 901 | mrs r0, cpsr |
b7ec4795 | 902 | eor r0, r0, #(\mode ^ SVC_MODE) |
ccea7a19 | 903 | msr spsr_cxsf, r0 |
1da177e4 | 904 | |
ccea7a19 RK |
905 | @ |
906 | @ the branch table must immediately follow this code | |
907 | @ | |
ccea7a19 | 908 | and lr, lr, #0x0f |
b7ec4795 | 909 | mov r0, sp |
1da177e4 | 910 | ldr lr, [pc, lr, lsl #2] |
ccea7a19 | 911 | movs pc, lr @ branch to handler in SVC mode |
1da177e4 LT |
912 | .endm |
913 | ||
7933523d | 914 | .globl __stubs_start |
1da177e4 LT |
915 | __stubs_start: |
916 | /* | |
917 | * Interrupt dispatcher | |
918 | */ | |
b7ec4795 | 919 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
920 | |
921 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
922 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
923 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
924 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
925 | .long __irq_invalid @ 4 | |
926 | .long __irq_invalid @ 5 | |
927 | .long __irq_invalid @ 6 | |
928 | .long __irq_invalid @ 7 | |
929 | .long __irq_invalid @ 8 | |
930 | .long __irq_invalid @ 9 | |
931 | .long __irq_invalid @ a | |
932 | .long __irq_invalid @ b | |
933 | .long __irq_invalid @ c | |
934 | .long __irq_invalid @ d | |
935 | .long __irq_invalid @ e | |
936 | .long __irq_invalid @ f | |
937 | ||
938 | /* | |
939 | * Data abort dispatcher | |
940 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
941 | */ | |
b7ec4795 | 942 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
943 | |
944 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
945 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
946 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
947 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
948 | .long __dabt_invalid @ 4 | |
949 | .long __dabt_invalid @ 5 | |
950 | .long __dabt_invalid @ 6 | |
951 | .long __dabt_invalid @ 7 | |
952 | .long __dabt_invalid @ 8 | |
953 | .long __dabt_invalid @ 9 | |
954 | .long __dabt_invalid @ a | |
955 | .long __dabt_invalid @ b | |
956 | .long __dabt_invalid @ c | |
957 | .long __dabt_invalid @ d | |
958 | .long __dabt_invalid @ e | |
959 | .long __dabt_invalid @ f | |
960 | ||
961 | /* | |
962 | * Prefetch abort dispatcher | |
963 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
964 | */ | |
b7ec4795 | 965 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
966 | |
967 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
968 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
969 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
970 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
971 | .long __pabt_invalid @ 4 | |
972 | .long __pabt_invalid @ 5 | |
973 | .long __pabt_invalid @ 6 | |
974 | .long __pabt_invalid @ 7 | |
975 | .long __pabt_invalid @ 8 | |
976 | .long __pabt_invalid @ 9 | |
977 | .long __pabt_invalid @ a | |
978 | .long __pabt_invalid @ b | |
979 | .long __pabt_invalid @ c | |
980 | .long __pabt_invalid @ d | |
981 | .long __pabt_invalid @ e | |
982 | .long __pabt_invalid @ f | |
983 | ||
984 | /* | |
985 | * Undef instr entry dispatcher | |
986 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
987 | */ | |
b7ec4795 | 988 | vector_stub und, UND_MODE |
1da177e4 LT |
989 | |
990 | .long __und_usr @ 0 (USR_26 / USR_32) | |
991 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
992 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
993 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
994 | .long __und_invalid @ 4 | |
995 | .long __und_invalid @ 5 | |
996 | .long __und_invalid @ 6 | |
997 | .long __und_invalid @ 7 | |
998 | .long __und_invalid @ 8 | |
999 | .long __und_invalid @ 9 | |
1000 | .long __und_invalid @ a | |
1001 | .long __und_invalid @ b | |
1002 | .long __und_invalid @ c | |
1003 | .long __und_invalid @ d | |
1004 | .long __und_invalid @ e | |
1005 | .long __und_invalid @ f | |
1006 | ||
1007 | .align 5 | |
1008 | ||
1009 | /*============================================================================= | |
1010 | * Undefined FIQs | |
1011 | *----------------------------------------------------------------------------- | |
1012 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1013 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1014 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1015 | * damage alert! I don't think that we can execute any code in here in any | |
1016 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1017 | * get out of that mode without clobbering one register. | |
1018 | */ | |
1019 | vector_fiq: | |
1020 | disable_fiq | |
1021 | subs pc, lr, #4 | |
1022 | ||
1023 | /*============================================================================= | |
1024 | * Address exception handler | |
1025 | *----------------------------------------------------------------------------- | |
1026 | * These aren't too critical. | |
1027 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1028 | */ | |
1029 | ||
1030 | vector_addrexcptn: | |
1031 | b vector_addrexcptn | |
1032 | ||
1033 | /* | |
1034 | * We group all the following data together to optimise | |
1035 | * for CPUs with separate I & D caches. | |
1036 | */ | |
1037 | .align 5 | |
1038 | ||
1039 | .LCvswi: | |
1040 | .word vector_swi | |
1041 | ||
7933523d | 1042 | .globl __stubs_end |
1da177e4 LT |
1043 | __stubs_end: |
1044 | ||
7933523d | 1045 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1046 | |
7933523d RK |
1047 | .globl __vectors_start |
1048 | __vectors_start: | |
1da177e4 | 1049 | swi SYS_ERROR0 |
7933523d RK |
1050 | b vector_und + stubs_offset |
1051 | ldr pc, .LCvswi + stubs_offset | |
1052 | b vector_pabt + stubs_offset | |
1053 | b vector_dabt + stubs_offset | |
1054 | b vector_addrexcptn + stubs_offset | |
1055 | b vector_irq + stubs_offset | |
1056 | b vector_fiq + stubs_offset | |
1057 | ||
1058 | .globl __vectors_end | |
1059 | __vectors_end: | |
1da177e4 LT |
1060 | |
1061 | .data | |
1062 | ||
1da177e4 LT |
1063 | .globl cr_alignment |
1064 | .globl cr_no_alignment | |
1065 | cr_alignment: | |
1066 | .space 4 | |
1067 | cr_no_alignment: | |
1068 | .space 4 |