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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
f09b9979 | 18 | #include <asm/memory.h> |
753790e7 RK |
19 | #include <asm/glue-df.h> |
20 | #include <asm/glue-pf.h> | |
1da177e4 | 21 | #include <asm/vfpmacros.h> |
243c8654 | 22 | #ifndef CONFIG_MULTI_IRQ_HANDLER |
a09e64fb | 23 | #include <mach/entry-macro.S> |
243c8654 | 24 | #endif |
d6551e88 | 25 | #include <asm/thread_notify.h> |
c4c5716e | 26 | #include <asm/unwind.h> |
cc20d429 | 27 | #include <asm/unistd.h> |
f159f4ed | 28 | #include <asm/tls.h> |
ef4c5368 | 29 | #include <asm/system.h> |
1da177e4 LT |
30 | |
31 | #include "entry-header.S" | |
cd544ce7 | 32 | #include <asm/entry-macro-multi.S> |
1da177e4 | 33 | |
187a51ad | 34 | /* |
d9600c99 | 35 | * Interrupt handling. |
187a51ad RK |
36 | */ |
37 | .macro irq_handler | |
52108641 | 38 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
d9600c99 | 39 | ldr r1, =handle_arch_irq |
52108641 | 40 | mov r0, sp |
52108641 | 41 | adr lr, BSYM(9997f) |
abeb24ae MZ |
42 | ldr pc, [r1] |
43 | #else | |
cd544ce7 | 44 | arch_irq_handler_default |
abeb24ae | 45 | #endif |
f00ec48f | 46 | 9997: |
187a51ad RK |
47 | .endm |
48 | ||
ac8b9c1c | 49 | .macro pabt_helper |
8dfe7ac9 | 50 | @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 |
ac8b9c1c | 51 | #ifdef MULTI_PABORT |
0402bece | 52 | ldr ip, .LCprocfns |
ac8b9c1c | 53 | mov lr, pc |
0402bece | 54 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
ac8b9c1c RK |
55 | #else |
56 | bl CPU_PABORT_HANDLER | |
57 | #endif | |
58 | .endm | |
59 | ||
60 | .macro dabt_helper | |
61 | ||
62 | @ | |
63 | @ Call the processor-specific abort handler: | |
64 | @ | |
da740472 | 65 | @ r2 - pt_regs |
3e287bec RK |
66 | @ r4 - aborted context pc |
67 | @ r5 - aborted context psr | |
ac8b9c1c RK |
68 | @ |
69 | @ The abort handler must return the aborted address in r0, and | |
70 | @ the fault status register in r1. r9 must be preserved. | |
71 | @ | |
72 | #ifdef MULTI_DABORT | |
0402bece | 73 | ldr ip, .LCprocfns |
ac8b9c1c | 74 | mov lr, pc |
0402bece | 75 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
ac8b9c1c RK |
76 | #else |
77 | bl CPU_DABORT_HANDLER | |
78 | #endif | |
79 | .endm | |
80 | ||
785d3cd2 NP |
81 | #ifdef CONFIG_KPROBES |
82 | .section .kprobes.text,"ax",%progbits | |
83 | #else | |
84 | .text | |
85 | #endif | |
86 | ||
1da177e4 LT |
87 | /* |
88 | * Invalid mode handlers | |
89 | */ | |
ccea7a19 RK |
90 | .macro inv_entry, reason |
91 | sub sp, sp, #S_FRAME_SIZE | |
b86040a5 CM |
92 | ARM( stmib sp, {r1 - lr} ) |
93 | THUMB( stmia sp, {r0 - r12} ) | |
94 | THUMB( str sp, [sp, #S_SP] ) | |
95 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
96 | mov r1, #\reason |
97 | .endm | |
98 | ||
99 | __pabt_invalid: | |
ccea7a19 RK |
100 | inv_entry BAD_PREFETCH |
101 | b common_invalid | |
93ed3970 | 102 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
103 | |
104 | __dabt_invalid: | |
ccea7a19 RK |
105 | inv_entry BAD_DATA |
106 | b common_invalid | |
93ed3970 | 107 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
108 | |
109 | __irq_invalid: | |
ccea7a19 RK |
110 | inv_entry BAD_IRQ |
111 | b common_invalid | |
93ed3970 | 112 | ENDPROC(__irq_invalid) |
1da177e4 LT |
113 | |
114 | __und_invalid: | |
ccea7a19 RK |
115 | inv_entry BAD_UNDEFINSTR |
116 | ||
117 | @ | |
118 | @ XXX fall through to common_invalid | |
119 | @ | |
120 | ||
121 | @ | |
122 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
123 | @ | |
124 | common_invalid: | |
125 | zero_fp | |
126 | ||
127 | ldmia r0, {r4 - r6} | |
128 | add r0, sp, #S_PC @ here for interlock avoidance | |
129 | mov r7, #-1 @ "" "" "" "" | |
130 | str r4, [sp] @ save preserved r0 | |
131 | stmia r0, {r5 - r7} @ lr_<exception>, | |
132 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 133 | |
1da177e4 | 134 | mov r0, sp |
1da177e4 | 135 | b bad_mode |
93ed3970 | 136 | ENDPROC(__und_invalid) |
1da177e4 LT |
137 | |
138 | /* | |
139 | * SVC mode handlers | |
140 | */ | |
2dede2d8 NP |
141 | |
142 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
143 | #define SPFIX(code...) code | |
144 | #else | |
145 | #define SPFIX(code...) | |
146 | #endif | |
147 | ||
d30a0c8b | 148 | .macro svc_entry, stack_hole=0 |
c4c5716e CM |
149 | UNWIND(.fnstart ) |
150 | UNWIND(.save {r0 - pc} ) | |
b86040a5 CM |
151 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
152 | #ifdef CONFIG_THUMB2_KERNEL | |
153 | SPFIX( str r0, [sp] ) @ temporarily saved | |
154 | SPFIX( mov r0, sp ) | |
155 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
156 | SPFIX( ldr r0, [sp] ) @ restored | |
157 | #else | |
2dede2d8 | 158 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
159 | #endif |
160 | SPFIX( subeq sp, sp, #4 ) | |
161 | stmia sp, {r1 - r12} | |
ccea7a19 | 162 | |
b059bdc3 RK |
163 | ldmia r0, {r3 - r5} |
164 | add r7, sp, #S_SP - 4 @ here for interlock avoidance | |
165 | mov r6, #-1 @ "" "" "" "" | |
166 | add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) | |
167 | SPFIX( addeq r2, r2, #4 ) | |
168 | str r3, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
169 | @ from the exception stack |
170 | ||
b059bdc3 | 171 | mov r3, lr |
1da177e4 LT |
172 | |
173 | @ | |
174 | @ We are now ready to fill in the remaining blanks on the stack: | |
175 | @ | |
b059bdc3 RK |
176 | @ r2 - sp_svc |
177 | @ r3 - lr_svc | |
178 | @ r4 - lr_<exception>, already fixed up for correct return/restart | |
179 | @ r5 - spsr_<exception> | |
180 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 | 181 | @ |
b059bdc3 | 182 | stmia r7, {r2 - r6} |
1da177e4 | 183 | |
02fe2845 RK |
184 | #ifdef CONFIG_TRACE_IRQFLAGS |
185 | bl trace_hardirqs_off | |
186 | #endif | |
f2741b78 | 187 | .endm |
1da177e4 | 188 | |
f2741b78 RK |
189 | .align 5 |
190 | __dabt_svc: | |
191 | svc_entry | |
1da177e4 | 192 | mov r2, sp |
da740472 | 193 | dabt_helper |
1da177e4 LT |
194 | |
195 | @ | |
196 | @ IRQs off again before pulling preserved data off the stack | |
197 | @ | |
ac78884e | 198 | disable_irq_notrace |
1da177e4 | 199 | |
02fe2845 RK |
200 | #ifdef CONFIG_TRACE_IRQFLAGS |
201 | tst r5, #PSR_I_BIT | |
202 | bleq trace_hardirqs_on | |
203 | tst r5, #PSR_I_BIT | |
204 | blne trace_hardirqs_off | |
205 | #endif | |
b059bdc3 | 206 | svc_exit r5 @ return from exception |
c4c5716e | 207 | UNWIND(.fnend ) |
93ed3970 | 208 | ENDPROC(__dabt_svc) |
1da177e4 LT |
209 | |
210 | .align 5 | |
211 | __irq_svc: | |
ccea7a19 | 212 | svc_entry |
187a51ad | 213 | irq_handler |
1613cc11 | 214 | |
1da177e4 | 215 | #ifdef CONFIG_PREEMPT |
1613cc11 RK |
216 | get_thread_info tsk |
217 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
706fdd9f | 218 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
219 | teq r8, #0 @ if preempt count != 0 |
220 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
221 | tst r0, #_TIF_NEED_RESCHED |
222 | blne svc_preempt | |
1da177e4 | 223 | #endif |
30891c90 | 224 | |
7ad1bcb2 | 225 | #ifdef CONFIG_TRACE_IRQFLAGS |
fbab1c80 RK |
226 | @ The parent context IRQs must have been enabled to get here in |
227 | @ the first place, so there's no point checking the PSR I bit. | |
228 | bl trace_hardirqs_on | |
7ad1bcb2 | 229 | #endif |
b059bdc3 | 230 | svc_exit r5 @ return from exception |
c4c5716e | 231 | UNWIND(.fnend ) |
93ed3970 | 232 | ENDPROC(__irq_svc) |
1da177e4 LT |
233 | |
234 | .ltorg | |
235 | ||
236 | #ifdef CONFIG_PREEMPT | |
237 | svc_preempt: | |
28fab1a2 | 238 | mov r8, lr |
1da177e4 | 239 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 240 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 241 | tst r0, #_TIF_NEED_RESCHED |
28fab1a2 | 242 | moveq pc, r8 @ go again |
1da177e4 LT |
243 | b 1b |
244 | #endif | |
245 | ||
246 | .align 5 | |
247 | __und_svc: | |
d30a0c8b NP |
248 | #ifdef CONFIG_KPROBES |
249 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
250 | @ it obviously needs free stack space which then will belong to | |
251 | @ the saved context. | |
252 | svc_entry 64 | |
253 | #else | |
ccea7a19 | 254 | svc_entry |
d30a0c8b | 255 | #endif |
1da177e4 LT |
256 | @ |
257 | @ call emulation code, which returns using r9 if it has emulated | |
258 | @ the instruction, or the more conventional lr if we are to treat | |
259 | @ this as a real undefined instruction | |
260 | @ | |
261 | @ r0 - instruction | |
262 | @ | |
83e686ea | 263 | #ifndef CONFIG_THUMB2_KERNEL |
b059bdc3 | 264 | ldr r0, [r4, #-4] |
83e686ea | 265 | #else |
b059bdc3 | 266 | ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 |
85519189 | 267 | cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 |
b059bdc3 | 268 | ldrhhs r9, [r4] @ bottom 16 bits |
83e686ea CM |
269 | orrhs r0, r9, r0, lsl #16 |
270 | #endif | |
b86040a5 | 271 | adr r9, BSYM(1f) |
b059bdc3 | 272 | mov r2, r4 |
1da177e4 LT |
273 | bl call_fpe |
274 | ||
275 | mov r0, sp @ struct pt_regs *regs | |
276 | bl do_undefinstr | |
277 | ||
278 | @ | |
279 | @ IRQs off again before pulling preserved data off the stack | |
280 | @ | |
ac78884e | 281 | 1: disable_irq_notrace |
1da177e4 LT |
282 | |
283 | @ | |
284 | @ restore SPSR and restart the instruction | |
285 | @ | |
b059bdc3 | 286 | ldr r5, [sp, #S_PSR] @ Get SVC cpsr |
df295df6 RK |
287 | #ifdef CONFIG_TRACE_IRQFLAGS |
288 | tst r5, #PSR_I_BIT | |
289 | bleq trace_hardirqs_on | |
290 | tst r5, #PSR_I_BIT | |
291 | blne trace_hardirqs_off | |
292 | #endif | |
b059bdc3 | 293 | svc_exit r5 @ return from exception |
c4c5716e | 294 | UNWIND(.fnend ) |
93ed3970 | 295 | ENDPROC(__und_svc) |
1da177e4 LT |
296 | |
297 | .align 5 | |
298 | __pabt_svc: | |
ccea7a19 | 299 | svc_entry |
4fb28474 | 300 | mov r2, sp @ regs |
8dfe7ac9 | 301 | pabt_helper |
1da177e4 LT |
302 | |
303 | @ | |
304 | @ IRQs off again before pulling preserved data off the stack | |
305 | @ | |
ac78884e | 306 | disable_irq_notrace |
1da177e4 | 307 | |
02fe2845 RK |
308 | #ifdef CONFIG_TRACE_IRQFLAGS |
309 | tst r5, #PSR_I_BIT | |
310 | bleq trace_hardirqs_on | |
311 | tst r5, #PSR_I_BIT | |
312 | blne trace_hardirqs_off | |
313 | #endif | |
b059bdc3 | 314 | svc_exit r5 @ return from exception |
c4c5716e | 315 | UNWIND(.fnend ) |
93ed3970 | 316 | ENDPROC(__pabt_svc) |
1da177e4 LT |
317 | |
318 | .align 5 | |
49f680ea RK |
319 | .LCcralign: |
320 | .word cr_alignment | |
48d7927b | 321 | #ifdef MULTI_DABORT |
1da177e4 LT |
322 | .LCprocfns: |
323 | .word processor | |
324 | #endif | |
325 | .LCfp: | |
326 | .word fp_enter | |
1da177e4 LT |
327 | |
328 | /* | |
329 | * User mode handlers | |
2dede2d8 NP |
330 | * |
331 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 332 | */ |
2dede2d8 NP |
333 | |
334 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
335 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
336 | #endif | |
337 | ||
ccea7a19 | 338 | .macro usr_entry |
c4c5716e CM |
339 | UNWIND(.fnstart ) |
340 | UNWIND(.cantunwind ) @ don't unwind the user space | |
ccea7a19 | 341 | sub sp, sp, #S_FRAME_SIZE |
b86040a5 CM |
342 | ARM( stmib sp, {r1 - r12} ) |
343 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 | 344 | |
b059bdc3 | 345 | ldmia r0, {r3 - r5} |
ccea7a19 | 346 | add r0, sp, #S_PC @ here for interlock avoidance |
b059bdc3 | 347 | mov r6, #-1 @ "" "" "" "" |
ccea7a19 | 348 | |
b059bdc3 | 349 | str r3, [sp] @ save the "real" r0 copied |
ccea7a19 | 350 | @ from the exception stack |
1da177e4 LT |
351 | |
352 | @ | |
353 | @ We are now ready to fill in the remaining blanks on the stack: | |
354 | @ | |
b059bdc3 RK |
355 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
356 | @ r5 - spsr_<exception> | |
357 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 LT |
358 | @ |
359 | @ Also, separately save sp_usr and lr_usr | |
360 | @ | |
b059bdc3 | 361 | stmia r0, {r4 - r6} |
b86040a5 CM |
362 | ARM( stmdb r0, {sp, lr}^ ) |
363 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 LT |
364 | |
365 | @ | |
366 | @ Enable the alignment trap while in kernel mode | |
367 | @ | |
49f680ea | 368 | alignment_trap r0 |
1da177e4 LT |
369 | |
370 | @ | |
371 | @ Clear FP to mark the first stack frame | |
372 | @ | |
373 | zero_fp | |
f2741b78 RK |
374 | |
375 | #ifdef CONFIG_IRQSOFF_TRACER | |
376 | bl trace_hardirqs_off | |
377 | #endif | |
1da177e4 LT |
378 | .endm |
379 | ||
b49c0f24 | 380 | .macro kuser_cmpxchg_check |
40fb79c8 | 381 | #if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
b49c0f24 NP |
382 | #ifndef CONFIG_MMU |
383 | #warning "NPTL on non MMU needs fixing" | |
384 | #else | |
385 | @ Make sure our user space atomic helper is restarted | |
386 | @ if it was interrupted in a critical region. Here we | |
387 | @ perform a quick test inline since it should be false | |
388 | @ 99.9999% of the time. The rest is done out of line. | |
b059bdc3 | 389 | cmp r4, #TASK_SIZE |
40fb79c8 | 390 | blhs kuser_cmpxchg64_fixup |
b49c0f24 NP |
391 | #endif |
392 | #endif | |
393 | .endm | |
394 | ||
1da177e4 LT |
395 | .align 5 |
396 | __dabt_usr: | |
ccea7a19 | 397 | usr_entry |
b49c0f24 | 398 | kuser_cmpxchg_check |
1da177e4 | 399 | mov r2, sp |
da740472 RK |
400 | dabt_helper |
401 | b ret_from_exception | |
c4c5716e | 402 | UNWIND(.fnend ) |
93ed3970 | 403 | ENDPROC(__dabt_usr) |
1da177e4 LT |
404 | |
405 | .align 5 | |
406 | __irq_usr: | |
ccea7a19 | 407 | usr_entry |
bc089602 | 408 | kuser_cmpxchg_check |
187a51ad | 409 | irq_handler |
1613cc11 | 410 | get_thread_info tsk |
1da177e4 | 411 | mov why, #0 |
9fc2552a | 412 | b ret_to_user_from_irq |
c4c5716e | 413 | UNWIND(.fnend ) |
93ed3970 | 414 | ENDPROC(__irq_usr) |
1da177e4 LT |
415 | |
416 | .ltorg | |
417 | ||
418 | .align 5 | |
419 | __und_usr: | |
ccea7a19 | 420 | usr_entry |
bc089602 | 421 | |
b059bdc3 RK |
422 | mov r2, r4 |
423 | mov r3, r5 | |
1da177e4 | 424 | |
1da177e4 LT |
425 | @ |
426 | @ fall through to the emulation code, which returns using r9 if | |
427 | @ it has emulated the instruction, or the more conventional lr | |
428 | @ if we are to treat this as a real undefined instruction | |
429 | @ | |
430 | @ r0 - instruction | |
431 | @ | |
b86040a5 CM |
432 | adr r9, BSYM(ret_from_exception) |
433 | adr lr, BSYM(__und_usr_unknown) | |
cb170a45 | 434 | tst r3, #PSR_T_BIT @ Thumb mode? |
b86040a5 | 435 | itet eq @ explicit IT needed for the 1f label |
cb170a45 PB |
436 | subeq r4, r2, #4 @ ARM instr at LR - 4 |
437 | subne r4, r2, #2 @ Thumb instr at LR - 2 | |
438 | 1: ldreqt r0, [r4] | |
26584853 CM |
439 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
440 | reveq r0, r0 @ little endian instruction | |
441 | #endif | |
cb170a45 PB |
442 | beq call_fpe |
443 | @ Thumb instruction | |
ef4c5368 DM |
444 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
445 | /* | |
446 | * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms | |
447 | * can never be supported in a single kernel, this code is not applicable at | |
448 | * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be | |
449 | * made about .arch directives. | |
450 | */ | |
451 | #if __LINUX_ARM_ARCH__ < 7 | |
452 | /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ | |
453 | #define NEED_CPU_ARCHITECTURE | |
454 | ldr r5, .LCcpu_architecture | |
455 | ldr r5, [r5] | |
456 | cmp r5, #CPU_ARCH_ARMv7 | |
457 | blo __und_usr_unknown | |
458 | /* | |
459 | * The following code won't get run unless the running CPU really is v7, so | |
460 | * coding round the lack of ldrht on older arches is pointless. Temporarily | |
461 | * override the assembler target arch with the minimum required instead: | |
462 | */ | |
463 | .arch armv6t2 | |
464 | #endif | |
b86040a5 CM |
465 | 2: |
466 | ARM( ldrht r5, [r4], #2 ) | |
467 | THUMB( ldrht r5, [r4] ) | |
468 | THUMB( add r4, r4, #2 ) | |
85519189 | 469 | cmp r5, #0xe800 @ 32bit instruction if xx != 0 |
cb170a45 PB |
470 | blo __und_usr_unknown |
471 | 3: ldrht r0, [r4] | |
472 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 | |
473 | orr r0, r0, r5, lsl #16 | |
ef4c5368 DM |
474 | |
475 | #if __LINUX_ARM_ARCH__ < 7 | |
476 | /* If the target arch was overridden, change it back: */ | |
477 | #ifdef CONFIG_CPU_32v6K | |
478 | .arch armv6k | |
cb170a45 | 479 | #else |
ef4c5368 DM |
480 | .arch armv6 |
481 | #endif | |
482 | #endif /* __LINUX_ARM_ARCH__ < 7 */ | |
483 | #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ | |
cb170a45 PB |
484 | b __und_usr_unknown |
485 | #endif | |
c4c5716e | 486 | UNWIND(.fnend ) |
93ed3970 | 487 | ENDPROC(__und_usr) |
cb170a45 | 488 | |
1da177e4 LT |
489 | @ |
490 | @ fallthrough to call_fpe | |
491 | @ | |
492 | ||
493 | /* | |
494 | * The out of line fixup for the ldrt above. | |
495 | */ | |
4260415f | 496 | .pushsection .fixup, "ax" |
cb170a45 | 497 | 4: mov pc, r9 |
4260415f RK |
498 | .popsection |
499 | .pushsection __ex_table,"a" | |
cb170a45 | 500 | .long 1b, 4b |
c89cefed | 501 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
cb170a45 PB |
502 | .long 2b, 4b |
503 | .long 3b, 4b | |
504 | #endif | |
4260415f | 505 | .popsection |
1da177e4 LT |
506 | |
507 | /* | |
508 | * Check whether the instruction is a co-processor instruction. | |
509 | * If yes, we need to call the relevant co-processor handler. | |
510 | * | |
511 | * Note that we don't do a full check here for the co-processor | |
512 | * instructions; all instructions with bit 27 set are well | |
513 | * defined. The only instructions that should fault are the | |
514 | * co-processor instructions. However, we have to watch out | |
515 | * for the ARM6/ARM7 SWI bug. | |
516 | * | |
b5872db4 CM |
517 | * NEON is a special case that has to be handled here. Not all |
518 | * NEON instructions are co-processor instructions, so we have | |
519 | * to make a special case of checking for them. Plus, there's | |
520 | * five groups of them, so we have a table of mask/opcode pairs | |
521 | * to check against, and if any match then we branch off into the | |
522 | * NEON handler code. | |
523 | * | |
1da177e4 LT |
524 | * Emulators may wish to make use of the following registers: |
525 | * r0 = instruction opcode. | |
526 | * r2 = PC+4 | |
db6ccbb6 | 527 | * r9 = normal "successful" return address |
1da177e4 | 528 | * r10 = this threads thread_info structure. |
db6ccbb6 | 529 | * lr = unrecognised instruction return address |
1da177e4 | 530 | */ |
cb170a45 PB |
531 | @ |
532 | @ Fall-through from Thumb-2 __und_usr | |
533 | @ | |
534 | #ifdef CONFIG_NEON | |
535 | adr r6, .LCneon_thumb_opcodes | |
536 | b 2f | |
537 | #endif | |
1da177e4 | 538 | call_fpe: |
b5872db4 | 539 | #ifdef CONFIG_NEON |
cb170a45 | 540 | adr r6, .LCneon_arm_opcodes |
b5872db4 CM |
541 | 2: |
542 | ldr r7, [r6], #4 @ mask value | |
543 | cmp r7, #0 @ end mask? | |
544 | beq 1f | |
545 | and r8, r0, r7 | |
546 | ldr r7, [r6], #4 @ opcode bits matching in mask | |
547 | cmp r8, r7 @ NEON instruction? | |
548 | bne 2b | |
549 | get_thread_info r10 | |
550 | mov r7, #1 | |
551 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
552 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
553 | b do_vfp @ let VFP handler handle this | |
554 | 1: | |
555 | #endif | |
1da177e4 | 556 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 557 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
1da177e4 LT |
558 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) |
559 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
560 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
561 | #endif | |
562 | moveq pc, lr | |
563 | get_thread_info r10 @ get current thread | |
564 | and r8, r0, #0x00000f00 @ mask out CP number | |
b86040a5 | 565 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
566 | mov r7, #1 |
567 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
568 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
569 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
570 | #ifdef CONFIG_IWMMXT |
571 | @ Test if we need to give access to iWMMXt coprocessors | |
572 | ldr r5, [r10, #TI_FLAGS] | |
573 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
574 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
575 | bcs iwmmxt_task_enable | |
576 | #endif | |
b86040a5 CM |
577 | ARM( add pc, pc, r8, lsr #6 ) |
578 | THUMB( lsl r8, r8, #2 ) | |
579 | THUMB( add pc, r8 ) | |
580 | nop | |
581 | ||
a771fe6e | 582 | movw_pc lr @ CP#0 |
b86040a5 CM |
583 | W(b) do_fpe @ CP#1 (FPE) |
584 | W(b) do_fpe @ CP#2 (FPE) | |
a771fe6e | 585 | movw_pc lr @ CP#3 |
c17fad11 LB |
586 | #ifdef CONFIG_CRUNCH |
587 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
588 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
589 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
590 | #else | |
a771fe6e CM |
591 | movw_pc lr @ CP#4 |
592 | movw_pc lr @ CP#5 | |
593 | movw_pc lr @ CP#6 | |
c17fad11 | 594 | #endif |
a771fe6e CM |
595 | movw_pc lr @ CP#7 |
596 | movw_pc lr @ CP#8 | |
597 | movw_pc lr @ CP#9 | |
1da177e4 | 598 | #ifdef CONFIG_VFP |
b86040a5 CM |
599 | W(b) do_vfp @ CP#10 (VFP) |
600 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 601 | #else |
a771fe6e CM |
602 | movw_pc lr @ CP#10 (VFP) |
603 | movw_pc lr @ CP#11 (VFP) | |
1da177e4 | 604 | #endif |
a771fe6e CM |
605 | movw_pc lr @ CP#12 |
606 | movw_pc lr @ CP#13 | |
607 | movw_pc lr @ CP#14 (Debug) | |
608 | movw_pc lr @ CP#15 (Control) | |
1da177e4 | 609 | |
ef4c5368 DM |
610 | #ifdef NEED_CPU_ARCHITECTURE |
611 | .align 2 | |
612 | .LCcpu_architecture: | |
613 | .word __cpu_architecture | |
614 | #endif | |
615 | ||
b5872db4 CM |
616 | #ifdef CONFIG_NEON |
617 | .align 6 | |
618 | ||
cb170a45 | 619 | .LCneon_arm_opcodes: |
b5872db4 CM |
620 | .word 0xfe000000 @ mask |
621 | .word 0xf2000000 @ opcode | |
622 | ||
623 | .word 0xff100000 @ mask | |
624 | .word 0xf4000000 @ opcode | |
625 | ||
cb170a45 PB |
626 | .word 0x00000000 @ mask |
627 | .word 0x00000000 @ opcode | |
628 | ||
629 | .LCneon_thumb_opcodes: | |
630 | .word 0xef000000 @ mask | |
631 | .word 0xef000000 @ opcode | |
632 | ||
633 | .word 0xff100000 @ mask | |
634 | .word 0xf9000000 @ opcode | |
635 | ||
b5872db4 CM |
636 | .word 0x00000000 @ mask |
637 | .word 0x00000000 @ opcode | |
638 | #endif | |
639 | ||
1da177e4 | 640 | do_fpe: |
5d25ac03 | 641 | enable_irq |
1da177e4 LT |
642 | ldr r4, .LCfp |
643 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
644 | ldr pc, [r4] @ Call FP module USR entry point | |
645 | ||
646 | /* | |
647 | * The FP module is called with these registers set: | |
648 | * r0 = instruction | |
649 | * r2 = PC+4 | |
650 | * r9 = normal "successful" return address | |
651 | * r10 = FP workspace | |
652 | * lr = unrecognised FP instruction return address | |
653 | */ | |
654 | ||
124efc27 | 655 | .pushsection .data |
1da177e4 | 656 | ENTRY(fp_enter) |
db6ccbb6 | 657 | .word no_fp |
124efc27 | 658 | .popsection |
1da177e4 | 659 | |
83e686ea CM |
660 | ENTRY(no_fp) |
661 | mov pc, lr | |
662 | ENDPROC(no_fp) | |
db6ccbb6 RK |
663 | |
664 | __und_usr_unknown: | |
ecbab71c | 665 | enable_irq |
1da177e4 | 666 | mov r0, sp |
b86040a5 | 667 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 668 | b do_undefinstr |
93ed3970 | 669 | ENDPROC(__und_usr_unknown) |
1da177e4 LT |
670 | |
671 | .align 5 | |
672 | __pabt_usr: | |
ccea7a19 | 673 | usr_entry |
4fb28474 | 674 | mov r2, sp @ regs |
8dfe7ac9 | 675 | pabt_helper |
c4c5716e | 676 | UNWIND(.fnend ) |
1da177e4 LT |
677 | /* fall through */ |
678 | /* | |
679 | * This is the return code to user mode for abort handlers | |
680 | */ | |
681 | ENTRY(ret_from_exception) | |
c4c5716e CM |
682 | UNWIND(.fnstart ) |
683 | UNWIND(.cantunwind ) | |
1da177e4 LT |
684 | get_thread_info tsk |
685 | mov why, #0 | |
686 | b ret_to_user | |
c4c5716e | 687 | UNWIND(.fnend ) |
93ed3970 CM |
688 | ENDPROC(__pabt_usr) |
689 | ENDPROC(ret_from_exception) | |
1da177e4 LT |
690 | |
691 | /* | |
692 | * Register switch for ARMv3 and ARMv4 processors | |
693 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
694 | * previous and next are guaranteed not to be the same. | |
695 | */ | |
696 | ENTRY(__switch_to) | |
c4c5716e CM |
697 | UNWIND(.fnstart ) |
698 | UNWIND(.cantunwind ) | |
1da177e4 LT |
699 | add ip, r1, #TI_CPU_SAVE |
700 | ldr r3, [r2, #TI_TP_VALUE] | |
b86040a5 CM |
701 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
702 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
703 | THUMB( str sp, [ip], #4 ) | |
704 | THUMB( str lr, [ip], #4 ) | |
247055aa | 705 | #ifdef CONFIG_CPU_USE_DOMAINS |
d6551e88 | 706 | ldr r6, [r2, #TI_CPU_DOMAIN] |
afeb90ca | 707 | #endif |
f159f4ed | 708 | set_tls r3, r4, r5 |
df0698be NP |
709 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
710 | ldr r7, [r2, #TI_TASK] | |
711 | ldr r8, =__stack_chk_guard | |
712 | ldr r7, [r7, #TSK_STACK_CANARY] | |
713 | #endif | |
247055aa | 714 | #ifdef CONFIG_CPU_USE_DOMAINS |
1da177e4 | 715 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 716 | #endif |
d6551e88 RK |
717 | mov r5, r0 |
718 | add r4, r2, #TI_CPU_SAVE | |
719 | ldr r0, =thread_notify_head | |
720 | mov r1, #THREAD_NOTIFY_SWITCH | |
721 | bl atomic_notifier_call_chain | |
df0698be NP |
722 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
723 | str r7, [r8] | |
724 | #endif | |
b86040a5 | 725 | THUMB( mov ip, r4 ) |
d6551e88 | 726 | mov r0, r5 |
b86040a5 CM |
727 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
728 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
729 | THUMB( ldr sp, [ip], #4 ) | |
730 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 731 | UNWIND(.fnend ) |
93ed3970 | 732 | ENDPROC(__switch_to) |
1da177e4 LT |
733 | |
734 | __INIT | |
2d2669b6 NP |
735 | |
736 | /* | |
737 | * User helpers. | |
738 | * | |
2d2669b6 NP |
739 | * Each segment is 32-byte aligned and will be moved to the top of the high |
740 | * vector page. New segments (if ever needed) must be added in front of | |
741 | * existing ones. This mechanism should be used only for things that are | |
742 | * really small and justified, and not be abused freely. | |
743 | * | |
37b83046 | 744 | * See Documentation/arm/kernel_user_helpers.txt for formal definitions. |
2d2669b6 | 745 | */ |
b86040a5 | 746 | THUMB( .arm ) |
2d2669b6 | 747 | |
ba9b5d76 NP |
748 | .macro usr_ret, reg |
749 | #ifdef CONFIG_ARM_THUMB | |
750 | bx \reg | |
751 | #else | |
752 | mov pc, \reg | |
753 | #endif | |
754 | .endm | |
755 | ||
2d2669b6 NP |
756 | .align 5 |
757 | .globl __kuser_helper_start | |
758 | __kuser_helper_start: | |
759 | ||
7c612bfd | 760 | /* |
40fb79c8 NP |
761 | * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular |
762 | * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. | |
7c612bfd NP |
763 | */ |
764 | ||
40fb79c8 NP |
765 | __kuser_cmpxchg64: @ 0xffff0f60 |
766 | ||
767 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
768 | ||
769 | /* | |
770 | * Poor you. No fast solution possible... | |
771 | * The kernel itself must perform the operation. | |
772 | * A special ghost syscall is used for that (see traps.c). | |
773 | */ | |
774 | stmfd sp!, {r7, lr} | |
775 | ldr r7, 1f @ it's 20 bits | |
776 | swi __ARM_NR_cmpxchg64 | |
777 | ldmfd sp!, {r7, pc} | |
778 | 1: .word __ARM_NR_cmpxchg64 | |
779 | ||
780 | #elif defined(CONFIG_CPU_32v6K) | |
781 | ||
782 | stmfd sp!, {r4, r5, r6, r7} | |
783 | ldrd r4, r5, [r0] @ load old val | |
784 | ldrd r6, r7, [r1] @ load new val | |
785 | smp_dmb arm | |
786 | 1: ldrexd r0, r1, [r2] @ load current val | |
787 | eors r3, r0, r4 @ compare with oldval (1) | |
788 | eoreqs r3, r1, r5 @ compare with oldval (2) | |
789 | strexdeq r3, r6, r7, [r2] @ store newval if eq | |
790 | teqeq r3, #1 @ success? | |
791 | beq 1b @ if no then retry | |
ed3768a8 | 792 | smp_dmb arm |
40fb79c8 NP |
793 | rsbs r0, r3, #0 @ set returned val and C flag |
794 | ldmfd sp!, {r4, r5, r6, r7} | |
5a97d0ae | 795 | usr_ret lr |
40fb79c8 NP |
796 | |
797 | #elif !defined(CONFIG_SMP) | |
798 | ||
799 | #ifdef CONFIG_MMU | |
800 | ||
801 | /* | |
802 | * The only thing that can break atomicity in this cmpxchg64 | |
803 | * implementation is either an IRQ or a data abort exception | |
804 | * causing another process/thread to be scheduled in the middle of | |
805 | * the critical sequence. The same strategy as for cmpxchg is used. | |
806 | */ | |
807 | stmfd sp!, {r4, r5, r6, lr} | |
808 | ldmia r0, {r4, r5} @ load old val | |
809 | ldmia r1, {r6, lr} @ load new val | |
810 | 1: ldmia r2, {r0, r1} @ load current val | |
811 | eors r3, r0, r4 @ compare with oldval (1) | |
812 | eoreqs r3, r1, r5 @ compare with oldval (2) | |
813 | 2: stmeqia r2, {r6, lr} @ store newval if eq | |
814 | rsbs r0, r3, #0 @ set return val and C flag | |
815 | ldmfd sp!, {r4, r5, r6, pc} | |
816 | ||
817 | .text | |
818 | kuser_cmpxchg64_fixup: | |
819 | @ Called from kuser_cmpxchg_fixup. | |
3ad55155 | 820 | @ r4 = address of interrupted insn (must be preserved). |
40fb79c8 NP |
821 | @ sp = saved regs. r7 and r8 are clobbered. |
822 | @ 1b = first critical insn, 2b = last critical insn. | |
3ad55155 | 823 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
40fb79c8 NP |
824 | mov r7, #0xffff0fff |
825 | sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) | |
3ad55155 | 826 | subs r8, r4, r7 |
40fb79c8 NP |
827 | rsbcss r8, r8, #(2b - 1b) |
828 | strcs r7, [sp, #S_PC] | |
829 | #if __LINUX_ARM_ARCH__ < 6 | |
830 | bcc kuser_cmpxchg32_fixup | |
831 | #endif | |
832 | mov pc, lr | |
833 | .previous | |
834 | ||
835 | #else | |
836 | #warning "NPTL on non MMU needs fixing" | |
837 | mov r0, #-1 | |
838 | adds r0, r0, #0 | |
ba9b5d76 | 839 | usr_ret lr |
40fb79c8 NP |
840 | #endif |
841 | ||
842 | #else | |
843 | #error "incoherent kernel configuration" | |
844 | #endif | |
845 | ||
846 | /* pad to next slot */ | |
847 | .rept (16 - (. - __kuser_cmpxchg64)/4) | |
848 | .word 0 | |
849 | .endr | |
7c612bfd NP |
850 | |
851 | .align 5 | |
852 | ||
7c612bfd | 853 | __kuser_memory_barrier: @ 0xffff0fa0 |
ed3768a8 | 854 | smp_dmb arm |
ba9b5d76 | 855 | usr_ret lr |
7c612bfd NP |
856 | |
857 | .align 5 | |
2d2669b6 NP |
858 | |
859 | __kuser_cmpxchg: @ 0xffff0fc0 | |
860 | ||
dcef1f63 | 861 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 862 | |
dcef1f63 NP |
863 | /* |
864 | * Poor you. No fast solution possible... | |
865 | * The kernel itself must perform the operation. | |
866 | * A special ghost syscall is used for that (see traps.c). | |
867 | */ | |
5e097445 | 868 | stmfd sp!, {r7, lr} |
55afd264 | 869 | ldr r7, 1f @ it's 20 bits |
cc20d429 | 870 | swi __ARM_NR_cmpxchg |
5e097445 | 871 | ldmfd sp!, {r7, pc} |
cc20d429 | 872 | 1: .word __ARM_NR_cmpxchg |
dcef1f63 NP |
873 | |
874 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 875 | |
b49c0f24 NP |
876 | #ifdef CONFIG_MMU |
877 | ||
2d2669b6 | 878 | /* |
b49c0f24 NP |
879 | * The only thing that can break atomicity in this cmpxchg |
880 | * implementation is either an IRQ or a data abort exception | |
881 | * causing another process/thread to be scheduled in the middle | |
882 | * of the critical sequence. To prevent this, code is added to | |
883 | * the IRQ and data abort exception handlers to set the pc back | |
884 | * to the beginning of the critical section if it is found to be | |
885 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 886 | */ |
b49c0f24 NP |
887 | 1: ldr r3, [r2] @ load current val |
888 | subs r3, r3, r0 @ compare with oldval | |
889 | 2: streq r1, [r2] @ store newval if eq | |
890 | rsbs r0, r3, #0 @ set return val and C flag | |
891 | usr_ret lr | |
892 | ||
893 | .text | |
40fb79c8 | 894 | kuser_cmpxchg32_fixup: |
b49c0f24 | 895 | @ Called from kuser_cmpxchg_check macro. |
b059bdc3 | 896 | @ r4 = address of interrupted insn (must be preserved). |
b49c0f24 NP |
897 | @ sp = saved regs. r7 and r8 are clobbered. |
898 | @ 1b = first critical insn, 2b = last critical insn. | |
b059bdc3 | 899 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
b49c0f24 NP |
900 | mov r7, #0xffff0fff |
901 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
b059bdc3 | 902 | subs r8, r4, r7 |
b49c0f24 NP |
903 | rsbcss r8, r8, #(2b - 1b) |
904 | strcs r7, [sp, #S_PC] | |
905 | mov pc, lr | |
906 | .previous | |
907 | ||
49bca4c2 NP |
908 | #else |
909 | #warning "NPTL on non MMU needs fixing" | |
910 | mov r0, #-1 | |
911 | adds r0, r0, #0 | |
ba9b5d76 | 912 | usr_ret lr |
b49c0f24 | 913 | #endif |
2d2669b6 NP |
914 | |
915 | #else | |
916 | ||
ed3768a8 | 917 | smp_dmb arm |
b49c0f24 | 918 | 1: ldrex r3, [r2] |
2d2669b6 NP |
919 | subs r3, r3, r0 |
920 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
921 | teqeq r3, #1 |
922 | beq 1b | |
2d2669b6 | 923 | rsbs r0, r3, #0 |
b49c0f24 | 924 | /* beware -- each __kuser slot must be 8 instructions max */ |
f00ec48f RK |
925 | ALT_SMP(b __kuser_memory_barrier) |
926 | ALT_UP(usr_ret lr) | |
2d2669b6 NP |
927 | |
928 | #endif | |
929 | ||
930 | .align 5 | |
931 | ||
2d2669b6 | 932 | __kuser_get_tls: @ 0xffff0fe0 |
f159f4ed | 933 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
ba9b5d76 | 934 | usr_ret lr |
f159f4ed TL |
935 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
936 | .rep 4 | |
937 | .word 0 @ 0xffff0ff0 software TLS value, then | |
938 | .endr @ pad up to __kuser_helper_version | |
2d2669b6 | 939 | |
2d2669b6 NP |
940 | __kuser_helper_version: @ 0xffff0ffc |
941 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
942 | ||
943 | .globl __kuser_helper_end | |
944 | __kuser_helper_end: | |
945 | ||
b86040a5 | 946 | THUMB( .thumb ) |
2d2669b6 | 947 | |
1da177e4 LT |
948 | /* |
949 | * Vector stubs. | |
950 | * | |
7933523d RK |
951 | * This code is copied to 0xffff0200 so we can use branches in the |
952 | * vectors, rather than ldr's. Note that this code must not | |
953 | * exceed 0x300 bytes. | |
1da177e4 LT |
954 | * |
955 | * Common stub entry macro: | |
956 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
957 | * |
958 | * SP points to a minimal amount of processor-private memory, the address | |
959 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 960 | */ |
b7ec4795 | 961 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
962 | .align 5 |
963 | ||
964 | vector_\name: | |
1da177e4 LT |
965 | .if \correction |
966 | sub lr, lr, #\correction | |
967 | .endif | |
ccea7a19 RK |
968 | |
969 | @ | |
970 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
971 | @ (parent CPSR) | |
972 | @ | |
973 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 974 | mrs lr, spsr |
ccea7a19 RK |
975 | str lr, [sp, #8] @ save spsr |
976 | ||
1da177e4 | 977 | @ |
ccea7a19 | 978 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 979 | @ |
ccea7a19 | 980 | mrs r0, cpsr |
b86040a5 | 981 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 982 | msr spsr_cxsf, r0 |
1da177e4 | 983 | |
ccea7a19 RK |
984 | @ |
985 | @ the branch table must immediately follow this code | |
986 | @ | |
ccea7a19 | 987 | and lr, lr, #0x0f |
b86040a5 CM |
988 | THUMB( adr r0, 1f ) |
989 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 990 | mov r0, sp |
b86040a5 | 991 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 992 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 993 | ENDPROC(vector_\name) |
88987ef9 CM |
994 | |
995 | .align 2 | |
996 | @ handler addresses follow this label | |
997 | 1: | |
1da177e4 LT |
998 | .endm |
999 | ||
7933523d | 1000 | .globl __stubs_start |
1da177e4 LT |
1001 | __stubs_start: |
1002 | /* | |
1003 | * Interrupt dispatcher | |
1004 | */ | |
b7ec4795 | 1005 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1006 | |
1007 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1008 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1009 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1010 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1011 | .long __irq_invalid @ 4 | |
1012 | .long __irq_invalid @ 5 | |
1013 | .long __irq_invalid @ 6 | |
1014 | .long __irq_invalid @ 7 | |
1015 | .long __irq_invalid @ 8 | |
1016 | .long __irq_invalid @ 9 | |
1017 | .long __irq_invalid @ a | |
1018 | .long __irq_invalid @ b | |
1019 | .long __irq_invalid @ c | |
1020 | .long __irq_invalid @ d | |
1021 | .long __irq_invalid @ e | |
1022 | .long __irq_invalid @ f | |
1023 | ||
1024 | /* | |
1025 | * Data abort dispatcher | |
1026 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1027 | */ | |
b7ec4795 | 1028 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1029 | |
1030 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1031 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1032 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1033 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1034 | .long __dabt_invalid @ 4 | |
1035 | .long __dabt_invalid @ 5 | |
1036 | .long __dabt_invalid @ 6 | |
1037 | .long __dabt_invalid @ 7 | |
1038 | .long __dabt_invalid @ 8 | |
1039 | .long __dabt_invalid @ 9 | |
1040 | .long __dabt_invalid @ a | |
1041 | .long __dabt_invalid @ b | |
1042 | .long __dabt_invalid @ c | |
1043 | .long __dabt_invalid @ d | |
1044 | .long __dabt_invalid @ e | |
1045 | .long __dabt_invalid @ f | |
1046 | ||
1047 | /* | |
1048 | * Prefetch abort dispatcher | |
1049 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1050 | */ | |
b7ec4795 | 1051 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1052 | |
1053 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1054 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1055 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1056 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1057 | .long __pabt_invalid @ 4 | |
1058 | .long __pabt_invalid @ 5 | |
1059 | .long __pabt_invalid @ 6 | |
1060 | .long __pabt_invalid @ 7 | |
1061 | .long __pabt_invalid @ 8 | |
1062 | .long __pabt_invalid @ 9 | |
1063 | .long __pabt_invalid @ a | |
1064 | .long __pabt_invalid @ b | |
1065 | .long __pabt_invalid @ c | |
1066 | .long __pabt_invalid @ d | |
1067 | .long __pabt_invalid @ e | |
1068 | .long __pabt_invalid @ f | |
1069 | ||
1070 | /* | |
1071 | * Undef instr entry dispatcher | |
1072 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1073 | */ | |
b7ec4795 | 1074 | vector_stub und, UND_MODE |
1da177e4 LT |
1075 | |
1076 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1077 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1078 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1079 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1080 | .long __und_invalid @ 4 | |
1081 | .long __und_invalid @ 5 | |
1082 | .long __und_invalid @ 6 | |
1083 | .long __und_invalid @ 7 | |
1084 | .long __und_invalid @ 8 | |
1085 | .long __und_invalid @ 9 | |
1086 | .long __und_invalid @ a | |
1087 | .long __und_invalid @ b | |
1088 | .long __und_invalid @ c | |
1089 | .long __und_invalid @ d | |
1090 | .long __und_invalid @ e | |
1091 | .long __und_invalid @ f | |
1092 | ||
1093 | .align 5 | |
1094 | ||
1095 | /*============================================================================= | |
1096 | * Undefined FIQs | |
1097 | *----------------------------------------------------------------------------- | |
1098 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1099 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1100 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1101 | * damage alert! I don't think that we can execute any code in here in any | |
1102 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1103 | * get out of that mode without clobbering one register. | |
1104 | */ | |
1105 | vector_fiq: | |
1da177e4 LT |
1106 | subs pc, lr, #4 |
1107 | ||
1108 | /*============================================================================= | |
1109 | * Address exception handler | |
1110 | *----------------------------------------------------------------------------- | |
1111 | * These aren't too critical. | |
1112 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1113 | */ | |
1114 | ||
1115 | vector_addrexcptn: | |
1116 | b vector_addrexcptn | |
1117 | ||
1118 | /* | |
1119 | * We group all the following data together to optimise | |
1120 | * for CPUs with separate I & D caches. | |
1121 | */ | |
1122 | .align 5 | |
1123 | ||
1124 | .LCvswi: | |
1125 | .word vector_swi | |
1126 | ||
7933523d | 1127 | .globl __stubs_end |
1da177e4 LT |
1128 | __stubs_end: |
1129 | ||
7933523d | 1130 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1131 | |
7933523d RK |
1132 | .globl __vectors_start |
1133 | __vectors_start: | |
b86040a5 CM |
1134 | ARM( swi SYS_ERROR0 ) |
1135 | THUMB( svc #0 ) | |
1136 | THUMB( nop ) | |
1137 | W(b) vector_und + stubs_offset | |
1138 | W(ldr) pc, .LCvswi + stubs_offset | |
1139 | W(b) vector_pabt + stubs_offset | |
1140 | W(b) vector_dabt + stubs_offset | |
1141 | W(b) vector_addrexcptn + stubs_offset | |
1142 | W(b) vector_irq + stubs_offset | |
1143 | W(b) vector_fiq + stubs_offset | |
7933523d RK |
1144 | |
1145 | .globl __vectors_end | |
1146 | __vectors_end: | |
1da177e4 LT |
1147 | |
1148 | .data | |
1149 | ||
1da177e4 LT |
1150 | .globl cr_alignment |
1151 | .globl cr_no_alignment | |
1152 | cr_alignment: | |
1153 | .space 4 | |
1154 | cr_no_alignment: | |
1155 | .space 4 | |
52108641 | 1156 | |
1157 | #ifdef CONFIG_MULTI_IRQ_HANDLER | |
1158 | .globl handle_arch_irq | |
1159 | handle_arch_irq: | |
1160 | .space 4 | |
1161 | #endif |