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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes | |
15 | * it to save wrong values... Be aware! | |
16 | */ | |
1da177e4 | 17 | |
f09b9979 | 18 | #include <asm/memory.h> |
1da177e4 | 19 | #include <asm/glue.h> |
1da177e4 | 20 | #include <asm/vfpmacros.h> |
bce495d8 | 21 | #include <asm/arch/entry-macro.S> |
d6551e88 | 22 | #include <asm/thread_notify.h> |
1da177e4 LT |
23 | |
24 | #include "entry-header.S" | |
25 | ||
187a51ad RK |
26 | /* |
27 | * Interrupt handling. Preserves r7, r8, r9 | |
28 | */ | |
29 | .macro irq_handler | |
f80dff9d | 30 | get_irqnr_preamble r5, lr |
187a51ad RK |
31 | 1: get_irqnr_and_base r0, r6, r5, lr |
32 | movne r1, sp | |
33 | @ | |
34 | @ routine called with r0 = irq number, r1 = struct pt_regs * | |
35 | @ | |
36 | adrne lr, 1b | |
37 | bne asm_do_IRQ | |
791be9b9 RK |
38 | |
39 | #ifdef CONFIG_SMP | |
40 | /* | |
41 | * XXX | |
42 | * | |
43 | * this macro assumes that irqstat (r6) and base (r5) are | |
44 | * preserved from get_irqnr_and_base above | |
45 | */ | |
46 | test_for_ipi r0, r6, r5, lr | |
47 | movne r0, sp | |
48 | adrne lr, 1b | |
49 | bne do_IPI | |
37ee16ae RK |
50 | |
51 | #ifdef CONFIG_LOCAL_TIMERS | |
52 | test_for_ltirq r0, r6, r5, lr | |
53 | movne r0, sp | |
54 | adrne lr, 1b | |
55 | bne do_local_timer | |
56 | #endif | |
791be9b9 RK |
57 | #endif |
58 | ||
187a51ad RK |
59 | .endm |
60 | ||
1da177e4 LT |
61 | /* |
62 | * Invalid mode handlers | |
63 | */ | |
ccea7a19 RK |
64 | .macro inv_entry, reason |
65 | sub sp, sp, #S_FRAME_SIZE | |
66 | stmib sp, {r1 - lr} | |
1da177e4 LT |
67 | mov r1, #\reason |
68 | .endm | |
69 | ||
70 | __pabt_invalid: | |
ccea7a19 RK |
71 | inv_entry BAD_PREFETCH |
72 | b common_invalid | |
1da177e4 LT |
73 | |
74 | __dabt_invalid: | |
ccea7a19 RK |
75 | inv_entry BAD_DATA |
76 | b common_invalid | |
1da177e4 LT |
77 | |
78 | __irq_invalid: | |
ccea7a19 RK |
79 | inv_entry BAD_IRQ |
80 | b common_invalid | |
1da177e4 LT |
81 | |
82 | __und_invalid: | |
ccea7a19 RK |
83 | inv_entry BAD_UNDEFINSTR |
84 | ||
85 | @ | |
86 | @ XXX fall through to common_invalid | |
87 | @ | |
88 | ||
89 | @ | |
90 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
91 | @ | |
92 | common_invalid: | |
93 | zero_fp | |
94 | ||
95 | ldmia r0, {r4 - r6} | |
96 | add r0, sp, #S_PC @ here for interlock avoidance | |
97 | mov r7, #-1 @ "" "" "" "" | |
98 | str r4, [sp] @ save preserved r0 | |
99 | stmia r0, {r5 - r7} @ lr_<exception>, | |
100 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 101 | |
1da177e4 | 102 | mov r0, sp |
1da177e4 LT |
103 | b bad_mode |
104 | ||
105 | /* | |
106 | * SVC mode handlers | |
107 | */ | |
2dede2d8 NP |
108 | |
109 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
110 | #define SPFIX(code...) code | |
111 | #else | |
112 | #define SPFIX(code...) | |
113 | #endif | |
114 | ||
ccea7a19 | 115 | .macro svc_entry |
1da177e4 | 116 | sub sp, sp, #S_FRAME_SIZE |
2dede2d8 NP |
117 | SPFIX( tst sp, #4 ) |
118 | SPFIX( bicne sp, sp, #4 ) | |
ccea7a19 RK |
119 | stmib sp, {r1 - r12} |
120 | ||
121 | ldmia r0, {r1 - r3} | |
122 | add r5, sp, #S_SP @ here for interlock avoidance | |
123 | mov r4, #-1 @ "" "" "" "" | |
124 | add r0, sp, #S_FRAME_SIZE @ "" "" "" "" | |
2dede2d8 | 125 | SPFIX( addne r0, r0, #4 ) |
ccea7a19 RK |
126 | str r1, [sp] @ save the "real" r0 copied |
127 | @ from the exception stack | |
128 | ||
1da177e4 LT |
129 | mov r1, lr |
130 | ||
131 | @ | |
132 | @ We are now ready to fill in the remaining blanks on the stack: | |
133 | @ | |
134 | @ r0 - sp_svc | |
135 | @ r1 - lr_svc | |
136 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
137 | @ r3 - spsr_<exception> | |
138 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
139 | @ | |
140 | stmia r5, {r0 - r4} | |
141 | .endm | |
142 | ||
143 | .align 5 | |
144 | __dabt_svc: | |
ccea7a19 | 145 | svc_entry |
1da177e4 LT |
146 | |
147 | @ | |
148 | @ get ready to re-enable interrupts if appropriate | |
149 | @ | |
150 | mrs r9, cpsr | |
151 | tst r3, #PSR_I_BIT | |
152 | biceq r9, r9, #PSR_I_BIT | |
153 | ||
154 | @ | |
155 | @ Call the processor-specific abort handler: | |
156 | @ | |
157 | @ r2 - aborted context pc | |
158 | @ r3 - aborted context cpsr | |
159 | @ | |
160 | @ The abort handler must return the aborted address in r0, and | |
161 | @ the fault status register in r1. r9 must be preserved. | |
162 | @ | |
163 | #ifdef MULTI_ABORT | |
164 | ldr r4, .LCprocfns | |
165 | mov lr, pc | |
166 | ldr pc, [r4] | |
167 | #else | |
168 | bl CPU_ABORT_HANDLER | |
169 | #endif | |
170 | ||
171 | @ | |
172 | @ set desired IRQ state, then call main handler | |
173 | @ | |
174 | msr cpsr_c, r9 | |
175 | mov r2, sp | |
176 | bl do_DataAbort | |
177 | ||
178 | @ | |
179 | @ IRQs off again before pulling preserved data off the stack | |
180 | @ | |
1ec42c0c | 181 | disable_irq |
1da177e4 LT |
182 | |
183 | @ | |
184 | @ restore SPSR and restart the instruction | |
185 | @ | |
186 | ldr r0, [sp, #S_PSR] | |
187 | msr spsr_cxsf, r0 | |
188 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
189 | ||
190 | .align 5 | |
191 | __irq_svc: | |
ccea7a19 RK |
192 | svc_entry |
193 | ||
7ad1bcb2 RK |
194 | #ifdef CONFIG_TRACE_IRQFLAGS |
195 | bl trace_hardirqs_off | |
196 | #endif | |
1da177e4 | 197 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
198 | get_thread_info tsk |
199 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
200 | add r7, r8, #1 @ increment it | |
201 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 202 | #endif |
ccea7a19 | 203 | |
187a51ad | 204 | irq_handler |
1da177e4 | 205 | #ifdef CONFIG_PREEMPT |
706fdd9f | 206 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
1da177e4 LT |
207 | tst r0, #_TIF_NEED_RESCHED |
208 | blne svc_preempt | |
209 | preempt_return: | |
706fdd9f RK |
210 | ldr r0, [tsk, #TI_PREEMPT] @ read preempt value |
211 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count | |
1da177e4 | 212 | teq r0, r7 |
1da177e4 LT |
213 | strne r0, [r0, -r0] @ bug() |
214 | #endif | |
215 | ldr r0, [sp, #S_PSR] @ irqs are already disabled | |
216 | msr spsr_cxsf, r0 | |
7ad1bcb2 RK |
217 | #ifdef CONFIG_TRACE_IRQFLAGS |
218 | tst r0, #PSR_I_BIT | |
219 | bleq trace_hardirqs_on | |
220 | #endif | |
1da177e4 LT |
221 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr |
222 | ||
223 | .ltorg | |
224 | ||
225 | #ifdef CONFIG_PREEMPT | |
226 | svc_preempt: | |
706fdd9f | 227 | teq r8, #0 @ was preempt count = 0 |
1da177e4 LT |
228 | ldreq r6, .LCirq_stat |
229 | movne pc, lr @ no | |
230 | ldr r0, [r6, #4] @ local_irq_count | |
231 | ldr r1, [r6, #8] @ local_bh_count | |
232 | adds r0, r0, r1 | |
233 | movne pc, lr | |
234 | mov r7, #0 @ preempt_schedule_irq | |
706fdd9f | 235 | str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 |
1da177e4 | 236 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 237 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 LT |
238 | tst r0, #_TIF_NEED_RESCHED |
239 | beq preempt_return @ go again | |
240 | b 1b | |
241 | #endif | |
242 | ||
243 | .align 5 | |
244 | __und_svc: | |
ccea7a19 | 245 | svc_entry |
1da177e4 LT |
246 | |
247 | @ | |
248 | @ call emulation code, which returns using r9 if it has emulated | |
249 | @ the instruction, or the more conventional lr if we are to treat | |
250 | @ this as a real undefined instruction | |
251 | @ | |
252 | @ r0 - instruction | |
253 | @ | |
254 | ldr r0, [r2, #-4] | |
255 | adr r9, 1f | |
256 | bl call_fpe | |
257 | ||
258 | mov r0, sp @ struct pt_regs *regs | |
259 | bl do_undefinstr | |
260 | ||
261 | @ | |
262 | @ IRQs off again before pulling preserved data off the stack | |
263 | @ | |
1ec42c0c | 264 | 1: disable_irq |
1da177e4 LT |
265 | |
266 | @ | |
267 | @ restore SPSR and restart the instruction | |
268 | @ | |
269 | ldr lr, [sp, #S_PSR] @ Get SVC cpsr | |
270 | msr spsr_cxsf, lr | |
271 | ldmia sp, {r0 - pc}^ @ Restore SVC registers | |
272 | ||
273 | .align 5 | |
274 | __pabt_svc: | |
ccea7a19 | 275 | svc_entry |
1da177e4 LT |
276 | |
277 | @ | |
278 | @ re-enable interrupts if appropriate | |
279 | @ | |
280 | mrs r9, cpsr | |
281 | tst r3, #PSR_I_BIT | |
282 | biceq r9, r9, #PSR_I_BIT | |
283 | msr cpsr_c, r9 | |
284 | ||
285 | @ | |
286 | @ set args, then call main handler | |
287 | @ | |
288 | @ r0 - address of faulting instruction | |
289 | @ r1 - pointer to registers on stack | |
290 | @ | |
291 | mov r0, r2 @ address (pc) | |
292 | mov r1, sp @ regs | |
293 | bl do_PrefetchAbort @ call abort handler | |
294 | ||
295 | @ | |
296 | @ IRQs off again before pulling preserved data off the stack | |
297 | @ | |
1ec42c0c | 298 | disable_irq |
1da177e4 LT |
299 | |
300 | @ | |
301 | @ restore SPSR and restart the instruction | |
302 | @ | |
303 | ldr r0, [sp, #S_PSR] | |
304 | msr spsr_cxsf, r0 | |
305 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
306 | ||
307 | .align 5 | |
49f680ea RK |
308 | .LCcralign: |
309 | .word cr_alignment | |
1da177e4 LT |
310 | #ifdef MULTI_ABORT |
311 | .LCprocfns: | |
312 | .word processor | |
313 | #endif | |
314 | .LCfp: | |
315 | .word fp_enter | |
316 | #ifdef CONFIG_PREEMPT | |
317 | .LCirq_stat: | |
318 | .word irq_stat | |
319 | #endif | |
320 | ||
321 | /* | |
322 | * User mode handlers | |
2dede2d8 NP |
323 | * |
324 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 325 | */ |
2dede2d8 NP |
326 | |
327 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
328 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
329 | #endif | |
330 | ||
ccea7a19 RK |
331 | .macro usr_entry |
332 | sub sp, sp, #S_FRAME_SIZE | |
333 | stmib sp, {r1 - r12} | |
334 | ||
335 | ldmia r0, {r1 - r3} | |
336 | add r0, sp, #S_PC @ here for interlock avoidance | |
337 | mov r4, #-1 @ "" "" "" "" | |
338 | ||
339 | str r1, [sp] @ save the "real" r0 copied | |
340 | @ from the exception stack | |
1da177e4 LT |
341 | |
342 | @ | |
343 | @ We are now ready to fill in the remaining blanks on the stack: | |
344 | @ | |
345 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
346 | @ r3 - spsr_<exception> | |
347 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
348 | @ | |
349 | @ Also, separately save sp_usr and lr_usr | |
350 | @ | |
ccea7a19 RK |
351 | stmia r0, {r2 - r4} |
352 | stmdb r0, {sp, lr}^ | |
1da177e4 LT |
353 | |
354 | @ | |
355 | @ Enable the alignment trap while in kernel mode | |
356 | @ | |
49f680ea | 357 | alignment_trap r0 |
1da177e4 LT |
358 | |
359 | @ | |
360 | @ Clear FP to mark the first stack frame | |
361 | @ | |
362 | zero_fp | |
363 | .endm | |
364 | ||
b49c0f24 NP |
365 | .macro kuser_cmpxchg_check |
366 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
367 | #ifndef CONFIG_MMU | |
368 | #warning "NPTL on non MMU needs fixing" | |
369 | #else | |
370 | @ Make sure our user space atomic helper is restarted | |
371 | @ if it was interrupted in a critical region. Here we | |
372 | @ perform a quick test inline since it should be false | |
373 | @ 99.9999% of the time. The rest is done out of line. | |
374 | cmp r2, #TASK_SIZE | |
375 | blhs kuser_cmpxchg_fixup | |
376 | #endif | |
377 | #endif | |
378 | .endm | |
379 | ||
1da177e4 LT |
380 | .align 5 |
381 | __dabt_usr: | |
ccea7a19 | 382 | usr_entry |
b49c0f24 | 383 | kuser_cmpxchg_check |
1da177e4 LT |
384 | |
385 | @ | |
386 | @ Call the processor-specific abort handler: | |
387 | @ | |
388 | @ r2 - aborted context pc | |
389 | @ r3 - aborted context cpsr | |
390 | @ | |
391 | @ The abort handler must return the aborted address in r0, and | |
392 | @ the fault status register in r1. | |
393 | @ | |
394 | #ifdef MULTI_ABORT | |
395 | ldr r4, .LCprocfns | |
396 | mov lr, pc | |
397 | ldr pc, [r4] | |
398 | #else | |
399 | bl CPU_ABORT_HANDLER | |
400 | #endif | |
401 | ||
402 | @ | |
403 | @ IRQs on, then call the main handler | |
404 | @ | |
1ec42c0c | 405 | enable_irq |
1da177e4 LT |
406 | mov r2, sp |
407 | adr lr, ret_from_exception | |
408 | b do_DataAbort | |
409 | ||
410 | .align 5 | |
411 | __irq_usr: | |
ccea7a19 | 412 | usr_entry |
b49c0f24 | 413 | kuser_cmpxchg_check |
1da177e4 | 414 | |
7ad1bcb2 RK |
415 | #ifdef CONFIG_TRACE_IRQFLAGS |
416 | bl trace_hardirqs_off | |
417 | #endif | |
706fdd9f | 418 | get_thread_info tsk |
1da177e4 | 419 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
420 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
421 | add r7, r8, #1 @ increment it | |
422 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 423 | #endif |
ccea7a19 | 424 | |
187a51ad | 425 | irq_handler |
1da177e4 | 426 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
427 | ldr r0, [tsk, #TI_PREEMPT] |
428 | str r8, [tsk, #TI_PREEMPT] | |
1da177e4 | 429 | teq r0, r7 |
1da177e4 | 430 | strne r0, [r0, -r0] |
1da177e4 | 431 | #endif |
7ad1bcb2 RK |
432 | #ifdef CONFIG_TRACE_IRQFLAGS |
433 | bl trace_hardirqs_on | |
434 | #endif | |
ccea7a19 | 435 | |
1da177e4 LT |
436 | mov why, #0 |
437 | b ret_to_user | |
438 | ||
439 | .ltorg | |
440 | ||
441 | .align 5 | |
442 | __und_usr: | |
ccea7a19 | 443 | usr_entry |
1da177e4 LT |
444 | |
445 | tst r3, #PSR_T_BIT @ Thumb mode? | |
db6ccbb6 | 446 | bne __und_usr_unknown @ ignore FP |
1da177e4 LT |
447 | sub r4, r2, #4 |
448 | ||
449 | @ | |
450 | @ fall through to the emulation code, which returns using r9 if | |
451 | @ it has emulated the instruction, or the more conventional lr | |
452 | @ if we are to treat this as a real undefined instruction | |
453 | @ | |
454 | @ r0 - instruction | |
455 | @ | |
1da177e4 | 456 | adr r9, ret_from_exception |
db6ccbb6 | 457 | adr lr, __und_usr_unknown |
d28a170d | 458 | 1: ldrt r0, [r4] |
1da177e4 LT |
459 | @ |
460 | @ fallthrough to call_fpe | |
461 | @ | |
462 | ||
463 | /* | |
464 | * The out of line fixup for the ldrt above. | |
465 | */ | |
466 | .section .fixup, "ax" | |
467 | 2: mov pc, r9 | |
468 | .previous | |
469 | .section __ex_table,"a" | |
470 | .long 1b, 2b | |
471 | .previous | |
472 | ||
473 | /* | |
474 | * Check whether the instruction is a co-processor instruction. | |
475 | * If yes, we need to call the relevant co-processor handler. | |
476 | * | |
477 | * Note that we don't do a full check here for the co-processor | |
478 | * instructions; all instructions with bit 27 set are well | |
479 | * defined. The only instructions that should fault are the | |
480 | * co-processor instructions. However, we have to watch out | |
481 | * for the ARM6/ARM7 SWI bug. | |
482 | * | |
483 | * Emulators may wish to make use of the following registers: | |
484 | * r0 = instruction opcode. | |
485 | * r2 = PC+4 | |
db6ccbb6 | 486 | * r9 = normal "successful" return address |
1da177e4 | 487 | * r10 = this threads thread_info structure. |
db6ccbb6 | 488 | * lr = unrecognised instruction return address |
1da177e4 LT |
489 | */ |
490 | call_fpe: | |
491 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 | |
492 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) | |
493 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
494 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
495 | #endif | |
496 | moveq pc, lr | |
497 | get_thread_info r10 @ get current thread | |
498 | and r8, r0, #0x00000f00 @ mask out CP number | |
499 | mov r7, #1 | |
500 | add r6, r10, #TI_USED_CP | |
501 | strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] | |
502 | #ifdef CONFIG_IWMMXT | |
503 | @ Test if we need to give access to iWMMXt coprocessors | |
504 | ldr r5, [r10, #TI_FLAGS] | |
505 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
506 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
507 | bcs iwmmxt_task_enable | |
508 | #endif | |
1da177e4 LT |
509 | add pc, pc, r8, lsr #6 |
510 | mov r0, r0 | |
511 | ||
512 | mov pc, lr @ CP#0 | |
513 | b do_fpe @ CP#1 (FPE) | |
514 | b do_fpe @ CP#2 (FPE) | |
515 | mov pc, lr @ CP#3 | |
c17fad11 LB |
516 | #ifdef CONFIG_CRUNCH |
517 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
518 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
519 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
520 | #else | |
1da177e4 LT |
521 | mov pc, lr @ CP#4 |
522 | mov pc, lr @ CP#5 | |
523 | mov pc, lr @ CP#6 | |
c17fad11 | 524 | #endif |
1da177e4 LT |
525 | mov pc, lr @ CP#7 |
526 | mov pc, lr @ CP#8 | |
527 | mov pc, lr @ CP#9 | |
528 | #ifdef CONFIG_VFP | |
529 | b do_vfp @ CP#10 (VFP) | |
530 | b do_vfp @ CP#11 (VFP) | |
531 | #else | |
532 | mov pc, lr @ CP#10 (VFP) | |
533 | mov pc, lr @ CP#11 (VFP) | |
534 | #endif | |
535 | mov pc, lr @ CP#12 | |
536 | mov pc, lr @ CP#13 | |
537 | mov pc, lr @ CP#14 (Debug) | |
538 | mov pc, lr @ CP#15 (Control) | |
539 | ||
540 | do_fpe: | |
5d25ac03 | 541 | enable_irq |
1da177e4 LT |
542 | ldr r4, .LCfp |
543 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
544 | ldr pc, [r4] @ Call FP module USR entry point | |
545 | ||
546 | /* | |
547 | * The FP module is called with these registers set: | |
548 | * r0 = instruction | |
549 | * r2 = PC+4 | |
550 | * r9 = normal "successful" return address | |
551 | * r10 = FP workspace | |
552 | * lr = unrecognised FP instruction return address | |
553 | */ | |
554 | ||
555 | .data | |
556 | ENTRY(fp_enter) | |
db6ccbb6 | 557 | .word no_fp |
1da177e4 LT |
558 | .text |
559 | ||
db6ccbb6 RK |
560 | no_fp: mov pc, lr |
561 | ||
562 | __und_usr_unknown: | |
1da177e4 LT |
563 | mov r0, sp |
564 | adr lr, ret_from_exception | |
565 | b do_undefinstr | |
566 | ||
567 | .align 5 | |
568 | __pabt_usr: | |
ccea7a19 | 569 | usr_entry |
1da177e4 | 570 | |
1ec42c0c | 571 | enable_irq @ Enable interrupts |
1da177e4 LT |
572 | mov r0, r2 @ address (pc) |
573 | mov r1, sp @ regs | |
574 | bl do_PrefetchAbort @ call abort handler | |
575 | /* fall through */ | |
576 | /* | |
577 | * This is the return code to user mode for abort handlers | |
578 | */ | |
579 | ENTRY(ret_from_exception) | |
580 | get_thread_info tsk | |
581 | mov why, #0 | |
582 | b ret_to_user | |
583 | ||
584 | /* | |
585 | * Register switch for ARMv3 and ARMv4 processors | |
586 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
587 | * previous and next are guaranteed not to be the same. | |
588 | */ | |
589 | ENTRY(__switch_to) | |
590 | add ip, r1, #TI_CPU_SAVE | |
591 | ldr r3, [r2, #TI_TP_VALUE] | |
592 | stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack | |
d6551e88 RK |
593 | #ifdef CONFIG_MMU |
594 | ldr r6, [r2, #TI_CPU_DOMAIN] | |
afeb90ca | 595 | #endif |
b876386e | 596 | #if __LINUX_ARM_ARCH__ >= 6 |
43cc1981 | 597 | #ifdef CONFIG_CPU_32v6K |
b876386e RK |
598 | clrex |
599 | #else | |
73394322 | 600 | strex r5, r4, [ip] @ Clear exclusive monitor |
b876386e RK |
601 | #endif |
602 | #endif | |
4b0e07a5 | 603 | #if defined(CONFIG_HAS_TLS_REG) |
2d2669b6 | 604 | mcr p15, 0, r3, c13, c0, 3 @ set TLS register |
4b0e07a5 | 605 | #elif !defined(CONFIG_TLS_REG_EMUL) |
1da177e4 | 606 | mov r4, #0xffff0fff |
2d2669b6 NP |
607 | str r3, [r4, #-15] @ TLS val at 0xffff0ff0 |
608 | #endif | |
afeb90ca | 609 | #ifdef CONFIG_MMU |
1da177e4 | 610 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 611 | #endif |
d6551e88 RK |
612 | mov r5, r0 |
613 | add r4, r2, #TI_CPU_SAVE | |
614 | ldr r0, =thread_notify_head | |
615 | mov r1, #THREAD_NOTIFY_SWITCH | |
616 | bl atomic_notifier_call_chain | |
617 | mov r0, r5 | |
618 | ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously | |
1da177e4 LT |
619 | |
620 | __INIT | |
2d2669b6 NP |
621 | |
622 | /* | |
623 | * User helpers. | |
624 | * | |
625 | * These are segment of kernel provided user code reachable from user space | |
626 | * at a fixed address in kernel memory. This is used to provide user space | |
627 | * with some operations which require kernel help because of unimplemented | |
628 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
629 | * this code to be executed directly in user mode for best efficiency but | |
630 | * which is too intimate with the kernel counter part to be left to user | |
631 | * libraries. In fact this code might even differ from one CPU to another | |
632 | * depending on the available instruction set and restrictions like on | |
633 | * SMP systems. In other words, the kernel reserves the right to change | |
634 | * this code as needed without warning. Only the entry points and their | |
635 | * results are guaranteed to be stable. | |
636 | * | |
637 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
638 | * vector page. New segments (if ever needed) must be added in front of | |
639 | * existing ones. This mechanism should be used only for things that are | |
640 | * really small and justified, and not be abused freely. | |
641 | * | |
642 | * User space is expected to implement those things inline when optimizing | |
643 | * for a processor that has the necessary native support, but only if such | |
644 | * resulting binaries are already to be incompatible with earlier ARM | |
645 | * processors due to the use of unsupported instructions other than what | |
646 | * is provided here. In other words don't make binaries unable to run on | |
647 | * earlier processors just for the sake of not using these kernel helpers | |
648 | * if your compiled code is not going to use the new instructions for other | |
649 | * purpose. | |
650 | */ | |
651 | ||
ba9b5d76 NP |
652 | .macro usr_ret, reg |
653 | #ifdef CONFIG_ARM_THUMB | |
654 | bx \reg | |
655 | #else | |
656 | mov pc, \reg | |
657 | #endif | |
658 | .endm | |
659 | ||
2d2669b6 NP |
660 | .align 5 |
661 | .globl __kuser_helper_start | |
662 | __kuser_helper_start: | |
663 | ||
7c612bfd NP |
664 | /* |
665 | * Reference prototype: | |
666 | * | |
667 | * void __kernel_memory_barrier(void) | |
668 | * | |
669 | * Input: | |
670 | * | |
671 | * lr = return address | |
672 | * | |
673 | * Output: | |
674 | * | |
675 | * none | |
676 | * | |
677 | * Clobbered: | |
678 | * | |
b49c0f24 | 679 | * none |
7c612bfd NP |
680 | * |
681 | * Definition and user space usage example: | |
682 | * | |
683 | * typedef void (__kernel_dmb_t)(void); | |
684 | * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) | |
685 | * | |
686 | * Apply any needed memory barrier to preserve consistency with data modified | |
687 | * manually and __kuser_cmpxchg usage. | |
688 | * | |
689 | * This could be used as follows: | |
690 | * | |
691 | * #define __kernel_dmb() \ | |
692 | * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ | |
6896eec0 | 693 | * : : : "r0", "lr","cc" ) |
7c612bfd NP |
694 | */ |
695 | ||
696 | __kuser_memory_barrier: @ 0xffff0fa0 | |
697 | ||
698 | #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) | |
699 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
700 | #endif | |
ba9b5d76 | 701 | usr_ret lr |
7c612bfd NP |
702 | |
703 | .align 5 | |
704 | ||
2d2669b6 NP |
705 | /* |
706 | * Reference prototype: | |
707 | * | |
708 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
709 | * | |
710 | * Input: | |
711 | * | |
712 | * r0 = oldval | |
713 | * r1 = newval | |
714 | * r2 = ptr | |
715 | * lr = return address | |
716 | * | |
717 | * Output: | |
718 | * | |
719 | * r0 = returned value (zero or non-zero) | |
720 | * C flag = set if r0 == 0, clear if r0 != 0 | |
721 | * | |
722 | * Clobbered: | |
723 | * | |
724 | * r3, ip, flags | |
725 | * | |
726 | * Definition and user space usage example: | |
727 | * | |
728 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
729 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
730 | * | |
731 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
732 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
733 | * The C flag is also set if *ptr was changed to allow for assembly | |
734 | * optimization in the calling code. | |
735 | * | |
5964eae8 NP |
736 | * Notes: |
737 | * | |
738 | * - This routine already includes memory barriers as needed. | |
739 | * | |
2d2669b6 NP |
740 | * For example, a user space atomic_add implementation could look like this: |
741 | * | |
742 | * #define atomic_add(ptr, val) \ | |
743 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
744 | * register unsigned int __result asm("r1"); \ | |
745 | * asm volatile ( \ | |
746 | * "1: @ atomic_add\n\t" \ | |
747 | * "ldr r0, [r2]\n\t" \ | |
748 | * "mov r3, #0xffff0fff\n\t" \ | |
749 | * "add lr, pc, #4\n\t" \ | |
750 | * "add r1, r0, %2\n\t" \ | |
751 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
752 | * "bcc 1b" \ | |
753 | * : "=&r" (__result) \ | |
754 | * : "r" (__ptr), "rIL" (val) \ | |
755 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
756 | * __result; }) | |
757 | */ | |
758 | ||
759 | __kuser_cmpxchg: @ 0xffff0fc0 | |
760 | ||
dcef1f63 | 761 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 762 | |
dcef1f63 NP |
763 | /* |
764 | * Poor you. No fast solution possible... | |
765 | * The kernel itself must perform the operation. | |
766 | * A special ghost syscall is used for that (see traps.c). | |
767 | */ | |
5e097445 NP |
768 | stmfd sp!, {r7, lr} |
769 | mov r7, #0xff00 @ 0xfff0 into r7 for EABI | |
770 | orr r7, r7, #0xf0 | |
dcef1f63 | 771 | swi #0x9ffff0 |
5e097445 | 772 | ldmfd sp!, {r7, pc} |
dcef1f63 NP |
773 | |
774 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 775 | |
b49c0f24 NP |
776 | #ifdef CONFIG_MMU |
777 | ||
2d2669b6 | 778 | /* |
b49c0f24 NP |
779 | * The only thing that can break atomicity in this cmpxchg |
780 | * implementation is either an IRQ or a data abort exception | |
781 | * causing another process/thread to be scheduled in the middle | |
782 | * of the critical sequence. To prevent this, code is added to | |
783 | * the IRQ and data abort exception handlers to set the pc back | |
784 | * to the beginning of the critical section if it is found to be | |
785 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 786 | */ |
b49c0f24 NP |
787 | 1: ldr r3, [r2] @ load current val |
788 | subs r3, r3, r0 @ compare with oldval | |
789 | 2: streq r1, [r2] @ store newval if eq | |
790 | rsbs r0, r3, #0 @ set return val and C flag | |
791 | usr_ret lr | |
792 | ||
793 | .text | |
794 | kuser_cmpxchg_fixup: | |
795 | @ Called from kuser_cmpxchg_check macro. | |
796 | @ r2 = address of interrupted insn (must be preserved). | |
797 | @ sp = saved regs. r7 and r8 are clobbered. | |
798 | @ 1b = first critical insn, 2b = last critical insn. | |
799 | @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b. | |
800 | mov r7, #0xffff0fff | |
801 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
802 | subs r8, r2, r7 | |
803 | rsbcss r8, r8, #(2b - 1b) | |
804 | strcs r7, [sp, #S_PC] | |
805 | mov pc, lr | |
806 | .previous | |
807 | ||
49bca4c2 NP |
808 | #else |
809 | #warning "NPTL on non MMU needs fixing" | |
810 | mov r0, #-1 | |
811 | adds r0, r0, #0 | |
ba9b5d76 | 812 | usr_ret lr |
b49c0f24 | 813 | #endif |
2d2669b6 NP |
814 | |
815 | #else | |
816 | ||
7c612bfd NP |
817 | #ifdef CONFIG_SMP |
818 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
819 | #endif | |
b49c0f24 | 820 | 1: ldrex r3, [r2] |
2d2669b6 NP |
821 | subs r3, r3, r0 |
822 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
823 | teqeq r3, #1 |
824 | beq 1b | |
2d2669b6 | 825 | rsbs r0, r3, #0 |
b49c0f24 | 826 | /* beware -- each __kuser slot must be 8 instructions max */ |
7c612bfd | 827 | #ifdef CONFIG_SMP |
b49c0f24 NP |
828 | b __kuser_memory_barrier |
829 | #else | |
ba9b5d76 | 830 | usr_ret lr |
b49c0f24 | 831 | #endif |
2d2669b6 NP |
832 | |
833 | #endif | |
834 | ||
835 | .align 5 | |
836 | ||
837 | /* | |
838 | * Reference prototype: | |
839 | * | |
840 | * int __kernel_get_tls(void) | |
841 | * | |
842 | * Input: | |
843 | * | |
844 | * lr = return address | |
845 | * | |
846 | * Output: | |
847 | * | |
848 | * r0 = TLS value | |
849 | * | |
850 | * Clobbered: | |
851 | * | |
b49c0f24 | 852 | * none |
2d2669b6 NP |
853 | * |
854 | * Definition and user space usage example: | |
855 | * | |
856 | * typedef int (__kernel_get_tls_t)(void); | |
857 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
858 | * | |
859 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
860 | * | |
861 | * This could be used as follows: | |
862 | * | |
863 | * #define __kernel_get_tls() \ | |
864 | * ({ register unsigned int __val asm("r0"); \ | |
865 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
866 | * : "=r" (__val) : : "lr","cc" ); \ | |
867 | * __val; }) | |
868 | */ | |
869 | ||
870 | __kuser_get_tls: @ 0xffff0fe0 | |
871 | ||
4b0e07a5 | 872 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) |
2d2669b6 | 873 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 |
2d2669b6 | 874 | #else |
2d2669b6 | 875 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register |
2d2669b6 | 876 | #endif |
ba9b5d76 | 877 | usr_ret lr |
2d2669b6 NP |
878 | |
879 | .rep 5 | |
880 | .word 0 @ pad up to __kuser_helper_version | |
881 | .endr | |
882 | ||
883 | /* | |
884 | * Reference declaration: | |
885 | * | |
886 | * extern unsigned int __kernel_helper_version; | |
887 | * | |
888 | * Definition and user space usage example: | |
889 | * | |
890 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
891 | * | |
892 | * User space may read this to determine the curent number of helpers | |
893 | * available. | |
894 | */ | |
895 | ||
896 | __kuser_helper_version: @ 0xffff0ffc | |
897 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
898 | ||
899 | .globl __kuser_helper_end | |
900 | __kuser_helper_end: | |
901 | ||
902 | ||
1da177e4 LT |
903 | /* |
904 | * Vector stubs. | |
905 | * | |
7933523d RK |
906 | * This code is copied to 0xffff0200 so we can use branches in the |
907 | * vectors, rather than ldr's. Note that this code must not | |
908 | * exceed 0x300 bytes. | |
1da177e4 LT |
909 | * |
910 | * Common stub entry macro: | |
911 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
912 | * |
913 | * SP points to a minimal amount of processor-private memory, the address | |
914 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 915 | */ |
b7ec4795 | 916 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
917 | .align 5 |
918 | ||
919 | vector_\name: | |
1da177e4 LT |
920 | .if \correction |
921 | sub lr, lr, #\correction | |
922 | .endif | |
ccea7a19 RK |
923 | |
924 | @ | |
925 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
926 | @ (parent CPSR) | |
927 | @ | |
928 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 929 | mrs lr, spsr |
ccea7a19 RK |
930 | str lr, [sp, #8] @ save spsr |
931 | ||
1da177e4 | 932 | @ |
ccea7a19 | 933 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 934 | @ |
ccea7a19 | 935 | mrs r0, cpsr |
b7ec4795 | 936 | eor r0, r0, #(\mode ^ SVC_MODE) |
ccea7a19 | 937 | msr spsr_cxsf, r0 |
1da177e4 | 938 | |
ccea7a19 RK |
939 | @ |
940 | @ the branch table must immediately follow this code | |
941 | @ | |
ccea7a19 | 942 | and lr, lr, #0x0f |
b7ec4795 | 943 | mov r0, sp |
1da177e4 | 944 | ldr lr, [pc, lr, lsl #2] |
ccea7a19 | 945 | movs pc, lr @ branch to handler in SVC mode |
1da177e4 LT |
946 | .endm |
947 | ||
7933523d | 948 | .globl __stubs_start |
1da177e4 LT |
949 | __stubs_start: |
950 | /* | |
951 | * Interrupt dispatcher | |
952 | */ | |
b7ec4795 | 953 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
954 | |
955 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
956 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
957 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
958 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
959 | .long __irq_invalid @ 4 | |
960 | .long __irq_invalid @ 5 | |
961 | .long __irq_invalid @ 6 | |
962 | .long __irq_invalid @ 7 | |
963 | .long __irq_invalid @ 8 | |
964 | .long __irq_invalid @ 9 | |
965 | .long __irq_invalid @ a | |
966 | .long __irq_invalid @ b | |
967 | .long __irq_invalid @ c | |
968 | .long __irq_invalid @ d | |
969 | .long __irq_invalid @ e | |
970 | .long __irq_invalid @ f | |
971 | ||
972 | /* | |
973 | * Data abort dispatcher | |
974 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
975 | */ | |
b7ec4795 | 976 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
977 | |
978 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
979 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
980 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
981 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
982 | .long __dabt_invalid @ 4 | |
983 | .long __dabt_invalid @ 5 | |
984 | .long __dabt_invalid @ 6 | |
985 | .long __dabt_invalid @ 7 | |
986 | .long __dabt_invalid @ 8 | |
987 | .long __dabt_invalid @ 9 | |
988 | .long __dabt_invalid @ a | |
989 | .long __dabt_invalid @ b | |
990 | .long __dabt_invalid @ c | |
991 | .long __dabt_invalid @ d | |
992 | .long __dabt_invalid @ e | |
993 | .long __dabt_invalid @ f | |
994 | ||
995 | /* | |
996 | * Prefetch abort dispatcher | |
997 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
998 | */ | |
b7ec4795 | 999 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1000 | |
1001 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1002 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1003 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1004 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1005 | .long __pabt_invalid @ 4 | |
1006 | .long __pabt_invalid @ 5 | |
1007 | .long __pabt_invalid @ 6 | |
1008 | .long __pabt_invalid @ 7 | |
1009 | .long __pabt_invalid @ 8 | |
1010 | .long __pabt_invalid @ 9 | |
1011 | .long __pabt_invalid @ a | |
1012 | .long __pabt_invalid @ b | |
1013 | .long __pabt_invalid @ c | |
1014 | .long __pabt_invalid @ d | |
1015 | .long __pabt_invalid @ e | |
1016 | .long __pabt_invalid @ f | |
1017 | ||
1018 | /* | |
1019 | * Undef instr entry dispatcher | |
1020 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1021 | */ | |
b7ec4795 | 1022 | vector_stub und, UND_MODE |
1da177e4 LT |
1023 | |
1024 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1025 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1026 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1027 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1028 | .long __und_invalid @ 4 | |
1029 | .long __und_invalid @ 5 | |
1030 | .long __und_invalid @ 6 | |
1031 | .long __und_invalid @ 7 | |
1032 | .long __und_invalid @ 8 | |
1033 | .long __und_invalid @ 9 | |
1034 | .long __und_invalid @ a | |
1035 | .long __und_invalid @ b | |
1036 | .long __und_invalid @ c | |
1037 | .long __und_invalid @ d | |
1038 | .long __und_invalid @ e | |
1039 | .long __und_invalid @ f | |
1040 | ||
1041 | .align 5 | |
1042 | ||
1043 | /*============================================================================= | |
1044 | * Undefined FIQs | |
1045 | *----------------------------------------------------------------------------- | |
1046 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1047 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1048 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1049 | * damage alert! I don't think that we can execute any code in here in any | |
1050 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1051 | * get out of that mode without clobbering one register. | |
1052 | */ | |
1053 | vector_fiq: | |
1054 | disable_fiq | |
1055 | subs pc, lr, #4 | |
1056 | ||
1057 | /*============================================================================= | |
1058 | * Address exception handler | |
1059 | *----------------------------------------------------------------------------- | |
1060 | * These aren't too critical. | |
1061 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1062 | */ | |
1063 | ||
1064 | vector_addrexcptn: | |
1065 | b vector_addrexcptn | |
1066 | ||
1067 | /* | |
1068 | * We group all the following data together to optimise | |
1069 | * for CPUs with separate I & D caches. | |
1070 | */ | |
1071 | .align 5 | |
1072 | ||
1073 | .LCvswi: | |
1074 | .word vector_swi | |
1075 | ||
7933523d | 1076 | .globl __stubs_end |
1da177e4 LT |
1077 | __stubs_end: |
1078 | ||
7933523d | 1079 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1080 | |
7933523d RK |
1081 | .globl __vectors_start |
1082 | __vectors_start: | |
1da177e4 | 1083 | swi SYS_ERROR0 |
7933523d RK |
1084 | b vector_und + stubs_offset |
1085 | ldr pc, .LCvswi + stubs_offset | |
1086 | b vector_pabt + stubs_offset | |
1087 | b vector_dabt + stubs_offset | |
1088 | b vector_addrexcptn + stubs_offset | |
1089 | b vector_irq + stubs_offset | |
1090 | b vector_fiq + stubs_offset | |
1091 | ||
1092 | .globl __vectors_end | |
1093 | __vectors_end: | |
1da177e4 LT |
1094 | |
1095 | .data | |
1096 | ||
1da177e4 LT |
1097 | .globl cr_alignment |
1098 | .globl cr_no_alignment | |
1099 | cr_alignment: | |
1100 | .space 4 | |
1101 | cr_no_alignment: | |
1102 | .space 4 |