Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
f09b9979 | 18 | #include <asm/memory.h> |
753790e7 RK |
19 | #include <asm/glue-df.h> |
20 | #include <asm/glue-pf.h> | |
1da177e4 | 21 | #include <asm/vfpmacros.h> |
a09e64fb | 22 | #include <mach/entry-macro.S> |
d6551e88 | 23 | #include <asm/thread_notify.h> |
c4c5716e | 24 | #include <asm/unwind.h> |
cc20d429 | 25 | #include <asm/unistd.h> |
f159f4ed | 26 | #include <asm/tls.h> |
1da177e4 LT |
27 | |
28 | #include "entry-header.S" | |
cd544ce7 | 29 | #include <asm/entry-macro-multi.S> |
1da177e4 | 30 | |
187a51ad RK |
31 | /* |
32 | * Interrupt handling. Preserves r7, r8, r9 | |
33 | */ | |
34 | .macro irq_handler | |
52108641 | 35 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
36 | ldr r5, =handle_arch_irq | |
37 | mov r0, sp | |
38 | ldr r5, [r5] | |
39 | adr lr, BSYM(9997f) | |
40 | teq r5, #0 | |
41 | movne pc, r5 | |
37ee16ae | 42 | #endif |
cd544ce7 | 43 | arch_irq_handler_default |
f00ec48f | 44 | 9997: |
187a51ad RK |
45 | .endm |
46 | ||
ac8b9c1c | 47 | .macro pabt_helper |
8b418616 | 48 | @ PABORT handler takes fault address in r4 |
ac8b9c1c | 49 | #ifdef MULTI_PABORT |
0402bece | 50 | ldr ip, .LCprocfns |
ac8b9c1c | 51 | mov lr, pc |
0402bece | 52 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
ac8b9c1c RK |
53 | #else |
54 | bl CPU_PABORT_HANDLER | |
55 | #endif | |
56 | .endm | |
57 | ||
58 | .macro dabt_helper | |
b059bdc3 RK |
59 | mov r2, r4 |
60 | mov r3, r5 | |
ac8b9c1c RK |
61 | |
62 | @ | |
63 | @ Call the processor-specific abort handler: | |
64 | @ | |
65 | @ r2 - aborted context pc | |
66 | @ r3 - aborted context cpsr | |
67 | @ | |
68 | @ The abort handler must return the aborted address in r0, and | |
69 | @ the fault status register in r1. r9 must be preserved. | |
70 | @ | |
71 | #ifdef MULTI_DABORT | |
0402bece | 72 | ldr ip, .LCprocfns |
ac8b9c1c | 73 | mov lr, pc |
0402bece | 74 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
ac8b9c1c RK |
75 | #else |
76 | bl CPU_DABORT_HANDLER | |
77 | #endif | |
78 | .endm | |
79 | ||
785d3cd2 NP |
80 | #ifdef CONFIG_KPROBES |
81 | .section .kprobes.text,"ax",%progbits | |
82 | #else | |
83 | .text | |
84 | #endif | |
85 | ||
1da177e4 LT |
86 | /* |
87 | * Invalid mode handlers | |
88 | */ | |
ccea7a19 RK |
89 | .macro inv_entry, reason |
90 | sub sp, sp, #S_FRAME_SIZE | |
b86040a5 CM |
91 | ARM( stmib sp, {r1 - lr} ) |
92 | THUMB( stmia sp, {r0 - r12} ) | |
93 | THUMB( str sp, [sp, #S_SP] ) | |
94 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
95 | mov r1, #\reason |
96 | .endm | |
97 | ||
98 | __pabt_invalid: | |
ccea7a19 RK |
99 | inv_entry BAD_PREFETCH |
100 | b common_invalid | |
93ed3970 | 101 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
102 | |
103 | __dabt_invalid: | |
ccea7a19 RK |
104 | inv_entry BAD_DATA |
105 | b common_invalid | |
93ed3970 | 106 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
107 | |
108 | __irq_invalid: | |
ccea7a19 RK |
109 | inv_entry BAD_IRQ |
110 | b common_invalid | |
93ed3970 | 111 | ENDPROC(__irq_invalid) |
1da177e4 LT |
112 | |
113 | __und_invalid: | |
ccea7a19 RK |
114 | inv_entry BAD_UNDEFINSTR |
115 | ||
116 | @ | |
117 | @ XXX fall through to common_invalid | |
118 | @ | |
119 | ||
120 | @ | |
121 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
122 | @ | |
123 | common_invalid: | |
124 | zero_fp | |
125 | ||
126 | ldmia r0, {r4 - r6} | |
127 | add r0, sp, #S_PC @ here for interlock avoidance | |
128 | mov r7, #-1 @ "" "" "" "" | |
129 | str r4, [sp] @ save preserved r0 | |
130 | stmia r0, {r5 - r7} @ lr_<exception>, | |
131 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 132 | |
1da177e4 | 133 | mov r0, sp |
1da177e4 | 134 | b bad_mode |
93ed3970 | 135 | ENDPROC(__und_invalid) |
1da177e4 LT |
136 | |
137 | /* | |
138 | * SVC mode handlers | |
139 | */ | |
2dede2d8 NP |
140 | |
141 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
142 | #define SPFIX(code...) code | |
143 | #else | |
144 | #define SPFIX(code...) | |
145 | #endif | |
146 | ||
d30a0c8b | 147 | .macro svc_entry, stack_hole=0 |
c4c5716e CM |
148 | UNWIND(.fnstart ) |
149 | UNWIND(.save {r0 - pc} ) | |
b86040a5 CM |
150 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
151 | #ifdef CONFIG_THUMB2_KERNEL | |
152 | SPFIX( str r0, [sp] ) @ temporarily saved | |
153 | SPFIX( mov r0, sp ) | |
154 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
155 | SPFIX( ldr r0, [sp] ) @ restored | |
156 | #else | |
2dede2d8 | 157 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
158 | #endif |
159 | SPFIX( subeq sp, sp, #4 ) | |
160 | stmia sp, {r1 - r12} | |
ccea7a19 | 161 | |
b059bdc3 RK |
162 | ldmia r0, {r3 - r5} |
163 | add r7, sp, #S_SP - 4 @ here for interlock avoidance | |
164 | mov r6, #-1 @ "" "" "" "" | |
165 | add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) | |
166 | SPFIX( addeq r2, r2, #4 ) | |
167 | str r3, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
168 | @ from the exception stack |
169 | ||
b059bdc3 | 170 | mov r3, lr |
1da177e4 LT |
171 | |
172 | @ | |
173 | @ We are now ready to fill in the remaining blanks on the stack: | |
174 | @ | |
b059bdc3 RK |
175 | @ r2 - sp_svc |
176 | @ r3 - lr_svc | |
177 | @ r4 - lr_<exception>, already fixed up for correct return/restart | |
178 | @ r5 - spsr_<exception> | |
179 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 | 180 | @ |
b059bdc3 | 181 | stmia r7, {r2 - r6} |
1da177e4 LT |
182 | .endm |
183 | ||
184 | .align 5 | |
185 | __dabt_svc: | |
ccea7a19 | 186 | svc_entry |
1da177e4 | 187 | |
02fe2845 RK |
188 | #ifdef CONFIG_TRACE_IRQFLAGS |
189 | bl trace_hardirqs_off | |
190 | #endif | |
1da177e4 | 191 | |
ac8b9c1c | 192 | dabt_helper |
1da177e4 LT |
193 | |
194 | @ | |
02fe2845 | 195 | @ call main handler |
1da177e4 | 196 | @ |
1da177e4 LT |
197 | mov r2, sp |
198 | bl do_DataAbort | |
199 | ||
200 | @ | |
201 | @ IRQs off again before pulling preserved data off the stack | |
202 | @ | |
ac78884e | 203 | disable_irq_notrace |
1da177e4 LT |
204 | |
205 | @ | |
206 | @ restore SPSR and restart the instruction | |
207 | @ | |
b059bdc3 | 208 | ldr r5, [sp, #S_PSR] |
02fe2845 RK |
209 | #ifdef CONFIG_TRACE_IRQFLAGS |
210 | tst r5, #PSR_I_BIT | |
211 | bleq trace_hardirqs_on | |
212 | tst r5, #PSR_I_BIT | |
213 | blne trace_hardirqs_off | |
214 | #endif | |
b059bdc3 | 215 | svc_exit r5 @ return from exception |
c4c5716e | 216 | UNWIND(.fnend ) |
93ed3970 | 217 | ENDPROC(__dabt_svc) |
1da177e4 LT |
218 | |
219 | .align 5 | |
220 | __irq_svc: | |
ccea7a19 RK |
221 | svc_entry |
222 | ||
ac78884e RK |
223 | #ifdef CONFIG_TRACE_IRQFLAGS |
224 | bl trace_hardirqs_off | |
225 | #endif | |
ccea7a19 | 226 | |
187a51ad | 227 | irq_handler |
1613cc11 | 228 | |
1da177e4 | 229 | #ifdef CONFIG_PREEMPT |
1613cc11 RK |
230 | get_thread_info tsk |
231 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
706fdd9f | 232 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
233 | teq r8, #0 @ if preempt count != 0 |
234 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
235 | tst r0, #_TIF_NEED_RESCHED |
236 | blne svc_preempt | |
1da177e4 | 237 | #endif |
b059bdc3 | 238 | ldr r5, [sp, #S_PSR] |
7ad1bcb2 | 239 | #ifdef CONFIG_TRACE_IRQFLAGS |
fbab1c80 RK |
240 | @ The parent context IRQs must have been enabled to get here in |
241 | @ the first place, so there's no point checking the PSR I bit. | |
242 | bl trace_hardirqs_on | |
7ad1bcb2 | 243 | #endif |
b059bdc3 | 244 | svc_exit r5 @ return from exception |
c4c5716e | 245 | UNWIND(.fnend ) |
93ed3970 | 246 | ENDPROC(__irq_svc) |
1da177e4 LT |
247 | |
248 | .ltorg | |
249 | ||
250 | #ifdef CONFIG_PREEMPT | |
251 | svc_preempt: | |
28fab1a2 | 252 | mov r8, lr |
1da177e4 | 253 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 254 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 255 | tst r0, #_TIF_NEED_RESCHED |
28fab1a2 | 256 | moveq pc, r8 @ go again |
1da177e4 LT |
257 | b 1b |
258 | #endif | |
259 | ||
260 | .align 5 | |
261 | __und_svc: | |
d30a0c8b NP |
262 | #ifdef CONFIG_KPROBES |
263 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
264 | @ it obviously needs free stack space which then will belong to | |
265 | @ the saved context. | |
266 | svc_entry 64 | |
267 | #else | |
ccea7a19 | 268 | svc_entry |
d30a0c8b | 269 | #endif |
1da177e4 | 270 | |
df295df6 RK |
271 | #ifdef CONFIG_TRACE_IRQFLAGS |
272 | bl trace_hardirqs_off | |
273 | #endif | |
274 | ||
1da177e4 LT |
275 | @ |
276 | @ call emulation code, which returns using r9 if it has emulated | |
277 | @ the instruction, or the more conventional lr if we are to treat | |
278 | @ this as a real undefined instruction | |
279 | @ | |
280 | @ r0 - instruction | |
281 | @ | |
83e686ea | 282 | #ifndef CONFIG_THUMB2_KERNEL |
b059bdc3 | 283 | ldr r0, [r4, #-4] |
83e686ea | 284 | #else |
b059bdc3 | 285 | ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 |
83e686ea CM |
286 | and r9, r0, #0xf800 |
287 | cmp r9, #0xe800 @ 32-bit instruction if xx >= 0 | |
b059bdc3 | 288 | ldrhhs r9, [r4] @ bottom 16 bits |
83e686ea CM |
289 | orrhs r0, r9, r0, lsl #16 |
290 | #endif | |
b86040a5 | 291 | adr r9, BSYM(1f) |
b059bdc3 | 292 | mov r2, r4 |
1da177e4 LT |
293 | bl call_fpe |
294 | ||
295 | mov r0, sp @ struct pt_regs *regs | |
296 | bl do_undefinstr | |
297 | ||
298 | @ | |
299 | @ IRQs off again before pulling preserved data off the stack | |
300 | @ | |
ac78884e | 301 | 1: disable_irq_notrace |
1da177e4 LT |
302 | |
303 | @ | |
304 | @ restore SPSR and restart the instruction | |
305 | @ | |
b059bdc3 | 306 | ldr r5, [sp, #S_PSR] @ Get SVC cpsr |
df295df6 RK |
307 | #ifdef CONFIG_TRACE_IRQFLAGS |
308 | tst r5, #PSR_I_BIT | |
309 | bleq trace_hardirqs_on | |
310 | tst r5, #PSR_I_BIT | |
311 | blne trace_hardirqs_off | |
312 | #endif | |
b059bdc3 | 313 | svc_exit r5 @ return from exception |
c4c5716e | 314 | UNWIND(.fnend ) |
93ed3970 | 315 | ENDPROC(__und_svc) |
1da177e4 LT |
316 | |
317 | .align 5 | |
318 | __pabt_svc: | |
ccea7a19 | 319 | svc_entry |
1da177e4 | 320 | |
02fe2845 RK |
321 | #ifdef CONFIG_TRACE_IRQFLAGS |
322 | bl trace_hardirqs_off | |
323 | #endif | |
1da177e4 | 324 | |
ac8b9c1c | 325 | pabt_helper |
4fb28474 | 326 | mov r2, sp @ regs |
1da177e4 LT |
327 | bl do_PrefetchAbort @ call abort handler |
328 | ||
329 | @ | |
330 | @ IRQs off again before pulling preserved data off the stack | |
331 | @ | |
ac78884e | 332 | disable_irq_notrace |
1da177e4 LT |
333 | |
334 | @ | |
335 | @ restore SPSR and restart the instruction | |
336 | @ | |
b059bdc3 | 337 | ldr r5, [sp, #S_PSR] |
02fe2845 RK |
338 | #ifdef CONFIG_TRACE_IRQFLAGS |
339 | tst r5, #PSR_I_BIT | |
340 | bleq trace_hardirqs_on | |
341 | tst r5, #PSR_I_BIT | |
342 | blne trace_hardirqs_off | |
343 | #endif | |
b059bdc3 | 344 | svc_exit r5 @ return from exception |
c4c5716e | 345 | UNWIND(.fnend ) |
93ed3970 | 346 | ENDPROC(__pabt_svc) |
1da177e4 LT |
347 | |
348 | .align 5 | |
49f680ea RK |
349 | .LCcralign: |
350 | .word cr_alignment | |
48d7927b | 351 | #ifdef MULTI_DABORT |
1da177e4 LT |
352 | .LCprocfns: |
353 | .word processor | |
354 | #endif | |
355 | .LCfp: | |
356 | .word fp_enter | |
1da177e4 LT |
357 | |
358 | /* | |
359 | * User mode handlers | |
2dede2d8 NP |
360 | * |
361 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 362 | */ |
2dede2d8 NP |
363 | |
364 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
365 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
366 | #endif | |
367 | ||
ccea7a19 | 368 | .macro usr_entry |
c4c5716e CM |
369 | UNWIND(.fnstart ) |
370 | UNWIND(.cantunwind ) @ don't unwind the user space | |
ccea7a19 | 371 | sub sp, sp, #S_FRAME_SIZE |
b86040a5 CM |
372 | ARM( stmib sp, {r1 - r12} ) |
373 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 | 374 | |
b059bdc3 | 375 | ldmia r0, {r3 - r5} |
ccea7a19 | 376 | add r0, sp, #S_PC @ here for interlock avoidance |
b059bdc3 | 377 | mov r6, #-1 @ "" "" "" "" |
ccea7a19 | 378 | |
b059bdc3 | 379 | str r3, [sp] @ save the "real" r0 copied |
ccea7a19 | 380 | @ from the exception stack |
1da177e4 LT |
381 | |
382 | @ | |
383 | @ We are now ready to fill in the remaining blanks on the stack: | |
384 | @ | |
b059bdc3 RK |
385 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
386 | @ r5 - spsr_<exception> | |
387 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 LT |
388 | @ |
389 | @ Also, separately save sp_usr and lr_usr | |
390 | @ | |
b059bdc3 | 391 | stmia r0, {r4 - r6} |
b86040a5 CM |
392 | ARM( stmdb r0, {sp, lr}^ ) |
393 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 LT |
394 | |
395 | @ | |
396 | @ Enable the alignment trap while in kernel mode | |
397 | @ | |
49f680ea | 398 | alignment_trap r0 |
1da177e4 LT |
399 | |
400 | @ | |
401 | @ Clear FP to mark the first stack frame | |
402 | @ | |
403 | zero_fp | |
404 | .endm | |
405 | ||
b49c0f24 NP |
406 | .macro kuser_cmpxchg_check |
407 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
408 | #ifndef CONFIG_MMU | |
409 | #warning "NPTL on non MMU needs fixing" | |
410 | #else | |
411 | @ Make sure our user space atomic helper is restarted | |
412 | @ if it was interrupted in a critical region. Here we | |
413 | @ perform a quick test inline since it should be false | |
414 | @ 99.9999% of the time. The rest is done out of line. | |
b059bdc3 | 415 | cmp r4, #TASK_SIZE |
b49c0f24 NP |
416 | blhs kuser_cmpxchg_fixup |
417 | #endif | |
418 | #endif | |
419 | .endm | |
420 | ||
1da177e4 LT |
421 | .align 5 |
422 | __dabt_usr: | |
ccea7a19 | 423 | usr_entry |
bc089602 RK |
424 | |
425 | #ifdef CONFIG_IRQSOFF_TRACER | |
426 | bl trace_hardirqs_off | |
427 | #endif | |
428 | ||
b49c0f24 | 429 | kuser_cmpxchg_check |
ac8b9c1c | 430 | dabt_helper |
1da177e4 | 431 | |
1da177e4 | 432 | mov r2, sp |
b86040a5 | 433 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 434 | b do_DataAbort |
c4c5716e | 435 | UNWIND(.fnend ) |
93ed3970 | 436 | ENDPROC(__dabt_usr) |
1da177e4 LT |
437 | |
438 | .align 5 | |
439 | __irq_usr: | |
ccea7a19 | 440 | usr_entry |
1da177e4 | 441 | |
9fc2552a ML |
442 | #ifdef CONFIG_IRQSOFF_TRACER |
443 | bl trace_hardirqs_off | |
444 | #endif | |
445 | ||
bc089602 | 446 | kuser_cmpxchg_check |
187a51ad | 447 | irq_handler |
1613cc11 | 448 | get_thread_info tsk |
1da177e4 | 449 | mov why, #0 |
9fc2552a | 450 | b ret_to_user_from_irq |
c4c5716e | 451 | UNWIND(.fnend ) |
93ed3970 | 452 | ENDPROC(__irq_usr) |
1da177e4 LT |
453 | |
454 | .ltorg | |
455 | ||
456 | .align 5 | |
457 | __und_usr: | |
ccea7a19 | 458 | usr_entry |
bc089602 RK |
459 | |
460 | #ifdef CONFIG_IRQSOFF_TRACER | |
461 | bl trace_hardirqs_off | |
462 | #endif | |
463 | ||
b059bdc3 RK |
464 | mov r2, r4 |
465 | mov r3, r5 | |
1da177e4 | 466 | |
1da177e4 LT |
467 | @ |
468 | @ fall through to the emulation code, which returns using r9 if | |
469 | @ it has emulated the instruction, or the more conventional lr | |
470 | @ if we are to treat this as a real undefined instruction | |
471 | @ | |
472 | @ r0 - instruction | |
473 | @ | |
b86040a5 CM |
474 | adr r9, BSYM(ret_from_exception) |
475 | adr lr, BSYM(__und_usr_unknown) | |
cb170a45 | 476 | tst r3, #PSR_T_BIT @ Thumb mode? |
b86040a5 | 477 | itet eq @ explicit IT needed for the 1f label |
cb170a45 PB |
478 | subeq r4, r2, #4 @ ARM instr at LR - 4 |
479 | subne r4, r2, #2 @ Thumb instr at LR - 2 | |
480 | 1: ldreqt r0, [r4] | |
26584853 CM |
481 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
482 | reveq r0, r0 @ little endian instruction | |
483 | #endif | |
cb170a45 PB |
484 | beq call_fpe |
485 | @ Thumb instruction | |
486 | #if __LINUX_ARM_ARCH__ >= 7 | |
b86040a5 CM |
487 | 2: |
488 | ARM( ldrht r5, [r4], #2 ) | |
489 | THUMB( ldrht r5, [r4] ) | |
490 | THUMB( add r4, r4, #2 ) | |
cb170a45 PB |
491 | and r0, r5, #0xf800 @ mask bits 111x x... .... .... |
492 | cmp r0, #0xe800 @ 32bit instruction if xx != 0 | |
493 | blo __und_usr_unknown | |
494 | 3: ldrht r0, [r4] | |
495 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 | |
496 | orr r0, r0, r5, lsl #16 | |
497 | #else | |
498 | b __und_usr_unknown | |
499 | #endif | |
c4c5716e | 500 | UNWIND(.fnend ) |
93ed3970 | 501 | ENDPROC(__und_usr) |
cb170a45 | 502 | |
1da177e4 LT |
503 | @ |
504 | @ fallthrough to call_fpe | |
505 | @ | |
506 | ||
507 | /* | |
508 | * The out of line fixup for the ldrt above. | |
509 | */ | |
4260415f | 510 | .pushsection .fixup, "ax" |
cb170a45 | 511 | 4: mov pc, r9 |
4260415f RK |
512 | .popsection |
513 | .pushsection __ex_table,"a" | |
cb170a45 PB |
514 | .long 1b, 4b |
515 | #if __LINUX_ARM_ARCH__ >= 7 | |
516 | .long 2b, 4b | |
517 | .long 3b, 4b | |
518 | #endif | |
4260415f | 519 | .popsection |
1da177e4 LT |
520 | |
521 | /* | |
522 | * Check whether the instruction is a co-processor instruction. | |
523 | * If yes, we need to call the relevant co-processor handler. | |
524 | * | |
525 | * Note that we don't do a full check here for the co-processor | |
526 | * instructions; all instructions with bit 27 set are well | |
527 | * defined. The only instructions that should fault are the | |
528 | * co-processor instructions. However, we have to watch out | |
529 | * for the ARM6/ARM7 SWI bug. | |
530 | * | |
b5872db4 CM |
531 | * NEON is a special case that has to be handled here. Not all |
532 | * NEON instructions are co-processor instructions, so we have | |
533 | * to make a special case of checking for them. Plus, there's | |
534 | * five groups of them, so we have a table of mask/opcode pairs | |
535 | * to check against, and if any match then we branch off into the | |
536 | * NEON handler code. | |
537 | * | |
1da177e4 LT |
538 | * Emulators may wish to make use of the following registers: |
539 | * r0 = instruction opcode. | |
540 | * r2 = PC+4 | |
db6ccbb6 | 541 | * r9 = normal "successful" return address |
1da177e4 | 542 | * r10 = this threads thread_info structure. |
db6ccbb6 | 543 | * lr = unrecognised instruction return address |
1da177e4 | 544 | */ |
cb170a45 PB |
545 | @ |
546 | @ Fall-through from Thumb-2 __und_usr | |
547 | @ | |
548 | #ifdef CONFIG_NEON | |
549 | adr r6, .LCneon_thumb_opcodes | |
550 | b 2f | |
551 | #endif | |
1da177e4 | 552 | call_fpe: |
b5872db4 | 553 | #ifdef CONFIG_NEON |
cb170a45 | 554 | adr r6, .LCneon_arm_opcodes |
b5872db4 CM |
555 | 2: |
556 | ldr r7, [r6], #4 @ mask value | |
557 | cmp r7, #0 @ end mask? | |
558 | beq 1f | |
559 | and r8, r0, r7 | |
560 | ldr r7, [r6], #4 @ opcode bits matching in mask | |
561 | cmp r8, r7 @ NEON instruction? | |
562 | bne 2b | |
563 | get_thread_info r10 | |
564 | mov r7, #1 | |
565 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
566 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
567 | b do_vfp @ let VFP handler handle this | |
568 | 1: | |
569 | #endif | |
1da177e4 | 570 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 571 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
1da177e4 LT |
572 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) |
573 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
574 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
575 | #endif | |
576 | moveq pc, lr | |
577 | get_thread_info r10 @ get current thread | |
578 | and r8, r0, #0x00000f00 @ mask out CP number | |
b86040a5 | 579 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
580 | mov r7, #1 |
581 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
582 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
583 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
584 | #ifdef CONFIG_IWMMXT |
585 | @ Test if we need to give access to iWMMXt coprocessors | |
586 | ldr r5, [r10, #TI_FLAGS] | |
587 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
588 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
589 | bcs iwmmxt_task_enable | |
590 | #endif | |
b86040a5 CM |
591 | ARM( add pc, pc, r8, lsr #6 ) |
592 | THUMB( lsl r8, r8, #2 ) | |
593 | THUMB( add pc, r8 ) | |
594 | nop | |
595 | ||
a771fe6e | 596 | movw_pc lr @ CP#0 |
b86040a5 CM |
597 | W(b) do_fpe @ CP#1 (FPE) |
598 | W(b) do_fpe @ CP#2 (FPE) | |
a771fe6e | 599 | movw_pc lr @ CP#3 |
c17fad11 LB |
600 | #ifdef CONFIG_CRUNCH |
601 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
602 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
603 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
604 | #else | |
a771fe6e CM |
605 | movw_pc lr @ CP#4 |
606 | movw_pc lr @ CP#5 | |
607 | movw_pc lr @ CP#6 | |
c17fad11 | 608 | #endif |
a771fe6e CM |
609 | movw_pc lr @ CP#7 |
610 | movw_pc lr @ CP#8 | |
611 | movw_pc lr @ CP#9 | |
1da177e4 | 612 | #ifdef CONFIG_VFP |
b86040a5 CM |
613 | W(b) do_vfp @ CP#10 (VFP) |
614 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 615 | #else |
a771fe6e CM |
616 | movw_pc lr @ CP#10 (VFP) |
617 | movw_pc lr @ CP#11 (VFP) | |
1da177e4 | 618 | #endif |
a771fe6e CM |
619 | movw_pc lr @ CP#12 |
620 | movw_pc lr @ CP#13 | |
621 | movw_pc lr @ CP#14 (Debug) | |
622 | movw_pc lr @ CP#15 (Control) | |
1da177e4 | 623 | |
b5872db4 CM |
624 | #ifdef CONFIG_NEON |
625 | .align 6 | |
626 | ||
cb170a45 | 627 | .LCneon_arm_opcodes: |
b5872db4 CM |
628 | .word 0xfe000000 @ mask |
629 | .word 0xf2000000 @ opcode | |
630 | ||
631 | .word 0xff100000 @ mask | |
632 | .word 0xf4000000 @ opcode | |
633 | ||
cb170a45 PB |
634 | .word 0x00000000 @ mask |
635 | .word 0x00000000 @ opcode | |
636 | ||
637 | .LCneon_thumb_opcodes: | |
638 | .word 0xef000000 @ mask | |
639 | .word 0xef000000 @ opcode | |
640 | ||
641 | .word 0xff100000 @ mask | |
642 | .word 0xf9000000 @ opcode | |
643 | ||
b5872db4 CM |
644 | .word 0x00000000 @ mask |
645 | .word 0x00000000 @ opcode | |
646 | #endif | |
647 | ||
1da177e4 | 648 | do_fpe: |
5d25ac03 | 649 | enable_irq |
1da177e4 LT |
650 | ldr r4, .LCfp |
651 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
652 | ldr pc, [r4] @ Call FP module USR entry point | |
653 | ||
654 | /* | |
655 | * The FP module is called with these registers set: | |
656 | * r0 = instruction | |
657 | * r2 = PC+4 | |
658 | * r9 = normal "successful" return address | |
659 | * r10 = FP workspace | |
660 | * lr = unrecognised FP instruction return address | |
661 | */ | |
662 | ||
124efc27 | 663 | .pushsection .data |
1da177e4 | 664 | ENTRY(fp_enter) |
db6ccbb6 | 665 | .word no_fp |
124efc27 | 666 | .popsection |
1da177e4 | 667 | |
83e686ea CM |
668 | ENTRY(no_fp) |
669 | mov pc, lr | |
670 | ENDPROC(no_fp) | |
db6ccbb6 RK |
671 | |
672 | __und_usr_unknown: | |
ecbab71c | 673 | enable_irq |
1da177e4 | 674 | mov r0, sp |
b86040a5 | 675 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 676 | b do_undefinstr |
93ed3970 | 677 | ENDPROC(__und_usr_unknown) |
1da177e4 LT |
678 | |
679 | .align 5 | |
680 | __pabt_usr: | |
ccea7a19 | 681 | usr_entry |
bc089602 RK |
682 | |
683 | #ifdef CONFIG_IRQSOFF_TRACER | |
684 | bl trace_hardirqs_off | |
685 | #endif | |
686 | ||
ac8b9c1c | 687 | pabt_helper |
4fb28474 | 688 | mov r2, sp @ regs |
1da177e4 | 689 | bl do_PrefetchAbort @ call abort handler |
c4c5716e | 690 | UNWIND(.fnend ) |
1da177e4 LT |
691 | /* fall through */ |
692 | /* | |
693 | * This is the return code to user mode for abort handlers | |
694 | */ | |
695 | ENTRY(ret_from_exception) | |
c4c5716e CM |
696 | UNWIND(.fnstart ) |
697 | UNWIND(.cantunwind ) | |
1da177e4 LT |
698 | get_thread_info tsk |
699 | mov why, #0 | |
700 | b ret_to_user | |
c4c5716e | 701 | UNWIND(.fnend ) |
93ed3970 CM |
702 | ENDPROC(__pabt_usr) |
703 | ENDPROC(ret_from_exception) | |
1da177e4 LT |
704 | |
705 | /* | |
706 | * Register switch for ARMv3 and ARMv4 processors | |
707 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
708 | * previous and next are guaranteed not to be the same. | |
709 | */ | |
710 | ENTRY(__switch_to) | |
c4c5716e CM |
711 | UNWIND(.fnstart ) |
712 | UNWIND(.cantunwind ) | |
1da177e4 LT |
713 | add ip, r1, #TI_CPU_SAVE |
714 | ldr r3, [r2, #TI_TP_VALUE] | |
b86040a5 CM |
715 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
716 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
717 | THUMB( str sp, [ip], #4 ) | |
718 | THUMB( str lr, [ip], #4 ) | |
247055aa | 719 | #ifdef CONFIG_CPU_USE_DOMAINS |
d6551e88 | 720 | ldr r6, [r2, #TI_CPU_DOMAIN] |
afeb90ca | 721 | #endif |
f159f4ed | 722 | set_tls r3, r4, r5 |
df0698be NP |
723 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
724 | ldr r7, [r2, #TI_TASK] | |
725 | ldr r8, =__stack_chk_guard | |
726 | ldr r7, [r7, #TSK_STACK_CANARY] | |
727 | #endif | |
247055aa | 728 | #ifdef CONFIG_CPU_USE_DOMAINS |
1da177e4 | 729 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 730 | #endif |
d6551e88 RK |
731 | mov r5, r0 |
732 | add r4, r2, #TI_CPU_SAVE | |
733 | ldr r0, =thread_notify_head | |
734 | mov r1, #THREAD_NOTIFY_SWITCH | |
735 | bl atomic_notifier_call_chain | |
df0698be NP |
736 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
737 | str r7, [r8] | |
738 | #endif | |
b86040a5 | 739 | THUMB( mov ip, r4 ) |
d6551e88 | 740 | mov r0, r5 |
b86040a5 CM |
741 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
742 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
743 | THUMB( ldr sp, [ip], #4 ) | |
744 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 745 | UNWIND(.fnend ) |
93ed3970 | 746 | ENDPROC(__switch_to) |
1da177e4 LT |
747 | |
748 | __INIT | |
2d2669b6 NP |
749 | |
750 | /* | |
751 | * User helpers. | |
752 | * | |
753 | * These are segment of kernel provided user code reachable from user space | |
754 | * at a fixed address in kernel memory. This is used to provide user space | |
755 | * with some operations which require kernel help because of unimplemented | |
756 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
757 | * this code to be executed directly in user mode for best efficiency but | |
758 | * which is too intimate with the kernel counter part to be left to user | |
759 | * libraries. In fact this code might even differ from one CPU to another | |
760 | * depending on the available instruction set and restrictions like on | |
761 | * SMP systems. In other words, the kernel reserves the right to change | |
762 | * this code as needed without warning. Only the entry points and their | |
763 | * results are guaranteed to be stable. | |
764 | * | |
765 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
766 | * vector page. New segments (if ever needed) must be added in front of | |
767 | * existing ones. This mechanism should be used only for things that are | |
768 | * really small and justified, and not be abused freely. | |
769 | * | |
770 | * User space is expected to implement those things inline when optimizing | |
771 | * for a processor that has the necessary native support, but only if such | |
772 | * resulting binaries are already to be incompatible with earlier ARM | |
773 | * processors due to the use of unsupported instructions other than what | |
774 | * is provided here. In other words don't make binaries unable to run on | |
775 | * earlier processors just for the sake of not using these kernel helpers | |
776 | * if your compiled code is not going to use the new instructions for other | |
777 | * purpose. | |
778 | */ | |
b86040a5 | 779 | THUMB( .arm ) |
2d2669b6 | 780 | |
ba9b5d76 NP |
781 | .macro usr_ret, reg |
782 | #ifdef CONFIG_ARM_THUMB | |
783 | bx \reg | |
784 | #else | |
785 | mov pc, \reg | |
786 | #endif | |
787 | .endm | |
788 | ||
2d2669b6 NP |
789 | .align 5 |
790 | .globl __kuser_helper_start | |
791 | __kuser_helper_start: | |
792 | ||
7c612bfd NP |
793 | /* |
794 | * Reference prototype: | |
795 | * | |
796 | * void __kernel_memory_barrier(void) | |
797 | * | |
798 | * Input: | |
799 | * | |
800 | * lr = return address | |
801 | * | |
802 | * Output: | |
803 | * | |
804 | * none | |
805 | * | |
806 | * Clobbered: | |
807 | * | |
b49c0f24 | 808 | * none |
7c612bfd NP |
809 | * |
810 | * Definition and user space usage example: | |
811 | * | |
812 | * typedef void (__kernel_dmb_t)(void); | |
813 | * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) | |
814 | * | |
815 | * Apply any needed memory barrier to preserve consistency with data modified | |
816 | * manually and __kuser_cmpxchg usage. | |
817 | * | |
818 | * This could be used as follows: | |
819 | * | |
820 | * #define __kernel_dmb() \ | |
821 | * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ | |
6896eec0 | 822 | * : : : "r0", "lr","cc" ) |
7c612bfd NP |
823 | */ |
824 | ||
825 | __kuser_memory_barrier: @ 0xffff0fa0 | |
ed3768a8 | 826 | smp_dmb arm |
ba9b5d76 | 827 | usr_ret lr |
7c612bfd NP |
828 | |
829 | .align 5 | |
830 | ||
2d2669b6 NP |
831 | /* |
832 | * Reference prototype: | |
833 | * | |
834 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
835 | * | |
836 | * Input: | |
837 | * | |
838 | * r0 = oldval | |
839 | * r1 = newval | |
840 | * r2 = ptr | |
841 | * lr = return address | |
842 | * | |
843 | * Output: | |
844 | * | |
845 | * r0 = returned value (zero or non-zero) | |
846 | * C flag = set if r0 == 0, clear if r0 != 0 | |
847 | * | |
848 | * Clobbered: | |
849 | * | |
850 | * r3, ip, flags | |
851 | * | |
852 | * Definition and user space usage example: | |
853 | * | |
854 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
855 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
856 | * | |
857 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
858 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
859 | * The C flag is also set if *ptr was changed to allow for assembly | |
860 | * optimization in the calling code. | |
861 | * | |
5964eae8 NP |
862 | * Notes: |
863 | * | |
864 | * - This routine already includes memory barriers as needed. | |
865 | * | |
2d2669b6 NP |
866 | * For example, a user space atomic_add implementation could look like this: |
867 | * | |
868 | * #define atomic_add(ptr, val) \ | |
869 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
870 | * register unsigned int __result asm("r1"); \ | |
871 | * asm volatile ( \ | |
872 | * "1: @ atomic_add\n\t" \ | |
873 | * "ldr r0, [r2]\n\t" \ | |
874 | * "mov r3, #0xffff0fff\n\t" \ | |
875 | * "add lr, pc, #4\n\t" \ | |
876 | * "add r1, r0, %2\n\t" \ | |
877 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
878 | * "bcc 1b" \ | |
879 | * : "=&r" (__result) \ | |
880 | * : "r" (__ptr), "rIL" (val) \ | |
881 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
882 | * __result; }) | |
883 | */ | |
884 | ||
885 | __kuser_cmpxchg: @ 0xffff0fc0 | |
886 | ||
dcef1f63 | 887 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 888 | |
dcef1f63 NP |
889 | /* |
890 | * Poor you. No fast solution possible... | |
891 | * The kernel itself must perform the operation. | |
892 | * A special ghost syscall is used for that (see traps.c). | |
893 | */ | |
5e097445 | 894 | stmfd sp!, {r7, lr} |
55afd264 | 895 | ldr r7, 1f @ it's 20 bits |
cc20d429 | 896 | swi __ARM_NR_cmpxchg |
5e097445 | 897 | ldmfd sp!, {r7, pc} |
cc20d429 | 898 | 1: .word __ARM_NR_cmpxchg |
dcef1f63 NP |
899 | |
900 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 901 | |
b49c0f24 NP |
902 | #ifdef CONFIG_MMU |
903 | ||
2d2669b6 | 904 | /* |
b49c0f24 NP |
905 | * The only thing that can break atomicity in this cmpxchg |
906 | * implementation is either an IRQ or a data abort exception | |
907 | * causing another process/thread to be scheduled in the middle | |
908 | * of the critical sequence. To prevent this, code is added to | |
909 | * the IRQ and data abort exception handlers to set the pc back | |
910 | * to the beginning of the critical section if it is found to be | |
911 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 912 | */ |
b49c0f24 NP |
913 | 1: ldr r3, [r2] @ load current val |
914 | subs r3, r3, r0 @ compare with oldval | |
915 | 2: streq r1, [r2] @ store newval if eq | |
916 | rsbs r0, r3, #0 @ set return val and C flag | |
917 | usr_ret lr | |
918 | ||
919 | .text | |
920 | kuser_cmpxchg_fixup: | |
921 | @ Called from kuser_cmpxchg_check macro. | |
b059bdc3 | 922 | @ r4 = address of interrupted insn (must be preserved). |
b49c0f24 NP |
923 | @ sp = saved regs. r7 and r8 are clobbered. |
924 | @ 1b = first critical insn, 2b = last critical insn. | |
b059bdc3 | 925 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
b49c0f24 NP |
926 | mov r7, #0xffff0fff |
927 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
b059bdc3 | 928 | subs r8, r4, r7 |
b49c0f24 NP |
929 | rsbcss r8, r8, #(2b - 1b) |
930 | strcs r7, [sp, #S_PC] | |
931 | mov pc, lr | |
932 | .previous | |
933 | ||
49bca4c2 NP |
934 | #else |
935 | #warning "NPTL on non MMU needs fixing" | |
936 | mov r0, #-1 | |
937 | adds r0, r0, #0 | |
ba9b5d76 | 938 | usr_ret lr |
b49c0f24 | 939 | #endif |
2d2669b6 NP |
940 | |
941 | #else | |
942 | ||
ed3768a8 | 943 | smp_dmb arm |
b49c0f24 | 944 | 1: ldrex r3, [r2] |
2d2669b6 NP |
945 | subs r3, r3, r0 |
946 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
947 | teqeq r3, #1 |
948 | beq 1b | |
2d2669b6 | 949 | rsbs r0, r3, #0 |
b49c0f24 | 950 | /* beware -- each __kuser slot must be 8 instructions max */ |
f00ec48f RK |
951 | ALT_SMP(b __kuser_memory_barrier) |
952 | ALT_UP(usr_ret lr) | |
2d2669b6 NP |
953 | |
954 | #endif | |
955 | ||
956 | .align 5 | |
957 | ||
958 | /* | |
959 | * Reference prototype: | |
960 | * | |
961 | * int __kernel_get_tls(void) | |
962 | * | |
963 | * Input: | |
964 | * | |
965 | * lr = return address | |
966 | * | |
967 | * Output: | |
968 | * | |
969 | * r0 = TLS value | |
970 | * | |
971 | * Clobbered: | |
972 | * | |
b49c0f24 | 973 | * none |
2d2669b6 NP |
974 | * |
975 | * Definition and user space usage example: | |
976 | * | |
977 | * typedef int (__kernel_get_tls_t)(void); | |
978 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
979 | * | |
980 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
981 | * | |
982 | * This could be used as follows: | |
983 | * | |
984 | * #define __kernel_get_tls() \ | |
985 | * ({ register unsigned int __val asm("r0"); \ | |
986 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
987 | * : "=r" (__val) : : "lr","cc" ); \ | |
988 | * __val; }) | |
989 | */ | |
990 | ||
991 | __kuser_get_tls: @ 0xffff0fe0 | |
f159f4ed | 992 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
ba9b5d76 | 993 | usr_ret lr |
f159f4ed TL |
994 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
995 | .rep 4 | |
996 | .word 0 @ 0xffff0ff0 software TLS value, then | |
997 | .endr @ pad up to __kuser_helper_version | |
2d2669b6 NP |
998 | |
999 | /* | |
1000 | * Reference declaration: | |
1001 | * | |
1002 | * extern unsigned int __kernel_helper_version; | |
1003 | * | |
1004 | * Definition and user space usage example: | |
1005 | * | |
1006 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
1007 | * | |
1008 | * User space may read this to determine the curent number of helpers | |
1009 | * available. | |
1010 | */ | |
1011 | ||
1012 | __kuser_helper_version: @ 0xffff0ffc | |
1013 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
1014 | ||
1015 | .globl __kuser_helper_end | |
1016 | __kuser_helper_end: | |
1017 | ||
b86040a5 | 1018 | THUMB( .thumb ) |
2d2669b6 | 1019 | |
1da177e4 LT |
1020 | /* |
1021 | * Vector stubs. | |
1022 | * | |
7933523d RK |
1023 | * This code is copied to 0xffff0200 so we can use branches in the |
1024 | * vectors, rather than ldr's. Note that this code must not | |
1025 | * exceed 0x300 bytes. | |
1da177e4 LT |
1026 | * |
1027 | * Common stub entry macro: | |
1028 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
1029 | * |
1030 | * SP points to a minimal amount of processor-private memory, the address | |
1031 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 1032 | */ |
b7ec4795 | 1033 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
1034 | .align 5 |
1035 | ||
1036 | vector_\name: | |
1da177e4 LT |
1037 | .if \correction |
1038 | sub lr, lr, #\correction | |
1039 | .endif | |
ccea7a19 RK |
1040 | |
1041 | @ | |
1042 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
1043 | @ (parent CPSR) | |
1044 | @ | |
1045 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 1046 | mrs lr, spsr |
ccea7a19 RK |
1047 | str lr, [sp, #8] @ save spsr |
1048 | ||
1da177e4 | 1049 | @ |
ccea7a19 | 1050 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 1051 | @ |
ccea7a19 | 1052 | mrs r0, cpsr |
b86040a5 | 1053 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 1054 | msr spsr_cxsf, r0 |
1da177e4 | 1055 | |
ccea7a19 RK |
1056 | @ |
1057 | @ the branch table must immediately follow this code | |
1058 | @ | |
ccea7a19 | 1059 | and lr, lr, #0x0f |
b86040a5 CM |
1060 | THUMB( adr r0, 1f ) |
1061 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 1062 | mov r0, sp |
b86040a5 | 1063 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 1064 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 1065 | ENDPROC(vector_\name) |
88987ef9 CM |
1066 | |
1067 | .align 2 | |
1068 | @ handler addresses follow this label | |
1069 | 1: | |
1da177e4 LT |
1070 | .endm |
1071 | ||
7933523d | 1072 | .globl __stubs_start |
1da177e4 LT |
1073 | __stubs_start: |
1074 | /* | |
1075 | * Interrupt dispatcher | |
1076 | */ | |
b7ec4795 | 1077 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1078 | |
1079 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1080 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1081 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1082 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1083 | .long __irq_invalid @ 4 | |
1084 | .long __irq_invalid @ 5 | |
1085 | .long __irq_invalid @ 6 | |
1086 | .long __irq_invalid @ 7 | |
1087 | .long __irq_invalid @ 8 | |
1088 | .long __irq_invalid @ 9 | |
1089 | .long __irq_invalid @ a | |
1090 | .long __irq_invalid @ b | |
1091 | .long __irq_invalid @ c | |
1092 | .long __irq_invalid @ d | |
1093 | .long __irq_invalid @ e | |
1094 | .long __irq_invalid @ f | |
1095 | ||
1096 | /* | |
1097 | * Data abort dispatcher | |
1098 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1099 | */ | |
b7ec4795 | 1100 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1101 | |
1102 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1103 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1104 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1105 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1106 | .long __dabt_invalid @ 4 | |
1107 | .long __dabt_invalid @ 5 | |
1108 | .long __dabt_invalid @ 6 | |
1109 | .long __dabt_invalid @ 7 | |
1110 | .long __dabt_invalid @ 8 | |
1111 | .long __dabt_invalid @ 9 | |
1112 | .long __dabt_invalid @ a | |
1113 | .long __dabt_invalid @ b | |
1114 | .long __dabt_invalid @ c | |
1115 | .long __dabt_invalid @ d | |
1116 | .long __dabt_invalid @ e | |
1117 | .long __dabt_invalid @ f | |
1118 | ||
1119 | /* | |
1120 | * Prefetch abort dispatcher | |
1121 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1122 | */ | |
b7ec4795 | 1123 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1124 | |
1125 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1126 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1127 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1128 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1129 | .long __pabt_invalid @ 4 | |
1130 | .long __pabt_invalid @ 5 | |
1131 | .long __pabt_invalid @ 6 | |
1132 | .long __pabt_invalid @ 7 | |
1133 | .long __pabt_invalid @ 8 | |
1134 | .long __pabt_invalid @ 9 | |
1135 | .long __pabt_invalid @ a | |
1136 | .long __pabt_invalid @ b | |
1137 | .long __pabt_invalid @ c | |
1138 | .long __pabt_invalid @ d | |
1139 | .long __pabt_invalid @ e | |
1140 | .long __pabt_invalid @ f | |
1141 | ||
1142 | /* | |
1143 | * Undef instr entry dispatcher | |
1144 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1145 | */ | |
b7ec4795 | 1146 | vector_stub und, UND_MODE |
1da177e4 LT |
1147 | |
1148 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1149 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1150 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1151 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1152 | .long __und_invalid @ 4 | |
1153 | .long __und_invalid @ 5 | |
1154 | .long __und_invalid @ 6 | |
1155 | .long __und_invalid @ 7 | |
1156 | .long __und_invalid @ 8 | |
1157 | .long __und_invalid @ 9 | |
1158 | .long __und_invalid @ a | |
1159 | .long __und_invalid @ b | |
1160 | .long __und_invalid @ c | |
1161 | .long __und_invalid @ d | |
1162 | .long __und_invalid @ e | |
1163 | .long __und_invalid @ f | |
1164 | ||
1165 | .align 5 | |
1166 | ||
1167 | /*============================================================================= | |
1168 | * Undefined FIQs | |
1169 | *----------------------------------------------------------------------------- | |
1170 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1171 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1172 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1173 | * damage alert! I don't think that we can execute any code in here in any | |
1174 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1175 | * get out of that mode without clobbering one register. | |
1176 | */ | |
1177 | vector_fiq: | |
1178 | disable_fiq | |
1179 | subs pc, lr, #4 | |
1180 | ||
1181 | /*============================================================================= | |
1182 | * Address exception handler | |
1183 | *----------------------------------------------------------------------------- | |
1184 | * These aren't too critical. | |
1185 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1186 | */ | |
1187 | ||
1188 | vector_addrexcptn: | |
1189 | b vector_addrexcptn | |
1190 | ||
1191 | /* | |
1192 | * We group all the following data together to optimise | |
1193 | * for CPUs with separate I & D caches. | |
1194 | */ | |
1195 | .align 5 | |
1196 | ||
1197 | .LCvswi: | |
1198 | .word vector_swi | |
1199 | ||
7933523d | 1200 | .globl __stubs_end |
1da177e4 LT |
1201 | __stubs_end: |
1202 | ||
7933523d | 1203 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1204 | |
7933523d RK |
1205 | .globl __vectors_start |
1206 | __vectors_start: | |
b86040a5 CM |
1207 | ARM( swi SYS_ERROR0 ) |
1208 | THUMB( svc #0 ) | |
1209 | THUMB( nop ) | |
1210 | W(b) vector_und + stubs_offset | |
1211 | W(ldr) pc, .LCvswi + stubs_offset | |
1212 | W(b) vector_pabt + stubs_offset | |
1213 | W(b) vector_dabt + stubs_offset | |
1214 | W(b) vector_addrexcptn + stubs_offset | |
1215 | W(b) vector_irq + stubs_offset | |
1216 | W(b) vector_fiq + stubs_offset | |
7933523d RK |
1217 | |
1218 | .globl __vectors_end | |
1219 | __vectors_end: | |
1da177e4 LT |
1220 | |
1221 | .data | |
1222 | ||
1da177e4 LT |
1223 | .globl cr_alignment |
1224 | .globl cr_no_alignment | |
1225 | cr_alignment: | |
1226 | .space 4 | |
1227 | cr_no_alignment: | |
1228 | .space 4 | |
52108641 | 1229 | |
1230 | #ifdef CONFIG_MULTI_IRQ_HANDLER | |
1231 | .globl handle_arch_irq | |
1232 | handle_arch_irq: | |
1233 | .space 4 | |
1234 | #endif |