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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
f09b9979 | 18 | #include <asm/memory.h> |
1da177e4 | 19 | #include <asm/glue.h> |
1da177e4 | 20 | #include <asm/vfpmacros.h> |
a09e64fb | 21 | #include <mach/entry-macro.S> |
d6551e88 | 22 | #include <asm/thread_notify.h> |
c4c5716e | 23 | #include <asm/unwind.h> |
1da177e4 LT |
24 | |
25 | #include "entry-header.S" | |
26 | ||
187a51ad RK |
27 | /* |
28 | * Interrupt handling. Preserves r7, r8, r9 | |
29 | */ | |
30 | .macro irq_handler | |
f80dff9d | 31 | get_irqnr_preamble r5, lr |
187a51ad RK |
32 | 1: get_irqnr_and_base r0, r6, r5, lr |
33 | movne r1, sp | |
34 | @ | |
35 | @ routine called with r0 = irq number, r1 = struct pt_regs * | |
36 | @ | |
b86040a5 | 37 | adrne lr, BSYM(1b) |
187a51ad | 38 | bne asm_do_IRQ |
791be9b9 RK |
39 | |
40 | #ifdef CONFIG_SMP | |
41 | /* | |
42 | * XXX | |
43 | * | |
44 | * this macro assumes that irqstat (r6) and base (r5) are | |
45 | * preserved from get_irqnr_and_base above | |
46 | */ | |
47 | test_for_ipi r0, r6, r5, lr | |
48 | movne r0, sp | |
b86040a5 | 49 | adrne lr, BSYM(1b) |
791be9b9 | 50 | bne do_IPI |
37ee16ae RK |
51 | |
52 | #ifdef CONFIG_LOCAL_TIMERS | |
53 | test_for_ltirq r0, r6, r5, lr | |
54 | movne r0, sp | |
b86040a5 | 55 | adrne lr, BSYM(1b) |
37ee16ae RK |
56 | bne do_local_timer |
57 | #endif | |
791be9b9 RK |
58 | #endif |
59 | ||
187a51ad RK |
60 | .endm |
61 | ||
785d3cd2 NP |
62 | #ifdef CONFIG_KPROBES |
63 | .section .kprobes.text,"ax",%progbits | |
64 | #else | |
65 | .text | |
66 | #endif | |
67 | ||
1da177e4 LT |
68 | /* |
69 | * Invalid mode handlers | |
70 | */ | |
ccea7a19 RK |
71 | .macro inv_entry, reason |
72 | sub sp, sp, #S_FRAME_SIZE | |
b86040a5 CM |
73 | ARM( stmib sp, {r1 - lr} ) |
74 | THUMB( stmia sp, {r0 - r12} ) | |
75 | THUMB( str sp, [sp, #S_SP] ) | |
76 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
77 | mov r1, #\reason |
78 | .endm | |
79 | ||
80 | __pabt_invalid: | |
ccea7a19 RK |
81 | inv_entry BAD_PREFETCH |
82 | b common_invalid | |
93ed3970 | 83 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
84 | |
85 | __dabt_invalid: | |
ccea7a19 RK |
86 | inv_entry BAD_DATA |
87 | b common_invalid | |
93ed3970 | 88 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
89 | |
90 | __irq_invalid: | |
ccea7a19 RK |
91 | inv_entry BAD_IRQ |
92 | b common_invalid | |
93ed3970 | 93 | ENDPROC(__irq_invalid) |
1da177e4 LT |
94 | |
95 | __und_invalid: | |
ccea7a19 RK |
96 | inv_entry BAD_UNDEFINSTR |
97 | ||
98 | @ | |
99 | @ XXX fall through to common_invalid | |
100 | @ | |
101 | ||
102 | @ | |
103 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
104 | @ | |
105 | common_invalid: | |
106 | zero_fp | |
107 | ||
108 | ldmia r0, {r4 - r6} | |
109 | add r0, sp, #S_PC @ here for interlock avoidance | |
110 | mov r7, #-1 @ "" "" "" "" | |
111 | str r4, [sp] @ save preserved r0 | |
112 | stmia r0, {r5 - r7} @ lr_<exception>, | |
113 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 114 | |
1da177e4 | 115 | mov r0, sp |
1da177e4 | 116 | b bad_mode |
93ed3970 | 117 | ENDPROC(__und_invalid) |
1da177e4 LT |
118 | |
119 | /* | |
120 | * SVC mode handlers | |
121 | */ | |
2dede2d8 NP |
122 | |
123 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
124 | #define SPFIX(code...) code | |
125 | #else | |
126 | #define SPFIX(code...) | |
127 | #endif | |
128 | ||
d30a0c8b | 129 | .macro svc_entry, stack_hole=0 |
c4c5716e CM |
130 | UNWIND(.fnstart ) |
131 | UNWIND(.save {r0 - pc} ) | |
b86040a5 CM |
132 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
133 | #ifdef CONFIG_THUMB2_KERNEL | |
134 | SPFIX( str r0, [sp] ) @ temporarily saved | |
135 | SPFIX( mov r0, sp ) | |
136 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
137 | SPFIX( ldr r0, [sp] ) @ restored | |
138 | #else | |
2dede2d8 | 139 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
140 | #endif |
141 | SPFIX( subeq sp, sp, #4 ) | |
142 | stmia sp, {r1 - r12} | |
ccea7a19 RK |
143 | |
144 | ldmia r0, {r1 - r3} | |
b86040a5 | 145 | add r5, sp, #S_SP - 4 @ here for interlock avoidance |
ccea7a19 | 146 | mov r4, #-1 @ "" "" "" "" |
b86040a5 CM |
147 | add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
148 | SPFIX( addeq r0, r0, #4 ) | |
149 | str r1, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
150 | @ from the exception stack |
151 | ||
1da177e4 LT |
152 | mov r1, lr |
153 | ||
154 | @ | |
155 | @ We are now ready to fill in the remaining blanks on the stack: | |
156 | @ | |
157 | @ r0 - sp_svc | |
158 | @ r1 - lr_svc | |
159 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
160 | @ r3 - spsr_<exception> | |
161 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
162 | @ | |
163 | stmia r5, {r0 - r4} | |
0d928b0b UKK |
164 | |
165 | asm_trace_hardirqs_off | |
1da177e4 LT |
166 | .endm |
167 | ||
168 | .align 5 | |
169 | __dabt_svc: | |
ccea7a19 | 170 | svc_entry |
1da177e4 LT |
171 | |
172 | @ | |
173 | @ get ready to re-enable interrupts if appropriate | |
174 | @ | |
175 | mrs r9, cpsr | |
176 | tst r3, #PSR_I_BIT | |
177 | biceq r9, r9, #PSR_I_BIT | |
178 | ||
179 | @ | |
180 | @ Call the processor-specific abort handler: | |
181 | @ | |
182 | @ r2 - aborted context pc | |
183 | @ r3 - aborted context cpsr | |
184 | @ | |
185 | @ The abort handler must return the aborted address in r0, and | |
186 | @ the fault status register in r1. r9 must be preserved. | |
187 | @ | |
48d7927b | 188 | #ifdef MULTI_DABORT |
1da177e4 LT |
189 | ldr r4, .LCprocfns |
190 | mov lr, pc | |
48d7927b | 191 | ldr pc, [r4, #PROCESSOR_DABT_FUNC] |
1da177e4 | 192 | #else |
48d7927b | 193 | bl CPU_DABORT_HANDLER |
1da177e4 LT |
194 | #endif |
195 | ||
196 | @ | |
197 | @ set desired IRQ state, then call main handler | |
198 | @ | |
199 | msr cpsr_c, r9 | |
200 | mov r2, sp | |
201 | bl do_DataAbort | |
202 | ||
203 | @ | |
204 | @ IRQs off again before pulling preserved data off the stack | |
205 | @ | |
1ec42c0c | 206 | disable_irq |
1da177e4 LT |
207 | |
208 | @ | |
209 | @ restore SPSR and restart the instruction | |
210 | @ | |
b86040a5 CM |
211 | ldr r2, [sp, #S_PSR] |
212 | svc_exit r2 @ return from exception | |
c4c5716e | 213 | UNWIND(.fnend ) |
93ed3970 | 214 | ENDPROC(__dabt_svc) |
1da177e4 LT |
215 | |
216 | .align 5 | |
217 | __irq_svc: | |
ccea7a19 RK |
218 | svc_entry |
219 | ||
1da177e4 | 220 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
221 | get_thread_info tsk |
222 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
223 | add r7, r8, #1 @ increment it | |
224 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 225 | #endif |
ccea7a19 | 226 | |
187a51ad | 227 | irq_handler |
1da177e4 | 228 | #ifdef CONFIG_PREEMPT |
28fab1a2 | 229 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count |
706fdd9f | 230 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
231 | teq r8, #0 @ if preempt count != 0 |
232 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
233 | tst r0, #_TIF_NEED_RESCHED |
234 | blne svc_preempt | |
1da177e4 | 235 | #endif |
b86040a5 | 236 | ldr r4, [sp, #S_PSR] @ irqs are already disabled |
7ad1bcb2 | 237 | #ifdef CONFIG_TRACE_IRQFLAGS |
b86040a5 | 238 | tst r4, #PSR_I_BIT |
7ad1bcb2 RK |
239 | bleq trace_hardirqs_on |
240 | #endif | |
b86040a5 | 241 | svc_exit r4 @ return from exception |
c4c5716e | 242 | UNWIND(.fnend ) |
93ed3970 | 243 | ENDPROC(__irq_svc) |
1da177e4 LT |
244 | |
245 | .ltorg | |
246 | ||
247 | #ifdef CONFIG_PREEMPT | |
248 | svc_preempt: | |
28fab1a2 | 249 | mov r8, lr |
1da177e4 | 250 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 251 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 252 | tst r0, #_TIF_NEED_RESCHED |
28fab1a2 | 253 | moveq pc, r8 @ go again |
1da177e4 LT |
254 | b 1b |
255 | #endif | |
256 | ||
257 | .align 5 | |
258 | __und_svc: | |
d30a0c8b NP |
259 | #ifdef CONFIG_KPROBES |
260 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
261 | @ it obviously needs free stack space which then will belong to | |
262 | @ the saved context. | |
263 | svc_entry 64 | |
264 | #else | |
ccea7a19 | 265 | svc_entry |
d30a0c8b | 266 | #endif |
1da177e4 LT |
267 | |
268 | @ | |
269 | @ call emulation code, which returns using r9 if it has emulated | |
270 | @ the instruction, or the more conventional lr if we are to treat | |
271 | @ this as a real undefined instruction | |
272 | @ | |
273 | @ r0 - instruction | |
274 | @ | |
83e686ea | 275 | #ifndef CONFIG_THUMB2_KERNEL |
1da177e4 | 276 | ldr r0, [r2, #-4] |
83e686ea CM |
277 | #else |
278 | ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2 | |
279 | and r9, r0, #0xf800 | |
280 | cmp r9, #0xe800 @ 32-bit instruction if xx >= 0 | |
281 | ldrhhs r9, [r2] @ bottom 16 bits | |
282 | orrhs r0, r9, r0, lsl #16 | |
283 | #endif | |
b86040a5 | 284 | adr r9, BSYM(1f) |
1da177e4 LT |
285 | bl call_fpe |
286 | ||
287 | mov r0, sp @ struct pt_regs *regs | |
288 | bl do_undefinstr | |
289 | ||
290 | @ | |
291 | @ IRQs off again before pulling preserved data off the stack | |
292 | @ | |
1ec42c0c | 293 | 1: disable_irq |
1da177e4 LT |
294 | |
295 | @ | |
296 | @ restore SPSR and restart the instruction | |
297 | @ | |
b86040a5 CM |
298 | ldr r2, [sp, #S_PSR] @ Get SVC cpsr |
299 | svc_exit r2 @ return from exception | |
c4c5716e | 300 | UNWIND(.fnend ) |
93ed3970 | 301 | ENDPROC(__und_svc) |
1da177e4 LT |
302 | |
303 | .align 5 | |
304 | __pabt_svc: | |
ccea7a19 | 305 | svc_entry |
1da177e4 LT |
306 | |
307 | @ | |
308 | @ re-enable interrupts if appropriate | |
309 | @ | |
310 | mrs r9, cpsr | |
311 | tst r3, #PSR_I_BIT | |
312 | biceq r9, r9, #PSR_I_BIT | |
1da177e4 | 313 | |
48d7927b | 314 | mov r0, r2 @ pass address of aborted instruction. |
4fb28474 | 315 | #ifdef MULTI_PABORT |
48d7927b PB |
316 | ldr r4, .LCprocfns |
317 | mov lr, pc | |
318 | ldr pc, [r4, #PROCESSOR_PABT_FUNC] | |
319 | #else | |
4fb28474 | 320 | bl CPU_PABORT_HANDLER |
48d7927b PB |
321 | #endif |
322 | msr cpsr_c, r9 @ Maybe enable interrupts | |
4fb28474 | 323 | mov r2, sp @ regs |
1da177e4 LT |
324 | bl do_PrefetchAbort @ call abort handler |
325 | ||
326 | @ | |
327 | @ IRQs off again before pulling preserved data off the stack | |
328 | @ | |
1ec42c0c | 329 | disable_irq |
1da177e4 LT |
330 | |
331 | @ | |
332 | @ restore SPSR and restart the instruction | |
333 | @ | |
b86040a5 CM |
334 | ldr r2, [sp, #S_PSR] |
335 | svc_exit r2 @ return from exception | |
c4c5716e | 336 | UNWIND(.fnend ) |
93ed3970 | 337 | ENDPROC(__pabt_svc) |
1da177e4 LT |
338 | |
339 | .align 5 | |
49f680ea RK |
340 | .LCcralign: |
341 | .word cr_alignment | |
48d7927b | 342 | #ifdef MULTI_DABORT |
1da177e4 LT |
343 | .LCprocfns: |
344 | .word processor | |
345 | #endif | |
346 | .LCfp: | |
347 | .word fp_enter | |
1da177e4 LT |
348 | |
349 | /* | |
350 | * User mode handlers | |
2dede2d8 NP |
351 | * |
352 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 353 | */ |
2dede2d8 NP |
354 | |
355 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
356 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
357 | #endif | |
358 | ||
ccea7a19 | 359 | .macro usr_entry |
c4c5716e CM |
360 | UNWIND(.fnstart ) |
361 | UNWIND(.cantunwind ) @ don't unwind the user space | |
ccea7a19 | 362 | sub sp, sp, #S_FRAME_SIZE |
b86040a5 CM |
363 | ARM( stmib sp, {r1 - r12} ) |
364 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 RK |
365 | |
366 | ldmia r0, {r1 - r3} | |
367 | add r0, sp, #S_PC @ here for interlock avoidance | |
368 | mov r4, #-1 @ "" "" "" "" | |
369 | ||
370 | str r1, [sp] @ save the "real" r0 copied | |
371 | @ from the exception stack | |
1da177e4 LT |
372 | |
373 | @ | |
374 | @ We are now ready to fill in the remaining blanks on the stack: | |
375 | @ | |
376 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
377 | @ r3 - spsr_<exception> | |
378 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
379 | @ | |
380 | @ Also, separately save sp_usr and lr_usr | |
381 | @ | |
ccea7a19 | 382 | stmia r0, {r2 - r4} |
b86040a5 CM |
383 | ARM( stmdb r0, {sp, lr}^ ) |
384 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 LT |
385 | |
386 | @ | |
387 | @ Enable the alignment trap while in kernel mode | |
388 | @ | |
49f680ea | 389 | alignment_trap r0 |
1da177e4 LT |
390 | |
391 | @ | |
392 | @ Clear FP to mark the first stack frame | |
393 | @ | |
394 | zero_fp | |
0d928b0b UKK |
395 | |
396 | asm_trace_hardirqs_off | |
1da177e4 LT |
397 | .endm |
398 | ||
b49c0f24 NP |
399 | .macro kuser_cmpxchg_check |
400 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
401 | #ifndef CONFIG_MMU | |
402 | #warning "NPTL on non MMU needs fixing" | |
403 | #else | |
404 | @ Make sure our user space atomic helper is restarted | |
405 | @ if it was interrupted in a critical region. Here we | |
406 | @ perform a quick test inline since it should be false | |
407 | @ 99.9999% of the time. The rest is done out of line. | |
408 | cmp r2, #TASK_SIZE | |
409 | blhs kuser_cmpxchg_fixup | |
410 | #endif | |
411 | #endif | |
412 | .endm | |
413 | ||
1da177e4 LT |
414 | .align 5 |
415 | __dabt_usr: | |
ccea7a19 | 416 | usr_entry |
b49c0f24 | 417 | kuser_cmpxchg_check |
1da177e4 LT |
418 | |
419 | @ | |
420 | @ Call the processor-specific abort handler: | |
421 | @ | |
422 | @ r2 - aborted context pc | |
423 | @ r3 - aborted context cpsr | |
424 | @ | |
425 | @ The abort handler must return the aborted address in r0, and | |
426 | @ the fault status register in r1. | |
427 | @ | |
48d7927b | 428 | #ifdef MULTI_DABORT |
1da177e4 LT |
429 | ldr r4, .LCprocfns |
430 | mov lr, pc | |
48d7927b | 431 | ldr pc, [r4, #PROCESSOR_DABT_FUNC] |
1da177e4 | 432 | #else |
48d7927b | 433 | bl CPU_DABORT_HANDLER |
1da177e4 LT |
434 | #endif |
435 | ||
436 | @ | |
437 | @ IRQs on, then call the main handler | |
438 | @ | |
1ec42c0c | 439 | enable_irq |
1da177e4 | 440 | mov r2, sp |
b86040a5 | 441 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 442 | b do_DataAbort |
c4c5716e | 443 | UNWIND(.fnend ) |
93ed3970 | 444 | ENDPROC(__dabt_usr) |
1da177e4 LT |
445 | |
446 | .align 5 | |
447 | __irq_usr: | |
ccea7a19 | 448 | usr_entry |
b49c0f24 | 449 | kuser_cmpxchg_check |
1da177e4 | 450 | |
706fdd9f | 451 | get_thread_info tsk |
1da177e4 | 452 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
453 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
454 | add r7, r8, #1 @ increment it | |
455 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 456 | #endif |
ccea7a19 | 457 | |
187a51ad | 458 | irq_handler |
1da177e4 | 459 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
460 | ldr r0, [tsk, #TI_PREEMPT] |
461 | str r8, [tsk, #TI_PREEMPT] | |
1da177e4 | 462 | teq r0, r7 |
b86040a5 CM |
463 | ARM( strne r0, [r0, -r0] ) |
464 | THUMB( movne r0, #0 ) | |
465 | THUMB( strne r0, [r0] ) | |
1da177e4 | 466 | #endif |
7ad1bcb2 RK |
467 | #ifdef CONFIG_TRACE_IRQFLAGS |
468 | bl trace_hardirqs_on | |
469 | #endif | |
ccea7a19 | 470 | |
1da177e4 LT |
471 | mov why, #0 |
472 | b ret_to_user | |
c4c5716e | 473 | UNWIND(.fnend ) |
93ed3970 | 474 | ENDPROC(__irq_usr) |
1da177e4 LT |
475 | |
476 | .ltorg | |
477 | ||
478 | .align 5 | |
479 | __und_usr: | |
ccea7a19 | 480 | usr_entry |
1da177e4 | 481 | |
1da177e4 LT |
482 | @ |
483 | @ fall through to the emulation code, which returns using r9 if | |
484 | @ it has emulated the instruction, or the more conventional lr | |
485 | @ if we are to treat this as a real undefined instruction | |
486 | @ | |
487 | @ r0 - instruction | |
488 | @ | |
b86040a5 CM |
489 | adr r9, BSYM(ret_from_exception) |
490 | adr lr, BSYM(__und_usr_unknown) | |
cb170a45 | 491 | tst r3, #PSR_T_BIT @ Thumb mode? |
b86040a5 | 492 | itet eq @ explicit IT needed for the 1f label |
cb170a45 PB |
493 | subeq r4, r2, #4 @ ARM instr at LR - 4 |
494 | subne r4, r2, #2 @ Thumb instr at LR - 2 | |
495 | 1: ldreqt r0, [r4] | |
26584853 CM |
496 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
497 | reveq r0, r0 @ little endian instruction | |
498 | #endif | |
cb170a45 PB |
499 | beq call_fpe |
500 | @ Thumb instruction | |
501 | #if __LINUX_ARM_ARCH__ >= 7 | |
b86040a5 CM |
502 | 2: |
503 | ARM( ldrht r5, [r4], #2 ) | |
504 | THUMB( ldrht r5, [r4] ) | |
505 | THUMB( add r4, r4, #2 ) | |
cb170a45 PB |
506 | and r0, r5, #0xf800 @ mask bits 111x x... .... .... |
507 | cmp r0, #0xe800 @ 32bit instruction if xx != 0 | |
508 | blo __und_usr_unknown | |
509 | 3: ldrht r0, [r4] | |
510 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 | |
511 | orr r0, r0, r5, lsl #16 | |
512 | #else | |
513 | b __und_usr_unknown | |
514 | #endif | |
c4c5716e | 515 | UNWIND(.fnend ) |
93ed3970 | 516 | ENDPROC(__und_usr) |
cb170a45 | 517 | |
1da177e4 LT |
518 | @ |
519 | @ fallthrough to call_fpe | |
520 | @ | |
521 | ||
522 | /* | |
523 | * The out of line fixup for the ldrt above. | |
524 | */ | |
525 | .section .fixup, "ax" | |
cb170a45 | 526 | 4: mov pc, r9 |
1da177e4 LT |
527 | .previous |
528 | .section __ex_table,"a" | |
cb170a45 PB |
529 | .long 1b, 4b |
530 | #if __LINUX_ARM_ARCH__ >= 7 | |
531 | .long 2b, 4b | |
532 | .long 3b, 4b | |
533 | #endif | |
1da177e4 LT |
534 | .previous |
535 | ||
536 | /* | |
537 | * Check whether the instruction is a co-processor instruction. | |
538 | * If yes, we need to call the relevant co-processor handler. | |
539 | * | |
540 | * Note that we don't do a full check here for the co-processor | |
541 | * instructions; all instructions with bit 27 set are well | |
542 | * defined. The only instructions that should fault are the | |
543 | * co-processor instructions. However, we have to watch out | |
544 | * for the ARM6/ARM7 SWI bug. | |
545 | * | |
b5872db4 CM |
546 | * NEON is a special case that has to be handled here. Not all |
547 | * NEON instructions are co-processor instructions, so we have | |
548 | * to make a special case of checking for them. Plus, there's | |
549 | * five groups of them, so we have a table of mask/opcode pairs | |
550 | * to check against, and if any match then we branch off into the | |
551 | * NEON handler code. | |
552 | * | |
1da177e4 LT |
553 | * Emulators may wish to make use of the following registers: |
554 | * r0 = instruction opcode. | |
555 | * r2 = PC+4 | |
db6ccbb6 | 556 | * r9 = normal "successful" return address |
1da177e4 | 557 | * r10 = this threads thread_info structure. |
db6ccbb6 | 558 | * lr = unrecognised instruction return address |
1da177e4 | 559 | */ |
cb170a45 PB |
560 | @ |
561 | @ Fall-through from Thumb-2 __und_usr | |
562 | @ | |
563 | #ifdef CONFIG_NEON | |
564 | adr r6, .LCneon_thumb_opcodes | |
565 | b 2f | |
566 | #endif | |
1da177e4 | 567 | call_fpe: |
b5872db4 | 568 | #ifdef CONFIG_NEON |
cb170a45 | 569 | adr r6, .LCneon_arm_opcodes |
b5872db4 CM |
570 | 2: |
571 | ldr r7, [r6], #4 @ mask value | |
572 | cmp r7, #0 @ end mask? | |
573 | beq 1f | |
574 | and r8, r0, r7 | |
575 | ldr r7, [r6], #4 @ opcode bits matching in mask | |
576 | cmp r8, r7 @ NEON instruction? | |
577 | bne 2b | |
578 | get_thread_info r10 | |
579 | mov r7, #1 | |
580 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
581 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
582 | b do_vfp @ let VFP handler handle this | |
583 | 1: | |
584 | #endif | |
1da177e4 | 585 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 586 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
1da177e4 LT |
587 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) |
588 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
589 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
590 | #endif | |
591 | moveq pc, lr | |
592 | get_thread_info r10 @ get current thread | |
593 | and r8, r0, #0x00000f00 @ mask out CP number | |
b86040a5 | 594 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
595 | mov r7, #1 |
596 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
597 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
598 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
599 | #ifdef CONFIG_IWMMXT |
600 | @ Test if we need to give access to iWMMXt coprocessors | |
601 | ldr r5, [r10, #TI_FLAGS] | |
602 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
603 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
604 | bcs iwmmxt_task_enable | |
605 | #endif | |
b86040a5 CM |
606 | ARM( add pc, pc, r8, lsr #6 ) |
607 | THUMB( lsl r8, r8, #2 ) | |
608 | THUMB( add pc, r8 ) | |
609 | nop | |
610 | ||
a771fe6e | 611 | movw_pc lr @ CP#0 |
b86040a5 CM |
612 | W(b) do_fpe @ CP#1 (FPE) |
613 | W(b) do_fpe @ CP#2 (FPE) | |
a771fe6e | 614 | movw_pc lr @ CP#3 |
c17fad11 LB |
615 | #ifdef CONFIG_CRUNCH |
616 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
617 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
618 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
619 | #else | |
a771fe6e CM |
620 | movw_pc lr @ CP#4 |
621 | movw_pc lr @ CP#5 | |
622 | movw_pc lr @ CP#6 | |
c17fad11 | 623 | #endif |
a771fe6e CM |
624 | movw_pc lr @ CP#7 |
625 | movw_pc lr @ CP#8 | |
626 | movw_pc lr @ CP#9 | |
1da177e4 | 627 | #ifdef CONFIG_VFP |
b86040a5 CM |
628 | W(b) do_vfp @ CP#10 (VFP) |
629 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 630 | #else |
a771fe6e CM |
631 | movw_pc lr @ CP#10 (VFP) |
632 | movw_pc lr @ CP#11 (VFP) | |
1da177e4 | 633 | #endif |
a771fe6e CM |
634 | movw_pc lr @ CP#12 |
635 | movw_pc lr @ CP#13 | |
636 | movw_pc lr @ CP#14 (Debug) | |
637 | movw_pc lr @ CP#15 (Control) | |
1da177e4 | 638 | |
b5872db4 CM |
639 | #ifdef CONFIG_NEON |
640 | .align 6 | |
641 | ||
cb170a45 | 642 | .LCneon_arm_opcodes: |
b5872db4 CM |
643 | .word 0xfe000000 @ mask |
644 | .word 0xf2000000 @ opcode | |
645 | ||
646 | .word 0xff100000 @ mask | |
647 | .word 0xf4000000 @ opcode | |
648 | ||
cb170a45 PB |
649 | .word 0x00000000 @ mask |
650 | .word 0x00000000 @ opcode | |
651 | ||
652 | .LCneon_thumb_opcodes: | |
653 | .word 0xef000000 @ mask | |
654 | .word 0xef000000 @ opcode | |
655 | ||
656 | .word 0xff100000 @ mask | |
657 | .word 0xf9000000 @ opcode | |
658 | ||
b5872db4 CM |
659 | .word 0x00000000 @ mask |
660 | .word 0x00000000 @ opcode | |
661 | #endif | |
662 | ||
1da177e4 | 663 | do_fpe: |
5d25ac03 | 664 | enable_irq |
1da177e4 LT |
665 | ldr r4, .LCfp |
666 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
667 | ldr pc, [r4] @ Call FP module USR entry point | |
668 | ||
669 | /* | |
670 | * The FP module is called with these registers set: | |
671 | * r0 = instruction | |
672 | * r2 = PC+4 | |
673 | * r9 = normal "successful" return address | |
674 | * r10 = FP workspace | |
675 | * lr = unrecognised FP instruction return address | |
676 | */ | |
677 | ||
678 | .data | |
679 | ENTRY(fp_enter) | |
db6ccbb6 | 680 | .word no_fp |
785d3cd2 | 681 | .previous |
1da177e4 | 682 | |
83e686ea CM |
683 | ENTRY(no_fp) |
684 | mov pc, lr | |
685 | ENDPROC(no_fp) | |
db6ccbb6 RK |
686 | |
687 | __und_usr_unknown: | |
ecbab71c | 688 | enable_irq |
1da177e4 | 689 | mov r0, sp |
b86040a5 | 690 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 691 | b do_undefinstr |
93ed3970 | 692 | ENDPROC(__und_usr_unknown) |
1da177e4 LT |
693 | |
694 | .align 5 | |
695 | __pabt_usr: | |
ccea7a19 | 696 | usr_entry |
1da177e4 | 697 | |
48d7927b | 698 | mov r0, r2 @ pass address of aborted instruction. |
4fb28474 | 699 | #ifdef MULTI_PABORT |
48d7927b PB |
700 | ldr r4, .LCprocfns |
701 | mov lr, pc | |
702 | ldr pc, [r4, #PROCESSOR_PABT_FUNC] | |
703 | #else | |
4fb28474 | 704 | bl CPU_PABORT_HANDLER |
48d7927b | 705 | #endif |
1ec42c0c | 706 | enable_irq @ Enable interrupts |
4fb28474 | 707 | mov r2, sp @ regs |
1da177e4 | 708 | bl do_PrefetchAbort @ call abort handler |
c4c5716e | 709 | UNWIND(.fnend ) |
1da177e4 LT |
710 | /* fall through */ |
711 | /* | |
712 | * This is the return code to user mode for abort handlers | |
713 | */ | |
714 | ENTRY(ret_from_exception) | |
c4c5716e CM |
715 | UNWIND(.fnstart ) |
716 | UNWIND(.cantunwind ) | |
1da177e4 LT |
717 | get_thread_info tsk |
718 | mov why, #0 | |
719 | b ret_to_user | |
c4c5716e | 720 | UNWIND(.fnend ) |
93ed3970 CM |
721 | ENDPROC(__pabt_usr) |
722 | ENDPROC(ret_from_exception) | |
1da177e4 LT |
723 | |
724 | /* | |
725 | * Register switch for ARMv3 and ARMv4 processors | |
726 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
727 | * previous and next are guaranteed not to be the same. | |
728 | */ | |
729 | ENTRY(__switch_to) | |
c4c5716e CM |
730 | UNWIND(.fnstart ) |
731 | UNWIND(.cantunwind ) | |
1da177e4 LT |
732 | add ip, r1, #TI_CPU_SAVE |
733 | ldr r3, [r2, #TI_TP_VALUE] | |
b86040a5 CM |
734 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
735 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
736 | THUMB( str sp, [ip], #4 ) | |
737 | THUMB( str lr, [ip], #4 ) | |
d6551e88 RK |
738 | #ifdef CONFIG_MMU |
739 | ldr r6, [r2, #TI_CPU_DOMAIN] | |
afeb90ca | 740 | #endif |
4b0e07a5 | 741 | #if defined(CONFIG_HAS_TLS_REG) |
2d2669b6 | 742 | mcr p15, 0, r3, c13, c0, 3 @ set TLS register |
4b0e07a5 | 743 | #elif !defined(CONFIG_TLS_REG_EMUL) |
1da177e4 | 744 | mov r4, #0xffff0fff |
2d2669b6 NP |
745 | str r3, [r4, #-15] @ TLS val at 0xffff0ff0 |
746 | #endif | |
afeb90ca | 747 | #ifdef CONFIG_MMU |
1da177e4 | 748 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 749 | #endif |
d6551e88 RK |
750 | mov r5, r0 |
751 | add r4, r2, #TI_CPU_SAVE | |
752 | ldr r0, =thread_notify_head | |
753 | mov r1, #THREAD_NOTIFY_SWITCH | |
754 | bl atomic_notifier_call_chain | |
b86040a5 | 755 | THUMB( mov ip, r4 ) |
d6551e88 | 756 | mov r0, r5 |
b86040a5 CM |
757 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
758 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
759 | THUMB( ldr sp, [ip], #4 ) | |
760 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 761 | UNWIND(.fnend ) |
93ed3970 | 762 | ENDPROC(__switch_to) |
1da177e4 LT |
763 | |
764 | __INIT | |
2d2669b6 NP |
765 | |
766 | /* | |
767 | * User helpers. | |
768 | * | |
769 | * These are segment of kernel provided user code reachable from user space | |
770 | * at a fixed address in kernel memory. This is used to provide user space | |
771 | * with some operations which require kernel help because of unimplemented | |
772 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
773 | * this code to be executed directly in user mode for best efficiency but | |
774 | * which is too intimate with the kernel counter part to be left to user | |
775 | * libraries. In fact this code might even differ from one CPU to another | |
776 | * depending on the available instruction set and restrictions like on | |
777 | * SMP systems. In other words, the kernel reserves the right to change | |
778 | * this code as needed without warning. Only the entry points and their | |
779 | * results are guaranteed to be stable. | |
780 | * | |
781 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
782 | * vector page. New segments (if ever needed) must be added in front of | |
783 | * existing ones. This mechanism should be used only for things that are | |
784 | * really small and justified, and not be abused freely. | |
785 | * | |
786 | * User space is expected to implement those things inline when optimizing | |
787 | * for a processor that has the necessary native support, but only if such | |
788 | * resulting binaries are already to be incompatible with earlier ARM | |
789 | * processors due to the use of unsupported instructions other than what | |
790 | * is provided here. In other words don't make binaries unable to run on | |
791 | * earlier processors just for the sake of not using these kernel helpers | |
792 | * if your compiled code is not going to use the new instructions for other | |
793 | * purpose. | |
794 | */ | |
b86040a5 | 795 | THUMB( .arm ) |
2d2669b6 | 796 | |
ba9b5d76 NP |
797 | .macro usr_ret, reg |
798 | #ifdef CONFIG_ARM_THUMB | |
799 | bx \reg | |
800 | #else | |
801 | mov pc, \reg | |
802 | #endif | |
803 | .endm | |
804 | ||
2d2669b6 NP |
805 | .align 5 |
806 | .globl __kuser_helper_start | |
807 | __kuser_helper_start: | |
808 | ||
7c612bfd NP |
809 | /* |
810 | * Reference prototype: | |
811 | * | |
812 | * void __kernel_memory_barrier(void) | |
813 | * | |
814 | * Input: | |
815 | * | |
816 | * lr = return address | |
817 | * | |
818 | * Output: | |
819 | * | |
820 | * none | |
821 | * | |
822 | * Clobbered: | |
823 | * | |
b49c0f24 | 824 | * none |
7c612bfd NP |
825 | * |
826 | * Definition and user space usage example: | |
827 | * | |
828 | * typedef void (__kernel_dmb_t)(void); | |
829 | * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) | |
830 | * | |
831 | * Apply any needed memory barrier to preserve consistency with data modified | |
832 | * manually and __kuser_cmpxchg usage. | |
833 | * | |
834 | * This could be used as follows: | |
835 | * | |
836 | * #define __kernel_dmb() \ | |
837 | * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ | |
6896eec0 | 838 | * : : : "r0", "lr","cc" ) |
7c612bfd NP |
839 | */ |
840 | ||
841 | __kuser_memory_barrier: @ 0xffff0fa0 | |
bac4e960 | 842 | smp_dmb |
ba9b5d76 | 843 | usr_ret lr |
7c612bfd NP |
844 | |
845 | .align 5 | |
846 | ||
2d2669b6 NP |
847 | /* |
848 | * Reference prototype: | |
849 | * | |
850 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
851 | * | |
852 | * Input: | |
853 | * | |
854 | * r0 = oldval | |
855 | * r1 = newval | |
856 | * r2 = ptr | |
857 | * lr = return address | |
858 | * | |
859 | * Output: | |
860 | * | |
861 | * r0 = returned value (zero or non-zero) | |
862 | * C flag = set if r0 == 0, clear if r0 != 0 | |
863 | * | |
864 | * Clobbered: | |
865 | * | |
866 | * r3, ip, flags | |
867 | * | |
868 | * Definition and user space usage example: | |
869 | * | |
870 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
871 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
872 | * | |
873 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
874 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
875 | * The C flag is also set if *ptr was changed to allow for assembly | |
876 | * optimization in the calling code. | |
877 | * | |
5964eae8 NP |
878 | * Notes: |
879 | * | |
880 | * - This routine already includes memory barriers as needed. | |
881 | * | |
2d2669b6 NP |
882 | * For example, a user space atomic_add implementation could look like this: |
883 | * | |
884 | * #define atomic_add(ptr, val) \ | |
885 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
886 | * register unsigned int __result asm("r1"); \ | |
887 | * asm volatile ( \ | |
888 | * "1: @ atomic_add\n\t" \ | |
889 | * "ldr r0, [r2]\n\t" \ | |
890 | * "mov r3, #0xffff0fff\n\t" \ | |
891 | * "add lr, pc, #4\n\t" \ | |
892 | * "add r1, r0, %2\n\t" \ | |
893 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
894 | * "bcc 1b" \ | |
895 | * : "=&r" (__result) \ | |
896 | * : "r" (__ptr), "rIL" (val) \ | |
897 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
898 | * __result; }) | |
899 | */ | |
900 | ||
901 | __kuser_cmpxchg: @ 0xffff0fc0 | |
902 | ||
dcef1f63 | 903 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 904 | |
dcef1f63 NP |
905 | /* |
906 | * Poor you. No fast solution possible... | |
907 | * The kernel itself must perform the operation. | |
908 | * A special ghost syscall is used for that (see traps.c). | |
909 | */ | |
5e097445 NP |
910 | stmfd sp!, {r7, lr} |
911 | mov r7, #0xff00 @ 0xfff0 into r7 for EABI | |
912 | orr r7, r7, #0xf0 | |
dcef1f63 | 913 | swi #0x9ffff0 |
5e097445 | 914 | ldmfd sp!, {r7, pc} |
dcef1f63 NP |
915 | |
916 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 917 | |
b49c0f24 NP |
918 | #ifdef CONFIG_MMU |
919 | ||
2d2669b6 | 920 | /* |
b49c0f24 NP |
921 | * The only thing that can break atomicity in this cmpxchg |
922 | * implementation is either an IRQ or a data abort exception | |
923 | * causing another process/thread to be scheduled in the middle | |
924 | * of the critical sequence. To prevent this, code is added to | |
925 | * the IRQ and data abort exception handlers to set the pc back | |
926 | * to the beginning of the critical section if it is found to be | |
927 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 928 | */ |
b49c0f24 NP |
929 | 1: ldr r3, [r2] @ load current val |
930 | subs r3, r3, r0 @ compare with oldval | |
931 | 2: streq r1, [r2] @ store newval if eq | |
932 | rsbs r0, r3, #0 @ set return val and C flag | |
933 | usr_ret lr | |
934 | ||
935 | .text | |
936 | kuser_cmpxchg_fixup: | |
937 | @ Called from kuser_cmpxchg_check macro. | |
938 | @ r2 = address of interrupted insn (must be preserved). | |
939 | @ sp = saved regs. r7 and r8 are clobbered. | |
940 | @ 1b = first critical insn, 2b = last critical insn. | |
941 | @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b. | |
942 | mov r7, #0xffff0fff | |
943 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
944 | subs r8, r2, r7 | |
945 | rsbcss r8, r8, #(2b - 1b) | |
946 | strcs r7, [sp, #S_PC] | |
947 | mov pc, lr | |
948 | .previous | |
949 | ||
49bca4c2 NP |
950 | #else |
951 | #warning "NPTL on non MMU needs fixing" | |
952 | mov r0, #-1 | |
953 | adds r0, r0, #0 | |
ba9b5d76 | 954 | usr_ret lr |
b49c0f24 | 955 | #endif |
2d2669b6 NP |
956 | |
957 | #else | |
958 | ||
7c612bfd NP |
959 | #ifdef CONFIG_SMP |
960 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
961 | #endif | |
b49c0f24 | 962 | 1: ldrex r3, [r2] |
2d2669b6 NP |
963 | subs r3, r3, r0 |
964 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
965 | teqeq r3, #1 |
966 | beq 1b | |
2d2669b6 | 967 | rsbs r0, r3, #0 |
b49c0f24 | 968 | /* beware -- each __kuser slot must be 8 instructions max */ |
7c612bfd | 969 | #ifdef CONFIG_SMP |
b49c0f24 NP |
970 | b __kuser_memory_barrier |
971 | #else | |
ba9b5d76 | 972 | usr_ret lr |
b49c0f24 | 973 | #endif |
2d2669b6 NP |
974 | |
975 | #endif | |
976 | ||
977 | .align 5 | |
978 | ||
979 | /* | |
980 | * Reference prototype: | |
981 | * | |
982 | * int __kernel_get_tls(void) | |
983 | * | |
984 | * Input: | |
985 | * | |
986 | * lr = return address | |
987 | * | |
988 | * Output: | |
989 | * | |
990 | * r0 = TLS value | |
991 | * | |
992 | * Clobbered: | |
993 | * | |
b49c0f24 | 994 | * none |
2d2669b6 NP |
995 | * |
996 | * Definition and user space usage example: | |
997 | * | |
998 | * typedef int (__kernel_get_tls_t)(void); | |
999 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
1000 | * | |
1001 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
1002 | * | |
1003 | * This could be used as follows: | |
1004 | * | |
1005 | * #define __kernel_get_tls() \ | |
1006 | * ({ register unsigned int __val asm("r0"); \ | |
1007 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
1008 | * : "=r" (__val) : : "lr","cc" ); \ | |
1009 | * __val; }) | |
1010 | */ | |
1011 | ||
1012 | __kuser_get_tls: @ 0xffff0fe0 | |
1013 | ||
4b0e07a5 | 1014 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) |
2d2669b6 | 1015 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 |
2d2669b6 | 1016 | #else |
2d2669b6 | 1017 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register |
2d2669b6 | 1018 | #endif |
ba9b5d76 | 1019 | usr_ret lr |
2d2669b6 NP |
1020 | |
1021 | .rep 5 | |
1022 | .word 0 @ pad up to __kuser_helper_version | |
1023 | .endr | |
1024 | ||
1025 | /* | |
1026 | * Reference declaration: | |
1027 | * | |
1028 | * extern unsigned int __kernel_helper_version; | |
1029 | * | |
1030 | * Definition and user space usage example: | |
1031 | * | |
1032 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
1033 | * | |
1034 | * User space may read this to determine the curent number of helpers | |
1035 | * available. | |
1036 | */ | |
1037 | ||
1038 | __kuser_helper_version: @ 0xffff0ffc | |
1039 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
1040 | ||
1041 | .globl __kuser_helper_end | |
1042 | __kuser_helper_end: | |
1043 | ||
b86040a5 | 1044 | THUMB( .thumb ) |
2d2669b6 | 1045 | |
1da177e4 LT |
1046 | /* |
1047 | * Vector stubs. | |
1048 | * | |
7933523d RK |
1049 | * This code is copied to 0xffff0200 so we can use branches in the |
1050 | * vectors, rather than ldr's. Note that this code must not | |
1051 | * exceed 0x300 bytes. | |
1da177e4 LT |
1052 | * |
1053 | * Common stub entry macro: | |
1054 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
1055 | * |
1056 | * SP points to a minimal amount of processor-private memory, the address | |
1057 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 1058 | */ |
b7ec4795 | 1059 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
1060 | .align 5 |
1061 | ||
1062 | vector_\name: | |
1da177e4 LT |
1063 | .if \correction |
1064 | sub lr, lr, #\correction | |
1065 | .endif | |
ccea7a19 RK |
1066 | |
1067 | @ | |
1068 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
1069 | @ (parent CPSR) | |
1070 | @ | |
1071 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 1072 | mrs lr, spsr |
ccea7a19 RK |
1073 | str lr, [sp, #8] @ save spsr |
1074 | ||
1da177e4 | 1075 | @ |
ccea7a19 | 1076 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 1077 | @ |
ccea7a19 | 1078 | mrs r0, cpsr |
b86040a5 | 1079 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 1080 | msr spsr_cxsf, r0 |
1da177e4 | 1081 | |
ccea7a19 RK |
1082 | @ |
1083 | @ the branch table must immediately follow this code | |
1084 | @ | |
ccea7a19 | 1085 | and lr, lr, #0x0f |
b86040a5 CM |
1086 | THUMB( adr r0, 1f ) |
1087 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 1088 | mov r0, sp |
b86040a5 | 1089 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 1090 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 1091 | ENDPROC(vector_\name) |
88987ef9 CM |
1092 | |
1093 | .align 2 | |
1094 | @ handler addresses follow this label | |
1095 | 1: | |
1da177e4 LT |
1096 | .endm |
1097 | ||
7933523d | 1098 | .globl __stubs_start |
1da177e4 LT |
1099 | __stubs_start: |
1100 | /* | |
1101 | * Interrupt dispatcher | |
1102 | */ | |
b7ec4795 | 1103 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1104 | |
1105 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1106 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1107 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1108 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1109 | .long __irq_invalid @ 4 | |
1110 | .long __irq_invalid @ 5 | |
1111 | .long __irq_invalid @ 6 | |
1112 | .long __irq_invalid @ 7 | |
1113 | .long __irq_invalid @ 8 | |
1114 | .long __irq_invalid @ 9 | |
1115 | .long __irq_invalid @ a | |
1116 | .long __irq_invalid @ b | |
1117 | .long __irq_invalid @ c | |
1118 | .long __irq_invalid @ d | |
1119 | .long __irq_invalid @ e | |
1120 | .long __irq_invalid @ f | |
1121 | ||
1122 | /* | |
1123 | * Data abort dispatcher | |
1124 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1125 | */ | |
b7ec4795 | 1126 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1127 | |
1128 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1129 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1130 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1131 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1132 | .long __dabt_invalid @ 4 | |
1133 | .long __dabt_invalid @ 5 | |
1134 | .long __dabt_invalid @ 6 | |
1135 | .long __dabt_invalid @ 7 | |
1136 | .long __dabt_invalid @ 8 | |
1137 | .long __dabt_invalid @ 9 | |
1138 | .long __dabt_invalid @ a | |
1139 | .long __dabt_invalid @ b | |
1140 | .long __dabt_invalid @ c | |
1141 | .long __dabt_invalid @ d | |
1142 | .long __dabt_invalid @ e | |
1143 | .long __dabt_invalid @ f | |
1144 | ||
1145 | /* | |
1146 | * Prefetch abort dispatcher | |
1147 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1148 | */ | |
b7ec4795 | 1149 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1150 | |
1151 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1152 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1153 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1154 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1155 | .long __pabt_invalid @ 4 | |
1156 | .long __pabt_invalid @ 5 | |
1157 | .long __pabt_invalid @ 6 | |
1158 | .long __pabt_invalid @ 7 | |
1159 | .long __pabt_invalid @ 8 | |
1160 | .long __pabt_invalid @ 9 | |
1161 | .long __pabt_invalid @ a | |
1162 | .long __pabt_invalid @ b | |
1163 | .long __pabt_invalid @ c | |
1164 | .long __pabt_invalid @ d | |
1165 | .long __pabt_invalid @ e | |
1166 | .long __pabt_invalid @ f | |
1167 | ||
1168 | /* | |
1169 | * Undef instr entry dispatcher | |
1170 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1171 | */ | |
b7ec4795 | 1172 | vector_stub und, UND_MODE |
1da177e4 LT |
1173 | |
1174 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1175 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1176 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1177 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1178 | .long __und_invalid @ 4 | |
1179 | .long __und_invalid @ 5 | |
1180 | .long __und_invalid @ 6 | |
1181 | .long __und_invalid @ 7 | |
1182 | .long __und_invalid @ 8 | |
1183 | .long __und_invalid @ 9 | |
1184 | .long __und_invalid @ a | |
1185 | .long __und_invalid @ b | |
1186 | .long __und_invalid @ c | |
1187 | .long __und_invalid @ d | |
1188 | .long __und_invalid @ e | |
1189 | .long __und_invalid @ f | |
1190 | ||
1191 | .align 5 | |
1192 | ||
1193 | /*============================================================================= | |
1194 | * Undefined FIQs | |
1195 | *----------------------------------------------------------------------------- | |
1196 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1197 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1198 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1199 | * damage alert! I don't think that we can execute any code in here in any | |
1200 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1201 | * get out of that mode without clobbering one register. | |
1202 | */ | |
1203 | vector_fiq: | |
1204 | disable_fiq | |
1205 | subs pc, lr, #4 | |
1206 | ||
1207 | /*============================================================================= | |
1208 | * Address exception handler | |
1209 | *----------------------------------------------------------------------------- | |
1210 | * These aren't too critical. | |
1211 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1212 | */ | |
1213 | ||
1214 | vector_addrexcptn: | |
1215 | b vector_addrexcptn | |
1216 | ||
1217 | /* | |
1218 | * We group all the following data together to optimise | |
1219 | * for CPUs with separate I & D caches. | |
1220 | */ | |
1221 | .align 5 | |
1222 | ||
1223 | .LCvswi: | |
1224 | .word vector_swi | |
1225 | ||
7933523d | 1226 | .globl __stubs_end |
1da177e4 LT |
1227 | __stubs_end: |
1228 | ||
7933523d | 1229 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1230 | |
7933523d RK |
1231 | .globl __vectors_start |
1232 | __vectors_start: | |
b86040a5 CM |
1233 | ARM( swi SYS_ERROR0 ) |
1234 | THUMB( svc #0 ) | |
1235 | THUMB( nop ) | |
1236 | W(b) vector_und + stubs_offset | |
1237 | W(ldr) pc, .LCvswi + stubs_offset | |
1238 | W(b) vector_pabt + stubs_offset | |
1239 | W(b) vector_dabt + stubs_offset | |
1240 | W(b) vector_addrexcptn + stubs_offset | |
1241 | W(b) vector_irq + stubs_offset | |
1242 | W(b) vector_fiq + stubs_offset | |
7933523d RK |
1243 | |
1244 | .globl __vectors_end | |
1245 | __vectors_end: | |
1da177e4 LT |
1246 | |
1247 | .data | |
1248 | ||
1da177e4 LT |
1249 | .globl cr_alignment |
1250 | .globl cr_no_alignment | |
1251 | cr_alignment: | |
1252 | .space 4 | |
1253 | cr_no_alignment: | |
1254 | .space 4 |