Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
f09b9979 | 18 | #include <asm/memory.h> |
753790e7 RK |
19 | #include <asm/glue-df.h> |
20 | #include <asm/glue-pf.h> | |
1da177e4 | 21 | #include <asm/vfpmacros.h> |
a09e64fb | 22 | #include <mach/entry-macro.S> |
d6551e88 | 23 | #include <asm/thread_notify.h> |
c4c5716e | 24 | #include <asm/unwind.h> |
cc20d429 | 25 | #include <asm/unistd.h> |
f159f4ed | 26 | #include <asm/tls.h> |
1da177e4 LT |
27 | |
28 | #include "entry-header.S" | |
cd544ce7 | 29 | #include <asm/entry-macro-multi.S> |
1da177e4 | 30 | |
187a51ad RK |
31 | /* |
32 | * Interrupt handling. Preserves r7, r8, r9 | |
33 | */ | |
34 | .macro irq_handler | |
52108641 | 35 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
36 | ldr r5, =handle_arch_irq | |
37 | mov r0, sp | |
38 | ldr r5, [r5] | |
39 | adr lr, BSYM(9997f) | |
40 | teq r5, #0 | |
41 | movne pc, r5 | |
37ee16ae | 42 | #endif |
cd544ce7 | 43 | arch_irq_handler_default |
f00ec48f | 44 | 9997: |
187a51ad RK |
45 | .endm |
46 | ||
ac8b9c1c | 47 | .macro pabt_helper |
8b418616 | 48 | @ PABORT handler takes fault address in r4 |
ac8b9c1c | 49 | #ifdef MULTI_PABORT |
0402bece | 50 | ldr ip, .LCprocfns |
ac8b9c1c | 51 | mov lr, pc |
0402bece | 52 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
ac8b9c1c RK |
53 | #else |
54 | bl CPU_PABORT_HANDLER | |
55 | #endif | |
56 | .endm | |
57 | ||
58 | .macro dabt_helper | |
b059bdc3 RK |
59 | mov r2, r4 |
60 | mov r3, r5 | |
ac8b9c1c RK |
61 | |
62 | @ | |
63 | @ Call the processor-specific abort handler: | |
64 | @ | |
65 | @ r2 - aborted context pc | |
66 | @ r3 - aborted context cpsr | |
67 | @ | |
68 | @ The abort handler must return the aborted address in r0, and | |
69 | @ the fault status register in r1. r9 must be preserved. | |
70 | @ | |
71 | #ifdef MULTI_DABORT | |
0402bece | 72 | ldr ip, .LCprocfns |
ac8b9c1c | 73 | mov lr, pc |
0402bece | 74 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
ac8b9c1c RK |
75 | #else |
76 | bl CPU_DABORT_HANDLER | |
77 | #endif | |
78 | .endm | |
79 | ||
785d3cd2 NP |
80 | #ifdef CONFIG_KPROBES |
81 | .section .kprobes.text,"ax",%progbits | |
82 | #else | |
83 | .text | |
84 | #endif | |
85 | ||
1da177e4 LT |
86 | /* |
87 | * Invalid mode handlers | |
88 | */ | |
ccea7a19 RK |
89 | .macro inv_entry, reason |
90 | sub sp, sp, #S_FRAME_SIZE | |
b86040a5 CM |
91 | ARM( stmib sp, {r1 - lr} ) |
92 | THUMB( stmia sp, {r0 - r12} ) | |
93 | THUMB( str sp, [sp, #S_SP] ) | |
94 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
95 | mov r1, #\reason |
96 | .endm | |
97 | ||
98 | __pabt_invalid: | |
ccea7a19 RK |
99 | inv_entry BAD_PREFETCH |
100 | b common_invalid | |
93ed3970 | 101 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
102 | |
103 | __dabt_invalid: | |
ccea7a19 RK |
104 | inv_entry BAD_DATA |
105 | b common_invalid | |
93ed3970 | 106 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
107 | |
108 | __irq_invalid: | |
ccea7a19 RK |
109 | inv_entry BAD_IRQ |
110 | b common_invalid | |
93ed3970 | 111 | ENDPROC(__irq_invalid) |
1da177e4 LT |
112 | |
113 | __und_invalid: | |
ccea7a19 RK |
114 | inv_entry BAD_UNDEFINSTR |
115 | ||
116 | @ | |
117 | @ XXX fall through to common_invalid | |
118 | @ | |
119 | ||
120 | @ | |
121 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
122 | @ | |
123 | common_invalid: | |
124 | zero_fp | |
125 | ||
126 | ldmia r0, {r4 - r6} | |
127 | add r0, sp, #S_PC @ here for interlock avoidance | |
128 | mov r7, #-1 @ "" "" "" "" | |
129 | str r4, [sp] @ save preserved r0 | |
130 | stmia r0, {r5 - r7} @ lr_<exception>, | |
131 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 132 | |
1da177e4 | 133 | mov r0, sp |
1da177e4 | 134 | b bad_mode |
93ed3970 | 135 | ENDPROC(__und_invalid) |
1da177e4 LT |
136 | |
137 | /* | |
138 | * SVC mode handlers | |
139 | */ | |
2dede2d8 NP |
140 | |
141 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
142 | #define SPFIX(code...) code | |
143 | #else | |
144 | #define SPFIX(code...) | |
145 | #endif | |
146 | ||
d30a0c8b | 147 | .macro svc_entry, stack_hole=0 |
c4c5716e CM |
148 | UNWIND(.fnstart ) |
149 | UNWIND(.save {r0 - pc} ) | |
b86040a5 CM |
150 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) |
151 | #ifdef CONFIG_THUMB2_KERNEL | |
152 | SPFIX( str r0, [sp] ) @ temporarily saved | |
153 | SPFIX( mov r0, sp ) | |
154 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
155 | SPFIX( ldr r0, [sp] ) @ restored | |
156 | #else | |
2dede2d8 | 157 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
158 | #endif |
159 | SPFIX( subeq sp, sp, #4 ) | |
160 | stmia sp, {r1 - r12} | |
ccea7a19 | 161 | |
b059bdc3 RK |
162 | ldmia r0, {r3 - r5} |
163 | add r7, sp, #S_SP - 4 @ here for interlock avoidance | |
164 | mov r6, #-1 @ "" "" "" "" | |
165 | add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4) | |
166 | SPFIX( addeq r2, r2, #4 ) | |
167 | str r3, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
168 | @ from the exception stack |
169 | ||
b059bdc3 | 170 | mov r3, lr |
1da177e4 LT |
171 | |
172 | @ | |
173 | @ We are now ready to fill in the remaining blanks on the stack: | |
174 | @ | |
b059bdc3 RK |
175 | @ r2 - sp_svc |
176 | @ r3 - lr_svc | |
177 | @ r4 - lr_<exception>, already fixed up for correct return/restart | |
178 | @ r5 - spsr_<exception> | |
179 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 | 180 | @ |
b059bdc3 | 181 | stmia r7, {r2 - r6} |
1da177e4 LT |
182 | .endm |
183 | ||
184 | .align 5 | |
185 | __dabt_svc: | |
ccea7a19 | 186 | svc_entry |
1da177e4 | 187 | |
02fe2845 RK |
188 | #ifdef CONFIG_TRACE_IRQFLAGS |
189 | bl trace_hardirqs_off | |
190 | #endif | |
1da177e4 | 191 | |
ac8b9c1c | 192 | dabt_helper |
1da177e4 LT |
193 | |
194 | @ | |
02fe2845 | 195 | @ call main handler |
1da177e4 | 196 | @ |
1da177e4 LT |
197 | mov r2, sp |
198 | bl do_DataAbort | |
199 | ||
200 | @ | |
201 | @ IRQs off again before pulling preserved data off the stack | |
202 | @ | |
ac78884e | 203 | disable_irq_notrace |
1da177e4 LT |
204 | |
205 | @ | |
206 | @ restore SPSR and restart the instruction | |
207 | @ | |
b059bdc3 | 208 | ldr r5, [sp, #S_PSR] |
02fe2845 RK |
209 | #ifdef CONFIG_TRACE_IRQFLAGS |
210 | tst r5, #PSR_I_BIT | |
211 | bleq trace_hardirqs_on | |
212 | tst r5, #PSR_I_BIT | |
213 | blne trace_hardirqs_off | |
214 | #endif | |
b059bdc3 | 215 | svc_exit r5 @ return from exception |
c4c5716e | 216 | UNWIND(.fnend ) |
93ed3970 | 217 | ENDPROC(__dabt_svc) |
1da177e4 LT |
218 | |
219 | .align 5 | |
220 | __irq_svc: | |
ccea7a19 RK |
221 | svc_entry |
222 | ||
ac78884e RK |
223 | #ifdef CONFIG_TRACE_IRQFLAGS |
224 | bl trace_hardirqs_off | |
225 | #endif | |
ccea7a19 | 226 | |
187a51ad | 227 | irq_handler |
1613cc11 | 228 | |
1da177e4 | 229 | #ifdef CONFIG_PREEMPT |
1613cc11 RK |
230 | get_thread_info tsk |
231 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
706fdd9f | 232 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
233 | teq r8, #0 @ if preempt count != 0 |
234 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
235 | tst r0, #_TIF_NEED_RESCHED |
236 | blne svc_preempt | |
1da177e4 | 237 | #endif |
b059bdc3 | 238 | ldr r5, [sp, #S_PSR] |
7ad1bcb2 | 239 | #ifdef CONFIG_TRACE_IRQFLAGS |
fbab1c80 RK |
240 | @ The parent context IRQs must have been enabled to get here in |
241 | @ the first place, so there's no point checking the PSR I bit. | |
242 | bl trace_hardirqs_on | |
7ad1bcb2 | 243 | #endif |
b059bdc3 | 244 | svc_exit r5 @ return from exception |
c4c5716e | 245 | UNWIND(.fnend ) |
93ed3970 | 246 | ENDPROC(__irq_svc) |
1da177e4 LT |
247 | |
248 | .ltorg | |
249 | ||
250 | #ifdef CONFIG_PREEMPT | |
251 | svc_preempt: | |
28fab1a2 | 252 | mov r8, lr |
1da177e4 | 253 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 254 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 255 | tst r0, #_TIF_NEED_RESCHED |
28fab1a2 | 256 | moveq pc, r8 @ go again |
1da177e4 LT |
257 | b 1b |
258 | #endif | |
259 | ||
260 | .align 5 | |
261 | __und_svc: | |
d30a0c8b NP |
262 | #ifdef CONFIG_KPROBES |
263 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
264 | @ it obviously needs free stack space which then will belong to | |
265 | @ the saved context. | |
266 | svc_entry 64 | |
267 | #else | |
ccea7a19 | 268 | svc_entry |
d30a0c8b | 269 | #endif |
1da177e4 | 270 | |
df295df6 RK |
271 | #ifdef CONFIG_TRACE_IRQFLAGS |
272 | bl trace_hardirqs_off | |
273 | #endif | |
274 | ||
1da177e4 LT |
275 | @ |
276 | @ call emulation code, which returns using r9 if it has emulated | |
277 | @ the instruction, or the more conventional lr if we are to treat | |
278 | @ this as a real undefined instruction | |
279 | @ | |
280 | @ r0 - instruction | |
281 | @ | |
83e686ea | 282 | #ifndef CONFIG_THUMB2_KERNEL |
b059bdc3 | 283 | ldr r0, [r4, #-4] |
83e686ea | 284 | #else |
b059bdc3 | 285 | ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 |
83e686ea CM |
286 | and r9, r0, #0xf800 |
287 | cmp r9, #0xe800 @ 32-bit instruction if xx >= 0 | |
b059bdc3 | 288 | ldrhhs r9, [r4] @ bottom 16 bits |
83e686ea CM |
289 | orrhs r0, r9, r0, lsl #16 |
290 | #endif | |
b86040a5 | 291 | adr r9, BSYM(1f) |
b059bdc3 | 292 | mov r2, r4 |
1da177e4 LT |
293 | bl call_fpe |
294 | ||
295 | mov r0, sp @ struct pt_regs *regs | |
296 | bl do_undefinstr | |
297 | ||
298 | @ | |
299 | @ IRQs off again before pulling preserved data off the stack | |
300 | @ | |
ac78884e | 301 | 1: disable_irq_notrace |
1da177e4 LT |
302 | |
303 | @ | |
304 | @ restore SPSR and restart the instruction | |
305 | @ | |
b059bdc3 | 306 | ldr r5, [sp, #S_PSR] @ Get SVC cpsr |
df295df6 RK |
307 | #ifdef CONFIG_TRACE_IRQFLAGS |
308 | tst r5, #PSR_I_BIT | |
309 | bleq trace_hardirqs_on | |
310 | tst r5, #PSR_I_BIT | |
311 | blne trace_hardirqs_off | |
312 | #endif | |
b059bdc3 | 313 | svc_exit r5 @ return from exception |
c4c5716e | 314 | UNWIND(.fnend ) |
93ed3970 | 315 | ENDPROC(__und_svc) |
1da177e4 LT |
316 | |
317 | .align 5 | |
318 | __pabt_svc: | |
ccea7a19 | 319 | svc_entry |
1da177e4 | 320 | |
02fe2845 RK |
321 | #ifdef CONFIG_TRACE_IRQFLAGS |
322 | bl trace_hardirqs_off | |
323 | #endif | |
1da177e4 | 324 | |
ac8b9c1c | 325 | pabt_helper |
4fb28474 | 326 | mov r2, sp @ regs |
1da177e4 LT |
327 | bl do_PrefetchAbort @ call abort handler |
328 | ||
329 | @ | |
330 | @ IRQs off again before pulling preserved data off the stack | |
331 | @ | |
ac78884e | 332 | disable_irq_notrace |
1da177e4 LT |
333 | |
334 | @ | |
335 | @ restore SPSR and restart the instruction | |
336 | @ | |
b059bdc3 | 337 | ldr r5, [sp, #S_PSR] |
02fe2845 RK |
338 | #ifdef CONFIG_TRACE_IRQFLAGS |
339 | tst r5, #PSR_I_BIT | |
340 | bleq trace_hardirqs_on | |
341 | tst r5, #PSR_I_BIT | |
342 | blne trace_hardirqs_off | |
343 | #endif | |
b059bdc3 | 344 | svc_exit r5 @ return from exception |
c4c5716e | 345 | UNWIND(.fnend ) |
93ed3970 | 346 | ENDPROC(__pabt_svc) |
1da177e4 LT |
347 | |
348 | .align 5 | |
49f680ea RK |
349 | .LCcralign: |
350 | .word cr_alignment | |
48d7927b | 351 | #ifdef MULTI_DABORT |
1da177e4 LT |
352 | .LCprocfns: |
353 | .word processor | |
354 | #endif | |
355 | .LCfp: | |
356 | .word fp_enter | |
1da177e4 LT |
357 | |
358 | /* | |
359 | * User mode handlers | |
2dede2d8 NP |
360 | * |
361 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 362 | */ |
2dede2d8 NP |
363 | |
364 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
365 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
366 | #endif | |
367 | ||
ccea7a19 | 368 | .macro usr_entry |
c4c5716e CM |
369 | UNWIND(.fnstart ) |
370 | UNWIND(.cantunwind ) @ don't unwind the user space | |
ccea7a19 | 371 | sub sp, sp, #S_FRAME_SIZE |
b86040a5 CM |
372 | ARM( stmib sp, {r1 - r12} ) |
373 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 | 374 | |
b059bdc3 | 375 | ldmia r0, {r3 - r5} |
ccea7a19 | 376 | add r0, sp, #S_PC @ here for interlock avoidance |
b059bdc3 | 377 | mov r6, #-1 @ "" "" "" "" |
ccea7a19 | 378 | |
b059bdc3 | 379 | str r3, [sp] @ save the "real" r0 copied |
ccea7a19 | 380 | @ from the exception stack |
1da177e4 LT |
381 | |
382 | @ | |
383 | @ We are now ready to fill in the remaining blanks on the stack: | |
384 | @ | |
b059bdc3 RK |
385 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
386 | @ r5 - spsr_<exception> | |
387 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 LT |
388 | @ |
389 | @ Also, separately save sp_usr and lr_usr | |
390 | @ | |
b059bdc3 | 391 | stmia r0, {r4 - r6} |
b86040a5 CM |
392 | ARM( stmdb r0, {sp, lr}^ ) |
393 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 LT |
394 | |
395 | @ | |
396 | @ Enable the alignment trap while in kernel mode | |
397 | @ | |
49f680ea | 398 | alignment_trap r0 |
1da177e4 LT |
399 | |
400 | @ | |
401 | @ Clear FP to mark the first stack frame | |
402 | @ | |
403 | zero_fp | |
404 | .endm | |
405 | ||
b49c0f24 NP |
406 | .macro kuser_cmpxchg_check |
407 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
408 | #ifndef CONFIG_MMU | |
409 | #warning "NPTL on non MMU needs fixing" | |
410 | #else | |
411 | @ Make sure our user space atomic helper is restarted | |
412 | @ if it was interrupted in a critical region. Here we | |
413 | @ perform a quick test inline since it should be false | |
414 | @ 99.9999% of the time. The rest is done out of line. | |
b059bdc3 | 415 | cmp r4, #TASK_SIZE |
b49c0f24 NP |
416 | blhs kuser_cmpxchg_fixup |
417 | #endif | |
418 | #endif | |
419 | .endm | |
420 | ||
1da177e4 LT |
421 | .align 5 |
422 | __dabt_usr: | |
ccea7a19 | 423 | usr_entry |
b49c0f24 | 424 | kuser_cmpxchg_check |
ac8b9c1c | 425 | dabt_helper |
1da177e4 | 426 | |
1da177e4 | 427 | mov r2, sp |
b86040a5 | 428 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 429 | b do_DataAbort |
c4c5716e | 430 | UNWIND(.fnend ) |
93ed3970 | 431 | ENDPROC(__dabt_usr) |
1da177e4 LT |
432 | |
433 | .align 5 | |
434 | __irq_usr: | |
ccea7a19 | 435 | usr_entry |
b49c0f24 | 436 | kuser_cmpxchg_check |
1da177e4 | 437 | |
9fc2552a ML |
438 | #ifdef CONFIG_IRQSOFF_TRACER |
439 | bl trace_hardirqs_off | |
440 | #endif | |
441 | ||
187a51ad | 442 | irq_handler |
1613cc11 | 443 | get_thread_info tsk |
1da177e4 | 444 | mov why, #0 |
9fc2552a | 445 | b ret_to_user_from_irq |
c4c5716e | 446 | UNWIND(.fnend ) |
93ed3970 | 447 | ENDPROC(__irq_usr) |
1da177e4 LT |
448 | |
449 | .ltorg | |
450 | ||
451 | .align 5 | |
452 | __und_usr: | |
ccea7a19 | 453 | usr_entry |
b059bdc3 RK |
454 | mov r2, r4 |
455 | mov r3, r5 | |
1da177e4 | 456 | |
1da177e4 LT |
457 | @ |
458 | @ fall through to the emulation code, which returns using r9 if | |
459 | @ it has emulated the instruction, or the more conventional lr | |
460 | @ if we are to treat this as a real undefined instruction | |
461 | @ | |
462 | @ r0 - instruction | |
463 | @ | |
b86040a5 CM |
464 | adr r9, BSYM(ret_from_exception) |
465 | adr lr, BSYM(__und_usr_unknown) | |
cb170a45 | 466 | tst r3, #PSR_T_BIT @ Thumb mode? |
b86040a5 | 467 | itet eq @ explicit IT needed for the 1f label |
cb170a45 PB |
468 | subeq r4, r2, #4 @ ARM instr at LR - 4 |
469 | subne r4, r2, #2 @ Thumb instr at LR - 2 | |
470 | 1: ldreqt r0, [r4] | |
26584853 CM |
471 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
472 | reveq r0, r0 @ little endian instruction | |
473 | #endif | |
cb170a45 PB |
474 | beq call_fpe |
475 | @ Thumb instruction | |
476 | #if __LINUX_ARM_ARCH__ >= 7 | |
b86040a5 CM |
477 | 2: |
478 | ARM( ldrht r5, [r4], #2 ) | |
479 | THUMB( ldrht r5, [r4] ) | |
480 | THUMB( add r4, r4, #2 ) | |
cb170a45 PB |
481 | and r0, r5, #0xf800 @ mask bits 111x x... .... .... |
482 | cmp r0, #0xe800 @ 32bit instruction if xx != 0 | |
483 | blo __und_usr_unknown | |
484 | 3: ldrht r0, [r4] | |
485 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 | |
486 | orr r0, r0, r5, lsl #16 | |
487 | #else | |
488 | b __und_usr_unknown | |
489 | #endif | |
c4c5716e | 490 | UNWIND(.fnend ) |
93ed3970 | 491 | ENDPROC(__und_usr) |
cb170a45 | 492 | |
1da177e4 LT |
493 | @ |
494 | @ fallthrough to call_fpe | |
495 | @ | |
496 | ||
497 | /* | |
498 | * The out of line fixup for the ldrt above. | |
499 | */ | |
4260415f | 500 | .pushsection .fixup, "ax" |
cb170a45 | 501 | 4: mov pc, r9 |
4260415f RK |
502 | .popsection |
503 | .pushsection __ex_table,"a" | |
cb170a45 PB |
504 | .long 1b, 4b |
505 | #if __LINUX_ARM_ARCH__ >= 7 | |
506 | .long 2b, 4b | |
507 | .long 3b, 4b | |
508 | #endif | |
4260415f | 509 | .popsection |
1da177e4 LT |
510 | |
511 | /* | |
512 | * Check whether the instruction is a co-processor instruction. | |
513 | * If yes, we need to call the relevant co-processor handler. | |
514 | * | |
515 | * Note that we don't do a full check here for the co-processor | |
516 | * instructions; all instructions with bit 27 set are well | |
517 | * defined. The only instructions that should fault are the | |
518 | * co-processor instructions. However, we have to watch out | |
519 | * for the ARM6/ARM7 SWI bug. | |
520 | * | |
b5872db4 CM |
521 | * NEON is a special case that has to be handled here. Not all |
522 | * NEON instructions are co-processor instructions, so we have | |
523 | * to make a special case of checking for them. Plus, there's | |
524 | * five groups of them, so we have a table of mask/opcode pairs | |
525 | * to check against, and if any match then we branch off into the | |
526 | * NEON handler code. | |
527 | * | |
1da177e4 LT |
528 | * Emulators may wish to make use of the following registers: |
529 | * r0 = instruction opcode. | |
530 | * r2 = PC+4 | |
db6ccbb6 | 531 | * r9 = normal "successful" return address |
1da177e4 | 532 | * r10 = this threads thread_info structure. |
db6ccbb6 | 533 | * lr = unrecognised instruction return address |
1da177e4 | 534 | */ |
cb170a45 PB |
535 | @ |
536 | @ Fall-through from Thumb-2 __und_usr | |
537 | @ | |
538 | #ifdef CONFIG_NEON | |
539 | adr r6, .LCneon_thumb_opcodes | |
540 | b 2f | |
541 | #endif | |
1da177e4 | 542 | call_fpe: |
b5872db4 | 543 | #ifdef CONFIG_NEON |
cb170a45 | 544 | adr r6, .LCneon_arm_opcodes |
b5872db4 CM |
545 | 2: |
546 | ldr r7, [r6], #4 @ mask value | |
547 | cmp r7, #0 @ end mask? | |
548 | beq 1f | |
549 | and r8, r0, r7 | |
550 | ldr r7, [r6], #4 @ opcode bits matching in mask | |
551 | cmp r8, r7 @ NEON instruction? | |
552 | bne 2b | |
553 | get_thread_info r10 | |
554 | mov r7, #1 | |
555 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
556 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
557 | b do_vfp @ let VFP handler handle this | |
558 | 1: | |
559 | #endif | |
1da177e4 | 560 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 561 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
1da177e4 LT |
562 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) |
563 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
564 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
565 | #endif | |
566 | moveq pc, lr | |
567 | get_thread_info r10 @ get current thread | |
568 | and r8, r0, #0x00000f00 @ mask out CP number | |
b86040a5 | 569 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
570 | mov r7, #1 |
571 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
572 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
573 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
574 | #ifdef CONFIG_IWMMXT |
575 | @ Test if we need to give access to iWMMXt coprocessors | |
576 | ldr r5, [r10, #TI_FLAGS] | |
577 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
578 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
579 | bcs iwmmxt_task_enable | |
580 | #endif | |
b86040a5 CM |
581 | ARM( add pc, pc, r8, lsr #6 ) |
582 | THUMB( lsl r8, r8, #2 ) | |
583 | THUMB( add pc, r8 ) | |
584 | nop | |
585 | ||
a771fe6e | 586 | movw_pc lr @ CP#0 |
b86040a5 CM |
587 | W(b) do_fpe @ CP#1 (FPE) |
588 | W(b) do_fpe @ CP#2 (FPE) | |
a771fe6e | 589 | movw_pc lr @ CP#3 |
c17fad11 LB |
590 | #ifdef CONFIG_CRUNCH |
591 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
592 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
593 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
594 | #else | |
a771fe6e CM |
595 | movw_pc lr @ CP#4 |
596 | movw_pc lr @ CP#5 | |
597 | movw_pc lr @ CP#6 | |
c17fad11 | 598 | #endif |
a771fe6e CM |
599 | movw_pc lr @ CP#7 |
600 | movw_pc lr @ CP#8 | |
601 | movw_pc lr @ CP#9 | |
1da177e4 | 602 | #ifdef CONFIG_VFP |
b86040a5 CM |
603 | W(b) do_vfp @ CP#10 (VFP) |
604 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 605 | #else |
a771fe6e CM |
606 | movw_pc lr @ CP#10 (VFP) |
607 | movw_pc lr @ CP#11 (VFP) | |
1da177e4 | 608 | #endif |
a771fe6e CM |
609 | movw_pc lr @ CP#12 |
610 | movw_pc lr @ CP#13 | |
611 | movw_pc lr @ CP#14 (Debug) | |
612 | movw_pc lr @ CP#15 (Control) | |
1da177e4 | 613 | |
b5872db4 CM |
614 | #ifdef CONFIG_NEON |
615 | .align 6 | |
616 | ||
cb170a45 | 617 | .LCneon_arm_opcodes: |
b5872db4 CM |
618 | .word 0xfe000000 @ mask |
619 | .word 0xf2000000 @ opcode | |
620 | ||
621 | .word 0xff100000 @ mask | |
622 | .word 0xf4000000 @ opcode | |
623 | ||
cb170a45 PB |
624 | .word 0x00000000 @ mask |
625 | .word 0x00000000 @ opcode | |
626 | ||
627 | .LCneon_thumb_opcodes: | |
628 | .word 0xef000000 @ mask | |
629 | .word 0xef000000 @ opcode | |
630 | ||
631 | .word 0xff100000 @ mask | |
632 | .word 0xf9000000 @ opcode | |
633 | ||
b5872db4 CM |
634 | .word 0x00000000 @ mask |
635 | .word 0x00000000 @ opcode | |
636 | #endif | |
637 | ||
1da177e4 | 638 | do_fpe: |
5d25ac03 | 639 | enable_irq |
1da177e4 LT |
640 | ldr r4, .LCfp |
641 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
642 | ldr pc, [r4] @ Call FP module USR entry point | |
643 | ||
644 | /* | |
645 | * The FP module is called with these registers set: | |
646 | * r0 = instruction | |
647 | * r2 = PC+4 | |
648 | * r9 = normal "successful" return address | |
649 | * r10 = FP workspace | |
650 | * lr = unrecognised FP instruction return address | |
651 | */ | |
652 | ||
124efc27 | 653 | .pushsection .data |
1da177e4 | 654 | ENTRY(fp_enter) |
db6ccbb6 | 655 | .word no_fp |
124efc27 | 656 | .popsection |
1da177e4 | 657 | |
83e686ea CM |
658 | ENTRY(no_fp) |
659 | mov pc, lr | |
660 | ENDPROC(no_fp) | |
db6ccbb6 RK |
661 | |
662 | __und_usr_unknown: | |
ecbab71c | 663 | enable_irq |
1da177e4 | 664 | mov r0, sp |
b86040a5 | 665 | adr lr, BSYM(ret_from_exception) |
1da177e4 | 666 | b do_undefinstr |
93ed3970 | 667 | ENDPROC(__und_usr_unknown) |
1da177e4 LT |
668 | |
669 | .align 5 | |
670 | __pabt_usr: | |
ccea7a19 | 671 | usr_entry |
ac8b9c1c | 672 | pabt_helper |
4fb28474 | 673 | mov r2, sp @ regs |
1da177e4 | 674 | bl do_PrefetchAbort @ call abort handler |
c4c5716e | 675 | UNWIND(.fnend ) |
1da177e4 LT |
676 | /* fall through */ |
677 | /* | |
678 | * This is the return code to user mode for abort handlers | |
679 | */ | |
680 | ENTRY(ret_from_exception) | |
c4c5716e CM |
681 | UNWIND(.fnstart ) |
682 | UNWIND(.cantunwind ) | |
1da177e4 LT |
683 | get_thread_info tsk |
684 | mov why, #0 | |
685 | b ret_to_user | |
c4c5716e | 686 | UNWIND(.fnend ) |
93ed3970 CM |
687 | ENDPROC(__pabt_usr) |
688 | ENDPROC(ret_from_exception) | |
1da177e4 LT |
689 | |
690 | /* | |
691 | * Register switch for ARMv3 and ARMv4 processors | |
692 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
693 | * previous and next are guaranteed not to be the same. | |
694 | */ | |
695 | ENTRY(__switch_to) | |
c4c5716e CM |
696 | UNWIND(.fnstart ) |
697 | UNWIND(.cantunwind ) | |
1da177e4 LT |
698 | add ip, r1, #TI_CPU_SAVE |
699 | ldr r3, [r2, #TI_TP_VALUE] | |
b86040a5 CM |
700 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
701 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
702 | THUMB( str sp, [ip], #4 ) | |
703 | THUMB( str lr, [ip], #4 ) | |
247055aa | 704 | #ifdef CONFIG_CPU_USE_DOMAINS |
d6551e88 | 705 | ldr r6, [r2, #TI_CPU_DOMAIN] |
afeb90ca | 706 | #endif |
f159f4ed | 707 | set_tls r3, r4, r5 |
df0698be NP |
708 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
709 | ldr r7, [r2, #TI_TASK] | |
710 | ldr r8, =__stack_chk_guard | |
711 | ldr r7, [r7, #TSK_STACK_CANARY] | |
712 | #endif | |
247055aa | 713 | #ifdef CONFIG_CPU_USE_DOMAINS |
1da177e4 | 714 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 715 | #endif |
d6551e88 RK |
716 | mov r5, r0 |
717 | add r4, r2, #TI_CPU_SAVE | |
718 | ldr r0, =thread_notify_head | |
719 | mov r1, #THREAD_NOTIFY_SWITCH | |
720 | bl atomic_notifier_call_chain | |
df0698be NP |
721 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
722 | str r7, [r8] | |
723 | #endif | |
b86040a5 | 724 | THUMB( mov ip, r4 ) |
d6551e88 | 725 | mov r0, r5 |
b86040a5 CM |
726 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
727 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
728 | THUMB( ldr sp, [ip], #4 ) | |
729 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 730 | UNWIND(.fnend ) |
93ed3970 | 731 | ENDPROC(__switch_to) |
1da177e4 LT |
732 | |
733 | __INIT | |
2d2669b6 NP |
734 | |
735 | /* | |
736 | * User helpers. | |
737 | * | |
738 | * These are segment of kernel provided user code reachable from user space | |
739 | * at a fixed address in kernel memory. This is used to provide user space | |
740 | * with some operations which require kernel help because of unimplemented | |
741 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
742 | * this code to be executed directly in user mode for best efficiency but | |
743 | * which is too intimate with the kernel counter part to be left to user | |
744 | * libraries. In fact this code might even differ from one CPU to another | |
745 | * depending on the available instruction set and restrictions like on | |
746 | * SMP systems. In other words, the kernel reserves the right to change | |
747 | * this code as needed without warning. Only the entry points and their | |
748 | * results are guaranteed to be stable. | |
749 | * | |
750 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
751 | * vector page. New segments (if ever needed) must be added in front of | |
752 | * existing ones. This mechanism should be used only for things that are | |
753 | * really small and justified, and not be abused freely. | |
754 | * | |
755 | * User space is expected to implement those things inline when optimizing | |
756 | * for a processor that has the necessary native support, but only if such | |
757 | * resulting binaries are already to be incompatible with earlier ARM | |
758 | * processors due to the use of unsupported instructions other than what | |
759 | * is provided here. In other words don't make binaries unable to run on | |
760 | * earlier processors just for the sake of not using these kernel helpers | |
761 | * if your compiled code is not going to use the new instructions for other | |
762 | * purpose. | |
763 | */ | |
b86040a5 | 764 | THUMB( .arm ) |
2d2669b6 | 765 | |
ba9b5d76 NP |
766 | .macro usr_ret, reg |
767 | #ifdef CONFIG_ARM_THUMB | |
768 | bx \reg | |
769 | #else | |
770 | mov pc, \reg | |
771 | #endif | |
772 | .endm | |
773 | ||
2d2669b6 NP |
774 | .align 5 |
775 | .globl __kuser_helper_start | |
776 | __kuser_helper_start: | |
777 | ||
7c612bfd NP |
778 | /* |
779 | * Reference prototype: | |
780 | * | |
781 | * void __kernel_memory_barrier(void) | |
782 | * | |
783 | * Input: | |
784 | * | |
785 | * lr = return address | |
786 | * | |
787 | * Output: | |
788 | * | |
789 | * none | |
790 | * | |
791 | * Clobbered: | |
792 | * | |
b49c0f24 | 793 | * none |
7c612bfd NP |
794 | * |
795 | * Definition and user space usage example: | |
796 | * | |
797 | * typedef void (__kernel_dmb_t)(void); | |
798 | * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) | |
799 | * | |
800 | * Apply any needed memory barrier to preserve consistency with data modified | |
801 | * manually and __kuser_cmpxchg usage. | |
802 | * | |
803 | * This could be used as follows: | |
804 | * | |
805 | * #define __kernel_dmb() \ | |
806 | * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ | |
6896eec0 | 807 | * : : : "r0", "lr","cc" ) |
7c612bfd NP |
808 | */ |
809 | ||
810 | __kuser_memory_barrier: @ 0xffff0fa0 | |
ed3768a8 | 811 | smp_dmb arm |
ba9b5d76 | 812 | usr_ret lr |
7c612bfd NP |
813 | |
814 | .align 5 | |
815 | ||
2d2669b6 NP |
816 | /* |
817 | * Reference prototype: | |
818 | * | |
819 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
820 | * | |
821 | * Input: | |
822 | * | |
823 | * r0 = oldval | |
824 | * r1 = newval | |
825 | * r2 = ptr | |
826 | * lr = return address | |
827 | * | |
828 | * Output: | |
829 | * | |
830 | * r0 = returned value (zero or non-zero) | |
831 | * C flag = set if r0 == 0, clear if r0 != 0 | |
832 | * | |
833 | * Clobbered: | |
834 | * | |
835 | * r3, ip, flags | |
836 | * | |
837 | * Definition and user space usage example: | |
838 | * | |
839 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
840 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
841 | * | |
842 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
843 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
844 | * The C flag is also set if *ptr was changed to allow for assembly | |
845 | * optimization in the calling code. | |
846 | * | |
5964eae8 NP |
847 | * Notes: |
848 | * | |
849 | * - This routine already includes memory barriers as needed. | |
850 | * | |
2d2669b6 NP |
851 | * For example, a user space atomic_add implementation could look like this: |
852 | * | |
853 | * #define atomic_add(ptr, val) \ | |
854 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
855 | * register unsigned int __result asm("r1"); \ | |
856 | * asm volatile ( \ | |
857 | * "1: @ atomic_add\n\t" \ | |
858 | * "ldr r0, [r2]\n\t" \ | |
859 | * "mov r3, #0xffff0fff\n\t" \ | |
860 | * "add lr, pc, #4\n\t" \ | |
861 | * "add r1, r0, %2\n\t" \ | |
862 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
863 | * "bcc 1b" \ | |
864 | * : "=&r" (__result) \ | |
865 | * : "r" (__ptr), "rIL" (val) \ | |
866 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
867 | * __result; }) | |
868 | */ | |
869 | ||
870 | __kuser_cmpxchg: @ 0xffff0fc0 | |
871 | ||
dcef1f63 | 872 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 873 | |
dcef1f63 NP |
874 | /* |
875 | * Poor you. No fast solution possible... | |
876 | * The kernel itself must perform the operation. | |
877 | * A special ghost syscall is used for that (see traps.c). | |
878 | */ | |
5e097445 | 879 | stmfd sp!, {r7, lr} |
55afd264 | 880 | ldr r7, 1f @ it's 20 bits |
cc20d429 | 881 | swi __ARM_NR_cmpxchg |
5e097445 | 882 | ldmfd sp!, {r7, pc} |
cc20d429 | 883 | 1: .word __ARM_NR_cmpxchg |
dcef1f63 NP |
884 | |
885 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 886 | |
b49c0f24 NP |
887 | #ifdef CONFIG_MMU |
888 | ||
2d2669b6 | 889 | /* |
b49c0f24 NP |
890 | * The only thing that can break atomicity in this cmpxchg |
891 | * implementation is either an IRQ or a data abort exception | |
892 | * causing another process/thread to be scheduled in the middle | |
893 | * of the critical sequence. To prevent this, code is added to | |
894 | * the IRQ and data abort exception handlers to set the pc back | |
895 | * to the beginning of the critical section if it is found to be | |
896 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 897 | */ |
b49c0f24 NP |
898 | 1: ldr r3, [r2] @ load current val |
899 | subs r3, r3, r0 @ compare with oldval | |
900 | 2: streq r1, [r2] @ store newval if eq | |
901 | rsbs r0, r3, #0 @ set return val and C flag | |
902 | usr_ret lr | |
903 | ||
904 | .text | |
905 | kuser_cmpxchg_fixup: | |
906 | @ Called from kuser_cmpxchg_check macro. | |
b059bdc3 | 907 | @ r4 = address of interrupted insn (must be preserved). |
b49c0f24 NP |
908 | @ sp = saved regs. r7 and r8 are clobbered. |
909 | @ 1b = first critical insn, 2b = last critical insn. | |
b059bdc3 | 910 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
b49c0f24 NP |
911 | mov r7, #0xffff0fff |
912 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
b059bdc3 | 913 | subs r8, r4, r7 |
b49c0f24 NP |
914 | rsbcss r8, r8, #(2b - 1b) |
915 | strcs r7, [sp, #S_PC] | |
916 | mov pc, lr | |
917 | .previous | |
918 | ||
49bca4c2 NP |
919 | #else |
920 | #warning "NPTL on non MMU needs fixing" | |
921 | mov r0, #-1 | |
922 | adds r0, r0, #0 | |
ba9b5d76 | 923 | usr_ret lr |
b49c0f24 | 924 | #endif |
2d2669b6 NP |
925 | |
926 | #else | |
927 | ||
ed3768a8 | 928 | smp_dmb arm |
b49c0f24 | 929 | 1: ldrex r3, [r2] |
2d2669b6 NP |
930 | subs r3, r3, r0 |
931 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
932 | teqeq r3, #1 |
933 | beq 1b | |
2d2669b6 | 934 | rsbs r0, r3, #0 |
b49c0f24 | 935 | /* beware -- each __kuser slot must be 8 instructions max */ |
f00ec48f RK |
936 | ALT_SMP(b __kuser_memory_barrier) |
937 | ALT_UP(usr_ret lr) | |
2d2669b6 NP |
938 | |
939 | #endif | |
940 | ||
941 | .align 5 | |
942 | ||
943 | /* | |
944 | * Reference prototype: | |
945 | * | |
946 | * int __kernel_get_tls(void) | |
947 | * | |
948 | * Input: | |
949 | * | |
950 | * lr = return address | |
951 | * | |
952 | * Output: | |
953 | * | |
954 | * r0 = TLS value | |
955 | * | |
956 | * Clobbered: | |
957 | * | |
b49c0f24 | 958 | * none |
2d2669b6 NP |
959 | * |
960 | * Definition and user space usage example: | |
961 | * | |
962 | * typedef int (__kernel_get_tls_t)(void); | |
963 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
964 | * | |
965 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
966 | * | |
967 | * This could be used as follows: | |
968 | * | |
969 | * #define __kernel_get_tls() \ | |
970 | * ({ register unsigned int __val asm("r0"); \ | |
971 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
972 | * : "=r" (__val) : : "lr","cc" ); \ | |
973 | * __val; }) | |
974 | */ | |
975 | ||
976 | __kuser_get_tls: @ 0xffff0fe0 | |
f159f4ed | 977 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
ba9b5d76 | 978 | usr_ret lr |
f159f4ed TL |
979 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
980 | .rep 4 | |
981 | .word 0 @ 0xffff0ff0 software TLS value, then | |
982 | .endr @ pad up to __kuser_helper_version | |
2d2669b6 NP |
983 | |
984 | /* | |
985 | * Reference declaration: | |
986 | * | |
987 | * extern unsigned int __kernel_helper_version; | |
988 | * | |
989 | * Definition and user space usage example: | |
990 | * | |
991 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
992 | * | |
993 | * User space may read this to determine the curent number of helpers | |
994 | * available. | |
995 | */ | |
996 | ||
997 | __kuser_helper_version: @ 0xffff0ffc | |
998 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
999 | ||
1000 | .globl __kuser_helper_end | |
1001 | __kuser_helper_end: | |
1002 | ||
b86040a5 | 1003 | THUMB( .thumb ) |
2d2669b6 | 1004 | |
1da177e4 LT |
1005 | /* |
1006 | * Vector stubs. | |
1007 | * | |
7933523d RK |
1008 | * This code is copied to 0xffff0200 so we can use branches in the |
1009 | * vectors, rather than ldr's. Note that this code must not | |
1010 | * exceed 0x300 bytes. | |
1da177e4 LT |
1011 | * |
1012 | * Common stub entry macro: | |
1013 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
1014 | * |
1015 | * SP points to a minimal amount of processor-private memory, the address | |
1016 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 1017 | */ |
b7ec4795 | 1018 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
1019 | .align 5 |
1020 | ||
1021 | vector_\name: | |
1da177e4 LT |
1022 | .if \correction |
1023 | sub lr, lr, #\correction | |
1024 | .endif | |
ccea7a19 RK |
1025 | |
1026 | @ | |
1027 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
1028 | @ (parent CPSR) | |
1029 | @ | |
1030 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 1031 | mrs lr, spsr |
ccea7a19 RK |
1032 | str lr, [sp, #8] @ save spsr |
1033 | ||
1da177e4 | 1034 | @ |
ccea7a19 | 1035 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 1036 | @ |
ccea7a19 | 1037 | mrs r0, cpsr |
b86040a5 | 1038 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 1039 | msr spsr_cxsf, r0 |
1da177e4 | 1040 | |
ccea7a19 RK |
1041 | @ |
1042 | @ the branch table must immediately follow this code | |
1043 | @ | |
ccea7a19 | 1044 | and lr, lr, #0x0f |
b86040a5 CM |
1045 | THUMB( adr r0, 1f ) |
1046 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 1047 | mov r0, sp |
b86040a5 | 1048 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 1049 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 1050 | ENDPROC(vector_\name) |
88987ef9 CM |
1051 | |
1052 | .align 2 | |
1053 | @ handler addresses follow this label | |
1054 | 1: | |
1da177e4 LT |
1055 | .endm |
1056 | ||
7933523d | 1057 | .globl __stubs_start |
1da177e4 LT |
1058 | __stubs_start: |
1059 | /* | |
1060 | * Interrupt dispatcher | |
1061 | */ | |
b7ec4795 | 1062 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1063 | |
1064 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1065 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1066 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1067 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1068 | .long __irq_invalid @ 4 | |
1069 | .long __irq_invalid @ 5 | |
1070 | .long __irq_invalid @ 6 | |
1071 | .long __irq_invalid @ 7 | |
1072 | .long __irq_invalid @ 8 | |
1073 | .long __irq_invalid @ 9 | |
1074 | .long __irq_invalid @ a | |
1075 | .long __irq_invalid @ b | |
1076 | .long __irq_invalid @ c | |
1077 | .long __irq_invalid @ d | |
1078 | .long __irq_invalid @ e | |
1079 | .long __irq_invalid @ f | |
1080 | ||
1081 | /* | |
1082 | * Data abort dispatcher | |
1083 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1084 | */ | |
b7ec4795 | 1085 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1086 | |
1087 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1088 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1089 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1090 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1091 | .long __dabt_invalid @ 4 | |
1092 | .long __dabt_invalid @ 5 | |
1093 | .long __dabt_invalid @ 6 | |
1094 | .long __dabt_invalid @ 7 | |
1095 | .long __dabt_invalid @ 8 | |
1096 | .long __dabt_invalid @ 9 | |
1097 | .long __dabt_invalid @ a | |
1098 | .long __dabt_invalid @ b | |
1099 | .long __dabt_invalid @ c | |
1100 | .long __dabt_invalid @ d | |
1101 | .long __dabt_invalid @ e | |
1102 | .long __dabt_invalid @ f | |
1103 | ||
1104 | /* | |
1105 | * Prefetch abort dispatcher | |
1106 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1107 | */ | |
b7ec4795 | 1108 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1109 | |
1110 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1111 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1112 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1113 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1114 | .long __pabt_invalid @ 4 | |
1115 | .long __pabt_invalid @ 5 | |
1116 | .long __pabt_invalid @ 6 | |
1117 | .long __pabt_invalid @ 7 | |
1118 | .long __pabt_invalid @ 8 | |
1119 | .long __pabt_invalid @ 9 | |
1120 | .long __pabt_invalid @ a | |
1121 | .long __pabt_invalid @ b | |
1122 | .long __pabt_invalid @ c | |
1123 | .long __pabt_invalid @ d | |
1124 | .long __pabt_invalid @ e | |
1125 | .long __pabt_invalid @ f | |
1126 | ||
1127 | /* | |
1128 | * Undef instr entry dispatcher | |
1129 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1130 | */ | |
b7ec4795 | 1131 | vector_stub und, UND_MODE |
1da177e4 LT |
1132 | |
1133 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1134 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1135 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1136 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1137 | .long __und_invalid @ 4 | |
1138 | .long __und_invalid @ 5 | |
1139 | .long __und_invalid @ 6 | |
1140 | .long __und_invalid @ 7 | |
1141 | .long __und_invalid @ 8 | |
1142 | .long __und_invalid @ 9 | |
1143 | .long __und_invalid @ a | |
1144 | .long __und_invalid @ b | |
1145 | .long __und_invalid @ c | |
1146 | .long __und_invalid @ d | |
1147 | .long __und_invalid @ e | |
1148 | .long __und_invalid @ f | |
1149 | ||
1150 | .align 5 | |
1151 | ||
1152 | /*============================================================================= | |
1153 | * Undefined FIQs | |
1154 | *----------------------------------------------------------------------------- | |
1155 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1156 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1157 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1158 | * damage alert! I don't think that we can execute any code in here in any | |
1159 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1160 | * get out of that mode without clobbering one register. | |
1161 | */ | |
1162 | vector_fiq: | |
1163 | disable_fiq | |
1164 | subs pc, lr, #4 | |
1165 | ||
1166 | /*============================================================================= | |
1167 | * Address exception handler | |
1168 | *----------------------------------------------------------------------------- | |
1169 | * These aren't too critical. | |
1170 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1171 | */ | |
1172 | ||
1173 | vector_addrexcptn: | |
1174 | b vector_addrexcptn | |
1175 | ||
1176 | /* | |
1177 | * We group all the following data together to optimise | |
1178 | * for CPUs with separate I & D caches. | |
1179 | */ | |
1180 | .align 5 | |
1181 | ||
1182 | .LCvswi: | |
1183 | .word vector_swi | |
1184 | ||
7933523d | 1185 | .globl __stubs_end |
1da177e4 LT |
1186 | __stubs_end: |
1187 | ||
7933523d | 1188 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1189 | |
7933523d RK |
1190 | .globl __vectors_start |
1191 | __vectors_start: | |
b86040a5 CM |
1192 | ARM( swi SYS_ERROR0 ) |
1193 | THUMB( svc #0 ) | |
1194 | THUMB( nop ) | |
1195 | W(b) vector_und + stubs_offset | |
1196 | W(ldr) pc, .LCvswi + stubs_offset | |
1197 | W(b) vector_pabt + stubs_offset | |
1198 | W(b) vector_dabt + stubs_offset | |
1199 | W(b) vector_addrexcptn + stubs_offset | |
1200 | W(b) vector_irq + stubs_offset | |
1201 | W(b) vector_fiq + stubs_offset | |
7933523d RK |
1202 | |
1203 | .globl __vectors_end | |
1204 | __vectors_end: | |
1da177e4 LT |
1205 | |
1206 | .data | |
1207 | ||
1da177e4 LT |
1208 | .globl cr_alignment |
1209 | .globl cr_no_alignment | |
1210 | cr_alignment: | |
1211 | .space 4 | |
1212 | cr_no_alignment: | |
1213 | .space 4 | |
52108641 | 1214 | |
1215 | #ifdef CONFIG_MULTI_IRQ_HANDLER | |
1216 | .globl handle_arch_irq | |
1217 | handle_arch_irq: | |
1218 | .space 4 | |
1219 | #endif |