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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/fiq.c | |
3 | * | |
4 | * Copyright (C) 1998 Russell King | |
5 | * Copyright (C) 1998, 1999 Phil Blundell | |
6 | * | |
7 | * FIQ support written by Philip Blundell <philb@gnu.org>, 1998. | |
8 | * | |
9 | * FIQ support re-written by Russell King to be more generic | |
10 | * | |
11 | * We now properly support a method by which the FIQ handlers can | |
12 | * be stacked onto the vector. We still do not support sharing | |
13 | * the FIQ vector itself. | |
14 | * | |
15 | * Operation is as follows: | |
16 | * 1. Owner A claims FIQ: | |
17 | * - default_fiq relinquishes control. | |
18 | * 2. Owner A: | |
19 | * - inserts code. | |
20 | * - sets any registers, | |
21 | * - enables FIQ. | |
22 | * 3. Owner B claims FIQ: | |
23 | * - if owner A has a relinquish function. | |
24 | * - disable FIQs. | |
25 | * - saves any registers. | |
26 | * - returns zero. | |
27 | * 4. Owner B: | |
28 | * - inserts code. | |
29 | * - sets any registers, | |
30 | * - enables FIQ. | |
31 | * 5. Owner B releases FIQ: | |
32 | * - Owner A is asked to reacquire FIQ: | |
33 | * - inserts code. | |
34 | * - restores saved registers. | |
35 | * - enables FIQ. | |
36 | * 6. Goto 3 | |
37 | */ | |
38 | #include <linux/module.h> | |
39 | #include <linux/kernel.h> | |
40 | #include <linux/init.h> | |
4a2581a0 | 41 | #include <linux/interrupt.h> |
1da177e4 LT |
42 | #include <linux/seq_file.h> |
43 | ||
44 | #include <asm/cacheflush.h> | |
45 | #include <asm/fiq.h> | |
46 | #include <asm/irq.h> | |
47 | #include <asm/system.h> | |
48 | #include <asm/uaccess.h> | |
49 | ||
50 | static unsigned long no_fiq_insn; | |
51 | ||
52 | /* Default reacquire function | |
53 | * - we always relinquish FIQ control | |
54 | * - we always reacquire FIQ control | |
55 | */ | |
56 | static int fiq_def_op(void *ref, int relinquish) | |
57 | { | |
58 | if (!relinquish) | |
59 | set_fiq_handler(&no_fiq_insn, sizeof(no_fiq_insn)); | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
64 | static struct fiq_handler default_owner = { | |
65 | .name = "default", | |
66 | .fiq_op = fiq_def_op, | |
67 | }; | |
68 | ||
69 | static struct fiq_handler *current_fiq = &default_owner; | |
70 | ||
71 | int show_fiq_list(struct seq_file *p, void *v) | |
72 | { | |
73 | if (current_fiq != &default_owner) | |
74 | seq_printf(p, "FIQ: %s\n", current_fiq->name); | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
79 | void set_fiq_handler(void *start, unsigned int length) | |
80 | { | |
81 | memcpy((void *)0xffff001c, start, length); | |
82 | flush_icache_range(0xffff001c, 0xffff001c + length); | |
83 | if (!vectors_high()) | |
84 | flush_icache_range(0x1c, 0x1c + length); | |
85 | } | |
86 | ||
87 | /* | |
88 | * Taking an interrupt in FIQ mode is death, so both these functions | |
89 | * disable irqs for the duration. Note - these functions are almost | |
90 | * entirely coded in assembly. | |
91 | */ | |
92 | void __attribute__((naked)) set_fiq_regs(struct pt_regs *regs) | |
93 | { | |
94 | register unsigned long tmp; | |
95 | asm volatile ( | |
96 | "mov ip, sp\n\ | |
97 | stmfd sp!, {fp, ip, lr, pc}\n\ | |
98 | sub fp, ip, #4\n\ | |
99 | mrs %0, cpsr\n\ | |
100 | msr cpsr_c, %2 @ select FIQ mode\n\ | |
101 | mov r0, r0\n\ | |
102 | ldmia %1, {r8 - r14}\n\ | |
103 | msr cpsr_c, %0 @ return to SVC mode\n\ | |
104 | mov r0, r0\n\ | |
90303b10 | 105 | ldmfd sp, {fp, sp, pc}" |
1da177e4 LT |
106 | : "=&r" (tmp) |
107 | : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE)); | |
108 | } | |
109 | ||
110 | void __attribute__((naked)) get_fiq_regs(struct pt_regs *regs) | |
111 | { | |
112 | register unsigned long tmp; | |
113 | asm volatile ( | |
114 | "mov ip, sp\n\ | |
115 | stmfd sp!, {fp, ip, lr, pc}\n\ | |
116 | sub fp, ip, #4\n\ | |
117 | mrs %0, cpsr\n\ | |
118 | msr cpsr_c, %2 @ select FIQ mode\n\ | |
119 | mov r0, r0\n\ | |
120 | stmia %1, {r8 - r14}\n\ | |
121 | msr cpsr_c, %0 @ return to SVC mode\n\ | |
122 | mov r0, r0\n\ | |
90303b10 | 123 | ldmfd sp, {fp, sp, pc}" |
1da177e4 LT |
124 | : "=&r" (tmp) |
125 | : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE)); | |
126 | } | |
127 | ||
128 | int claim_fiq(struct fiq_handler *f) | |
129 | { | |
130 | int ret = 0; | |
131 | ||
132 | if (current_fiq) { | |
133 | ret = -EBUSY; | |
134 | ||
135 | if (current_fiq->fiq_op != NULL) | |
136 | ret = current_fiq->fiq_op(current_fiq->dev_id, 1); | |
137 | } | |
138 | ||
139 | if (!ret) { | |
140 | f->next = current_fiq; | |
141 | current_fiq = f; | |
142 | } | |
143 | ||
144 | return ret; | |
145 | } | |
146 | ||
147 | void release_fiq(struct fiq_handler *f) | |
148 | { | |
149 | if (current_fiq != f) { | |
150 | printk(KERN_ERR "%s FIQ trying to release %s FIQ\n", | |
151 | f->name, current_fiq->name); | |
152 | dump_stack(); | |
153 | return; | |
154 | } | |
155 | ||
156 | do | |
157 | current_fiq = current_fiq->next; | |
158 | while (current_fiq->fiq_op(current_fiq->dev_id, 0)); | |
159 | } | |
160 | ||
161 | void enable_fiq(int fiq) | |
162 | { | |
163 | enable_irq(fiq + FIQ_START); | |
164 | } | |
165 | ||
166 | void disable_fiq(int fiq) | |
167 | { | |
168 | disable_irq(fiq + FIQ_START); | |
169 | } | |
170 | ||
171 | EXPORT_SYMBOL(set_fiq_handler); | |
172 | EXPORT_SYMBOL(set_fiq_regs); | |
173 | EXPORT_SYMBOL(get_fiq_regs); | |
174 | EXPORT_SYMBOL(claim_fiq); | |
175 | EXPORT_SYMBOL(release_fiq); | |
176 | EXPORT_SYMBOL(enable_fiq); | |
177 | EXPORT_SYMBOL(disable_fiq); | |
178 | ||
179 | void __init init_FIQ(void) | |
180 | { | |
181 | no_fiq_insn = *(unsigned long *)0xffff001c; | |
182 | } |