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75d90832 HC |
1 | /* |
2 | * linux/arch/arm/kernel/head-nommu.S | |
3 | * | |
4 | * Copyright (C) 1994-2002 Russell King | |
5 | * Copyright (C) 2003-2006 Hyok S. Choi | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Common kernel startup code (non-paged MM) | |
75d90832 HC |
12 | * |
13 | */ | |
75d90832 HC |
14 | #include <linux/linkage.h> |
15 | #include <linux/init.h> | |
16 | ||
17 | #include <asm/assembler.h> | |
75d90832 | 18 | #include <asm/ptrace.h> |
2eb9d315 | 19 | #include <asm/asm-offsets.h> |
67c9845b | 20 | #include <asm/memory.h> |
15d07dc9 | 21 | #include <asm/cp15.h> |
3b920cef | 22 | #include <asm/thread_info.h> |
55bdd694 | 23 | #include <asm/v7m.h> |
67c9845b | 24 | #include <asm/mpu.h> |
9dfc28b6 | 25 | #include <asm/page.h> |
75d90832 | 26 | |
75d90832 HC |
27 | /* |
28 | * Kernel startup entry point. | |
29 | * --------------------------- | |
30 | * | |
31 | * This is normally called from the decompressor code. The requirements | |
32 | * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, | |
33 | * r1 = machine nr. | |
34 | * | |
35 | * See linux/arch/arm/tools/mach-types for the complete list of machine | |
36 | * numbers for r1. | |
37 | * | |
38 | */ | |
540b5738 | 39 | |
2abc1c50 | 40 | __HEAD |
bc7dea00 UKK |
41 | |
42 | #ifdef CONFIG_CPU_THUMBONLY | |
43 | .thumb | |
44 | ENTRY(stext) | |
45 | #else | |
46 | .arm | |
75d90832 | 47 | ENTRY(stext) |
540b5738 | 48 | |
14327c66 | 49 | THUMB( badr r9, 1f ) @ Kernel is always entered in ARM. |
540b5738 DM |
50 | THUMB( bx r9 ) @ If this is a Thumb-2 kernel, |
51 | THUMB( .thumb ) @ switch to Thumb now. | |
52 | THUMB(1: ) | |
bc7dea00 | 53 | #endif |
540b5738 | 54 | |
b86040a5 | 55 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode |
75d90832 | 56 | @ and irqs disabled |
55bdd694 | 57 | #if defined(CONFIG_CPU_CP15) |
75d90832 | 58 | mrc p15, 0, r9, c0, c0 @ get processor id |
55bdd694 CM |
59 | #elif defined(CONFIG_CPU_V7M) |
60 | ldr r9, =BASEADDR_V7M_SCB | |
61 | ldr r9, [r9, V7M_SCB_CPUID] | |
62 | #else | |
63 | ldr r9, =CONFIG_PROCESSOR_ID | |
f12d0d7c | 64 | #endif |
75d90832 HC |
65 | bl __lookup_processor_type @ r5=procinfo r9=cpuid |
66 | movs r10, r5 @ invalid processor (r5=0)? | |
67 | beq __error_p @ yes, error 'p' | |
75d90832 | 68 | |
67c9845b JA |
69 | #ifdef CONFIG_ARM_MPU |
70 | /* Calculate the size of a region covering just the kernel */ | |
b713aa0b | 71 | ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET |
67c9845b JA |
72 | ldr r6, =(_end) @ Cover whole kernel |
73 | sub r6, r6, r5 @ Minimum size of region to map | |
74 | clz r6, r6 @ Region size must be 2^N... | |
75 | rsb r6, r6, #31 @ ...so round up region size | |
76 | lsl r6, r6, #MPU_RSR_SZ @ Put size in right field | |
77 | orr r6, r6, #(1 << MPU_RSR_EN) @ Set region enabled bit | |
78 | bl __setup_mpu | |
79 | #endif | |
970d96f9 | 80 | |
14327c66 | 81 | badr lr, 1f @ return (PIC) address |
0a9024e8 RK |
82 | ldr r12, [r10, #PROCINFO_INITFUNC] |
83 | add r12, r12, r10 | |
84 | ret r12 | |
970d96f9 SA |
85 | 1: bl __after_proc_init |
86 | b __mmap_switched | |
93ed3970 | 87 | ENDPROC(stext) |
75d90832 | 88 | |
01fafcab | 89 | #ifdef CONFIG_SMP |
2449189b | 90 | .text |
01fafcab WD |
91 | ENTRY(secondary_startup) |
92 | /* | |
93 | * Common entry point for secondary CPUs. | |
94 | * | |
95 | * Ensure that we're in SVC mode, and IRQs are disabled. Lookup | |
96 | * the processor type - there is no need to check the machine type | |
97 | * as it has already been validated by the primary processor. | |
98 | */ | |
99 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 | |
100 | #ifndef CONFIG_CPU_CP15 | |
101 | ldr r9, =CONFIG_PROCESSOR_ID | |
102 | #else | |
103 | mrc p15, 0, r9, c0, c0 @ get processor id | |
104 | #endif | |
105 | bl __lookup_processor_type @ r5=procinfo r9=cpuid | |
106 | movs r10, r5 @ invalid processor? | |
107 | beq __error_p @ yes, error 'p' | |
108 | ||
970d96f9 | 109 | ldr r7, __secondary_data |
eb08375e JA |
110 | |
111 | #ifdef CONFIG_ARM_MPU | |
112 | /* Use MPU region info supplied by __cpu_up */ | |
113 | ldr r6, [r7] @ get secondary_data.mpu_szr | |
114 | bl __setup_mpu @ Initialize the MPU | |
115 | #endif | |
116 | ||
970d96f9 | 117 | badr lr, 1f @ return (PIC) address |
0a9024e8 RK |
118 | ldr r12, [r10, #PROCINFO_INITFUNC] |
119 | add r12, r12, r10 | |
120 | ret r12 | |
970d96f9 | 121 | 1: bl __after_proc_init |
b2c3e38a | 122 | ldr sp, [r7, #12] @ set up the stack pointer |
01fafcab WD |
123 | mov fp, #0 |
124 | b secondary_start_kernel | |
970d96f9 | 125 | ENDPROC(secondary_startup) |
01fafcab WD |
126 | |
127 | .type __secondary_data, %object | |
128 | __secondary_data: | |
129 | .long secondary_data | |
01fafcab WD |
130 | #endif /* CONFIG_SMP */ |
131 | ||
75d90832 HC |
132 | /* |
133 | * Set the Control Register and Read the process ID. | |
134 | */ | |
75d90832 | 135 | __after_proc_init: |
f12d0d7c | 136 | #ifdef CONFIG_CPU_CP15 |
05efde9d CM |
137 | /* |
138 | * CP15 system control register value returned in r0 from | |
139 | * the CPU init function. | |
140 | */ | |
76e09204 | 141 | #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 |
75d90832 HC |
142 | orr r0, r0, #CR_A |
143 | #else | |
144 | bic r0, r0, #CR_A | |
145 | #endif | |
146 | #ifdef CONFIG_CPU_DCACHE_DISABLE | |
147 | bic r0, r0, #CR_C | |
148 | #endif | |
149 | #ifdef CONFIG_CPU_BPREDICT_DISABLE | |
150 | bic r0, r0, #CR_Z | |
151 | #endif | |
152 | #ifdef CONFIG_CPU_ICACHE_DISABLE | |
153 | bic r0, r0, #CR_I | |
6afd6fae HC |
154 | #endif |
155 | #ifdef CONFIG_CPU_HIGH_VECTOR | |
156 | orr r0, r0, #CR_V | |
157 | #else | |
158 | bic r0, r0, #CR_V | |
75d90832 HC |
159 | #endif |
160 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
f12d0d7c | 161 | #endif /* CONFIG_CPU_CP15 */ |
970d96f9 | 162 | ret lr |
93ed3970 | 163 | ENDPROC(__after_proc_init) |
3b920cef | 164 | .ltorg |
75d90832 | 165 | |
67c9845b JA |
166 | #ifdef CONFIG_ARM_MPU |
167 | ||
168 | ||
169 | /* Set which MPU region should be programmed */ | |
170 | .macro set_region_nr tmp, rgnr | |
171 | mov \tmp, \rgnr @ Use static region numbers | |
172 | mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR | |
173 | .endm | |
174 | ||
175 | /* Setup a single MPU region, either D or I side (D-side for unified) */ | |
176 | .macro setup_region bar, acr, sr, side = MPU_DATA_SIDE | |
177 | mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR | |
178 | mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR | |
179 | mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR | |
180 | .endm | |
181 | ||
182 | /* | |
183 | * Setup the MPU and initial MPU Regions. We create the following regions: | |
184 | * Region 0: Use this for probing the MPU details, so leave disabled. | |
185 | * Region 1: Background region - covers the whole of RAM as strongly ordered | |
186 | * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6 | |
9dfc28b6 | 187 | * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page |
67c9845b JA |
188 | * |
189 | * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION | |
190 | */ | |
191 | ||
192 | ENTRY(__setup_mpu) | |
193 | ||
194 | /* Probe for v7 PMSA compliance */ | |
195 | mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 | |
196 | and r0, r0, #(MMFR0_PMSA) @ PMSA field | |
197 | teq r0, #(MMFR0_PMSAv7) @ PMSA v7 | |
198 | bne __error_p @ Fail: ARM_MPU on NOT v7 PMSA | |
199 | ||
200 | /* Determine whether the D/I-side memory map is unified. We set the | |
201 | * flags here and continue to use them for the rest of this function */ | |
202 | mrc p15, 0, r0, c0, c0, 4 @ MPUIR | |
203 | ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU | |
204 | beq __error_p @ Fail: ARM_MPU and no MPU | |
205 | tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified | |
206 | ||
207 | /* Setup second region first to free up r6 */ | |
208 | set_region_nr r0, #MPU_RAM_REGION | |
209 | isb | |
210 | /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */ | |
b713aa0b | 211 | ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET |
67c9845b JA |
212 | ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL) |
213 | ||
214 | setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled | |
215 | beq 1f @ Memory-map not unified | |
216 | setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled | |
217 | 1: isb | |
218 | ||
219 | /* First/background region */ | |
220 | set_region_nr r0, #MPU_BG_REGION | |
221 | isb | |
222 | /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */ | |
223 | mov r0, #0 @ BG region starts at 0x0 | |
224 | ldr r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA) | |
225 | mov r6, #MPU_RSR_ALL_MEM @ 4GB region, enabled | |
226 | ||
227 | setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled | |
228 | beq 2f @ Memory-map not unified | |
229 | setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled | |
230 | 2: isb | |
231 | ||
9dfc28b6 JA |
232 | /* Vectors region */ |
233 | set_region_nr r0, #MPU_VECTORS_REGION | |
234 | isb | |
235 | /* Shared, inaccessible to PL0, rw PL1 */ | |
236 | mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE | |
237 | ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL) | |
238 | /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */ | |
239 | mov r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN) | |
240 | ||
241 | setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled | |
242 | beq 3f @ Memory-map not unified | |
243 | setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled | |
244 | 3: isb | |
245 | ||
67c9845b JA |
246 | /* Enable the MPU */ |
247 | mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR | |
248 | bic r0, r0, #CR_BR @ Disable the 'default mem-map' | |
249 | orr r0, r0, #CR_M @ Set SCTRL.M (MPU on) | |
250 | mcr p15, 0, r0, c1, c0, 0 @ Enable MPU | |
251 | isb | |
6ebbf2ce | 252 | ret lr |
67c9845b JA |
253 | ENDPROC(__setup_mpu) |
254 | #endif | |
75d90832 | 255 | #include "head-common.S" |