[deliverable/linux.git] / arch / arm / kernel / head-nommu.S

/*
 *  linux/arch/arm/kernel/head-nommu.S
 *
 *  Copyright (C) 1994-2002 Russell King
 *  Copyright (C) 2003-2006 Hyok S. Choi
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Common kernel startup code (non-paged MM)
 *
 */
#include <linux/linkage.h>
#include <linux/init.h>

#include <asm/assembler.h>
#include <asm/ptrace.h>
#include <asm/asm-offsets.h>
#include <asm/memory.h>
#include <asm/cp15.h>
#include <asm/thread_info.h>
#include <asm/v7m.h>
#include <asm/mpu.h>
#include <asm/page.h>

/*
 * Kernel startup entry point.
 * ---------------------------
 *
 * This is normally called from the decompressor code.  The requirements
 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
 * r1 = machine nr.
 *
 * See linux/arch/arm/tools/mach-types for the complete list of machine
 * numbers for r1.
 *
 */

	__HEAD

#ifdef CONFIG_CPU_THUMBONLY
	.thumb
ENTRY(stext)
#else
	.arm
ENTRY(stext)

 THUMB(	adr	r9, BSYM(1f)	)	@ Kernel is always entered in ARM.
 THUMB(	bx	r9		)	@ If this is a Thumb-2 kernel,
 THUMB(	.thumb			)	@ switch to Thumb now.
 THUMB(1:			)
#endif

	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
						@ and irqs disabled
#if defined(CONFIG_CPU_CP15)
	mrc	p15, 0, r9, c0, c0		@ get processor id
#elif defined(CONFIG_CPU_V7M)
	ldr	r9, =BASEADDR_V7M_SCB
	ldr	r9, [r9, V7M_SCB_CPUID]
#else
	ldr	r9, =CONFIG_PROCESSOR_ID
#endif
	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
	movs	r10, r5				@ invalid processor (r5=0)?
	beq	__error_p				@ yes, error 'p'

#ifdef CONFIG_ARM_MPU
	/* Calculate the size of a region covering just the kernel */
	ldr	r5, =PHYS_OFFSET		@ Region start: PHYS_OFFSET
	ldr     r6, =(_end)			@ Cover whole kernel
	sub	r6, r6, r5			@ Minimum size of region to map
	clz	r6, r6				@ Region size must be 2^N...
	rsb	r6, r6, #31			@ ...so round up region size
	lsl	r6, r6, #MPU_RSR_SZ		@ Put size in right field
	orr	r6, r6, #(1 << MPU_RSR_EN)	@ Set region enabled bit
	bl	__setup_mpu
#endif
	ldr	r13, =__mmap_switched		@ address to jump to after
						@ initialising sctlr
	adr	lr, BSYM(1f)			@ return (PIC) address
 ARM(	add	pc, r10, #PROCINFO_INITFUNC	)
 THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
 THUMB(	mov	pc, r12				)
 1:	b	__after_proc_init
ENDPROC(stext)

#ifdef CONFIG_SMP
ENTRY(secondary_startup)
	/*
	 * Common entry point for secondary CPUs.
	 *
	 * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
	 * the processor type - there is no need to check the machine type
	 * as it has already been validated by the primary processor.
	 */
	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
#ifndef CONFIG_CPU_CP15
	ldr	r9, =CONFIG_PROCESSOR_ID
#else
	mrc	p15, 0, r9, c0, c0		@ get processor id
#endif
	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
	movs	r10, r5				@ invalid processor?
	beq	__error_p			@ yes, error 'p'

	adr	r4, __secondary_data
	ldmia	r4, {r7, r12}

#ifdef CONFIG_ARM_MPU
	/* Use MPU region info supplied by __cpu_up */
	ldr	r6, [r7]			@ get secondary_data.mpu_szr
	bl      __setup_mpu			@ Initialize the MPU
#endif

	adr	lr, BSYM(__after_proc_init)	@ return address
	mov	r13, r12			@ __secondary_switched address
 ARM(	add	pc, r10, #PROCINFO_INITFUNC	)
 THUMB(	add	r12, r10, #PROCINFO_INITFUNC	)
 THUMB(	mov	pc, r12				)
ENDPROC(secondary_startup)

ENTRY(__secondary_switched)
	ldr	sp, [r7, #8]			@ set up the stack pointer
	mov	fp, #0
	b	secondary_start_kernel
ENDPROC(__secondary_switched)

	.type	__secondary_data, %object
__secondary_data:
	.long	secondary_data
	.long	__secondary_switched
#endif /* CONFIG_SMP */

/*
 * Set the Control Register and Read the process ID.
 */
__after_proc_init:
#ifdef CONFIG_CPU_CP15
	/*
	 * CP15 system control register value returned in r0 from
	 * the CPU init function.
	 */
#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
	orr	r0, r0, #CR_A
#else
	bic	r0, r0, #CR_A
#endif
#ifdef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CR_C
#endif
#ifdef CONFIG_CPU_BPREDICT_DISABLE
	bic	r0, r0, #CR_Z
#endif
#ifdef CONFIG_CPU_ICACHE_DISABLE
	bic	r0, r0, #CR_I
#endif
#ifdef CONFIG_CPU_HIGH_VECTOR
	orr	r0, r0, #CR_V
#else
	bic	r0, r0, #CR_V
#endif
	mcr	p15, 0, r0, c1, c0, 0		@ write control reg
#endif /* CONFIG_CPU_CP15 */
	mov	pc, r13
ENDPROC(__after_proc_init)
	.ltorg

#ifdef CONFIG_ARM_MPU


/* Set which MPU region should be programmed */
.macro set_region_nr tmp, rgnr
	mov	\tmp, \rgnr			@ Use static region numbers
	mcr	p15, 0, \tmp, c6, c2, 0		@ Write RGNR
.endm

/* Setup a single MPU region, either D or I side (D-side for unified) */
.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
	mcr	p15, 0, \bar, c6, c1, (0 + \side)	@ I/DRBAR
	mcr	p15, 0, \acr, c6, c1, (4 + \side)	@ I/DRACR
	mcr	p15, 0, \sr, c6, c1, (2 + \side)		@ I/DRSR
.endm

/*
 * Setup the MPU and initial MPU Regions. We create the following regions:
 * Region 0: Use this for probing the MPU details, so leave disabled.
 * Region 1: Background region - covers the whole of RAM as strongly ordered
 * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
 * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
 *
 * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
*/

ENTRY(__setup_mpu)

	/* Probe for v7 PMSA compliance */
	mrc	p15, 0, r0, c0, c1, 4		@ Read ID_MMFR0
	and	r0, r0, #(MMFR0_PMSA)		@ PMSA field
	teq	r0, #(MMFR0_PMSAv7)		@ PMSA v7
	bne	__error_p			@ Fail: ARM_MPU on NOT v7 PMSA

	/* Determine whether the D/I-side memory map is unified. We set the
	 * flags here and continue to use them for the rest of this function */
	mrc	p15, 0, r0, c0, c0, 4		@ MPUIR
	ands	r5, r0, #MPUIR_DREGION_SZMASK	@ 0 size d region => No MPU
	beq	__error_p			@ Fail: ARM_MPU and no MPU
	tst	r0, #MPUIR_nU			@ MPUIR_nU = 0 for unified

	/* Setup second region first to free up r6 */
	set_region_nr r0, #MPU_RAM_REGION
	isb
	/* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
	ldr	r0, =PHYS_OFFSET		@ RAM starts at PHYS_OFFSET
	ldr	r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)

	setup_region r0, r5, r6, MPU_DATA_SIDE	@ PHYS_OFFSET, shared, enabled
	beq	1f				@ Memory-map not unified
	setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
1:	isb

	/* First/background region */
	set_region_nr r0, #MPU_BG_REGION
	isb
	/* Execute Never,  strongly ordered, inaccessible to PL0, rw PL1  */
	mov	r0, #0				@ BG region starts at 0x0
	ldr	r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
	mov	r6, #MPU_RSR_ALL_MEM		@ 4GB region, enabled

	setup_region r0, r5, r6, MPU_DATA_SIDE	@ 0x0, BG region, enabled
	beq	2f				@ Memory-map not unified
	setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
2:	isb

	/* Vectors region */
	set_region_nr r0, #MPU_VECTORS_REGION
	isb
	/* Shared, inaccessible to PL0, rw PL1 */
	mov	r0, #CONFIG_VECTORS_BASE	@ Cover from VECTORS_BASE
	ldr	r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
	/* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
	mov	r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)

	setup_region r0, r5, r6, MPU_DATA_SIDE	@ VECTORS_BASE, PL0 NA, enabled
	beq	3f				@ Memory-map not unified
	setup_region r0, r5, r6, MPU_INSTR_SIDE	@ VECTORS_BASE, PL0 NA, enabled
3:	isb

	/* Enable the MPU */
	mrc	p15, 0, r0, c1, c0, 0		@ Read SCTLR
	bic     r0, r0, #CR_BR			@ Disable the 'default mem-map'
	orr	r0, r0, #CR_M			@ Set SCTRL.M (MPU on)
	mcr	p15, 0, r0, c1, c0, 0		@ Enable MPU
	isb
	mov pc,lr
ENDPROC(__setup_mpu)
#endif
#include "head-common.S"
Commit	Line	Data
75d90832 HC	1	/*
	2	* linux/arch/arm/kernel/head-nommu.S
	3	*
	4	* Copyright (C) 1994-2002 Russell King
	5	* Copyright (C) 2003-2006 Hyok S. Choi
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Common kernel startup code (non-paged MM)
75d90832 HC	12	*
75d90832 HC	13	*/
75d90832 HC	14	#include <linux/linkage.h>
	15	#include <linux/init.h>
	16
	17	#include <asm/assembler.h>
75d90832	18	#include <asm/ptrace.h>
2eb9d315	19	#include <asm/asm-offsets.h>
67c9845b	20	#include <asm/memory.h>
15d07dc9	21	#include <asm/cp15.h>
3b920cef	22	#include <asm/thread_info.h>
55bdd694	23	#include <asm/v7m.h>
67c9845b	24	#include <asm/mpu.h>
9dfc28b6	25	#include <asm/page.h>
75d90832	26
75d90832 HC	27	/*
	28	* Kernel startup entry point.
	29	* ---------------------------
	30	*
	31	* This is normally called from the decompressor code. The requirements
	32	* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
	33	* r1 = machine nr.
	34	*
	35	* See linux/arch/arm/tools/mach-types for the complete list of machine
	36	* numbers for r1.
	37	*
	38	*/
540b5738	39
2abc1c50	40	__HEAD
bc7dea00 UKK	41
	42	#ifdef CONFIG_CPU_THUMBONLY
	43	.thumb
	44	ENTRY(stext)
	45	#else
	46	.arm
75d90832	47	ENTRY(stext)
540b5738 DM	48
	49	THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
	50	THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
	51	THUMB( .thumb ) @ switch to Thumb now.
	52	THUMB(1: )
bc7dea00	53	#endif
540b5738	54
b86040a5	55	setmode PSR_F_BIT \| PSR_I_BIT \| SVC_MODE, r9 @ ensure svc mode
75d90832	56	@ and irqs disabled
55bdd694	57	#if defined(CONFIG_CPU_CP15)
75d90832	58	mrc p15, 0, r9, c0, c0 @ get processor id
55bdd694 CM	59	#elif defined(CONFIG_CPU_V7M)
	60	ldr r9, =BASEADDR_V7M_SCB
	61	ldr r9, [r9, V7M_SCB_CPUID]
	62	#else
	63	ldr r9, =CONFIG_PROCESSOR_ID
f12d0d7c	64	#endif
75d90832 HC	65	bl __lookup_processor_type @ r5=procinfo r9=cpuid
	66	movs r10, r5 @ invalid processor (r5=0)?
	67	beq __error_p @ yes, error 'p'
75d90832	68
67c9845b JA	69	#ifdef CONFIG_ARM_MPU
	70	/* Calculate the size of a region covering just the kernel */
	71	ldr r5, =PHYS_OFFSET @ Region start: PHYS_OFFSET
	72	ldr r6, =(_end) @ Cover whole kernel
	73	sub r6, r6, r5 @ Minimum size of region to map
	74	clz r6, r6 @ Region size must be 2^N...
	75	rsb r6, r6, #31 @ ...so round up region size
	76	lsl r6, r6, #MPU_RSR_SZ @ Put size in right field
	77	orr r6, r6, #(1 << MPU_RSR_EN) @ Set region enabled bit
	78	bl __setup_mpu
	79	#endif
01fafcab WD	80	ldr r13, =__mmap_switched @ address to jump to after
	81	@ initialising sctlr
	82	adr lr, BSYM(1f) @ return (PIC) address
b86040a5 CM	83	ARM( add pc, r10, #PROCINFO_INITFUNC )
	84	THUMB( add r12, r10, #PROCINFO_INITFUNC )
	85	THUMB( mov pc, r12 )
01fafcab	86	1: b __after_proc_init
93ed3970	87	ENDPROC(stext)
75d90832	88
01fafcab	89	#ifdef CONFIG_SMP
01fafcab WD	90	ENTRY(secondary_startup)
	91	/*
	92	* Common entry point for secondary CPUs.
	93	*
	94	* Ensure that we're in SVC mode, and IRQs are disabled. Lookup
	95	* the processor type - there is no need to check the machine type
	96	* as it has already been validated by the primary processor.
	97	*/
	98	setmode PSR_F_BIT \| PSR_I_BIT \| SVC_MODE, r9
	99	#ifndef CONFIG_CPU_CP15
	100	ldr r9, =CONFIG_PROCESSOR_ID
	101	#else
	102	mrc p15, 0, r9, c0, c0 @ get processor id
	103	#endif
	104	bl __lookup_processor_type @ r5=procinfo r9=cpuid
	105	movs r10, r5 @ invalid processor?
	106	beq __error_p @ yes, error 'p'
	107
	108	adr r4, __secondary_data
	109	ldmia r4, {r7, r12}
eb08375e JA	110
	111	#ifdef CONFIG_ARM_MPU
	112	/* Use MPU region info supplied by __cpu_up */
	113	ldr r6, [r7] @ get secondary_data.mpu_szr
	114	bl __setup_mpu @ Initialize the MPU
	115	#endif
	116
01fafcab WD	117	adr lr, BSYM(__after_proc_init) @ return address
	118	mov r13, r12 @ __secondary_switched address
	119	ARM( add pc, r10, #PROCINFO_INITFUNC )
	120	THUMB( add r12, r10, #PROCINFO_INITFUNC )
	121	THUMB( mov pc, r12 )
	122	ENDPROC(secondary_startup)
	123
	124	ENTRY(__secondary_switched)
	125	ldr sp, [r7, #8] @ set up the stack pointer
	126	mov fp, #0
	127	b secondary_start_kernel
	128	ENDPROC(__secondary_switched)
	129
	130	.type __secondary_data, %object
	131	__secondary_data:
	132	.long secondary_data
	133	.long __secondary_switched
	134	#endif /* CONFIG_SMP */
	135
75d90832 HC	136	/*
	137	* Set the Control Register and Read the process ID.
	138	*/
75d90832	139	__after_proc_init:
f12d0d7c	140	#ifdef CONFIG_CPU_CP15
05efde9d CM	141	/*
	142	* CP15 system control register value returned in r0 from
	143	* the CPU init function.
	144	*/
76e09204	145	#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
75d90832 HC	146	orr r0, r0, #CR_A
	147	#else
	148	bic r0, r0, #CR_A
	149	#endif
	150	#ifdef CONFIG_CPU_DCACHE_DISABLE
	151	bic r0, r0, #CR_C
	152	#endif
	153	#ifdef CONFIG_CPU_BPREDICT_DISABLE
	154	bic r0, r0, #CR_Z
	155	#endif
	156	#ifdef CONFIG_CPU_ICACHE_DISABLE
	157	bic r0, r0, #CR_I
6afd6fae HC	158	#endif
	159	#ifdef CONFIG_CPU_HIGH_VECTOR
	160	orr r0, r0, #CR_V
	161	#else
	162	bic r0, r0, #CR_V
75d90832 HC	163	#endif
75d90832 HC	164	mcr p15, 0, r0, c1, c0, 0 @ write control reg
f12d0d7c	165	#endif /* CONFIG_CPU_CP15 */
01fafcab	166	mov pc, r13
93ed3970	167	ENDPROC(__after_proc_init)
3b920cef	168	.ltorg
75d90832	169
67c9845b JA	170	#ifdef CONFIG_ARM_MPU
	171
	172
	173	/* Set which MPU region should be programmed */
	174	.macro set_region_nr tmp, rgnr
	175	mov \tmp, \rgnr @ Use static region numbers
	176	mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
	177	.endm
	178
	179	/* Setup a single MPU region, either D or I side (D-side for unified) */
	180	.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
	181	mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
	182	mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
	183	mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
	184	.endm
	185
	186	/*
	187	* Setup the MPU and initial MPU Regions. We create the following regions:
	188	* Region 0: Use this for probing the MPU details, so leave disabled.
	189	* Region 1: Background region - covers the whole of RAM as strongly ordered
	190	* Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
9dfc28b6	191	* Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
67c9845b JA	192	*
	193	* r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
	194	*/
	195
	196	ENTRY(__setup_mpu)
	197
	198	/* Probe for v7 PMSA compliance */
	199	mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
	200	and r0, r0, #(MMFR0_PMSA) @ PMSA field
	201	teq r0, #(MMFR0_PMSAv7) @ PMSA v7
	202	bne __error_p @ Fail: ARM_MPU on NOT v7 PMSA
	203
	204	/* Determine whether the D/I-side memory map is unified. We set the
	205	* flags here and continue to use them for the rest of this function */
	206	mrc p15, 0, r0, c0, c0, 4 @ MPUIR
	207	ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
	208	beq __error_p @ Fail: ARM_MPU and no MPU
	209	tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
	210
	211	/* Setup second region first to free up r6 */
	212	set_region_nr r0, #MPU_RAM_REGION
	213	isb
	214	/* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
	215	ldr r0, =PHYS_OFFSET @ RAM starts at PHYS_OFFSET
	216	ldr r5,=(MPU_AP_PL1RW_PL0RW \| MPU_RGN_NORMAL)
	217
	218	setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled
	219	beq 1f @ Memory-map not unified
	220	setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
	221	1: isb
	222
	223	/* First/background region */
	224	set_region_nr r0, #MPU_BG_REGION
	225	isb
	226	/* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */
	227	mov r0, #0 @ BG region starts at 0x0
	228	ldr r5,=(MPU_ACR_XN \| MPU_RGN_STRONGLY_ORDERED \| MPU_AP_PL1RW_PL0NA)
	229	mov r6, #MPU_RSR_ALL_MEM @ 4GB region, enabled
	230
	231	setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled
	232	beq 2f @ Memory-map not unified
	233	setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
	234	2: isb
	235
9dfc28b6 JA	236	/* Vectors region */
	237	set_region_nr r0, #MPU_VECTORS_REGION
	238	isb
	239	/* Shared, inaccessible to PL0, rw PL1 */
	240	mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE
	241	ldr r5,=(MPU_AP_PL1RW_PL0NA \| MPU_RGN_NORMAL)
	242	/* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
	243	mov r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) \| 1 << MPU_RSR_EN)
	244
	245	setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled
	246	beq 3f @ Memory-map not unified
	247	setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled
	248	3: isb
	249
67c9845b JA	250	/* Enable the MPU */
	251	mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
	252	bic r0, r0, #CR_BR @ Disable the 'default mem-map'
	253	orr r0, r0, #CR_M @ Set SCTRL.M (MPU on)
	254	mcr p15, 0, r0, c1, c0, 0 @ Enable MPU
	255	isb
	256	mov pc,lr
	257	ENDPROC(__setup_mpu)
	258	#endif
75d90832	259	#include "head-common.S"