Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/head.S | |
3 | * | |
4 | * Copyright (C) 1994-2002 Russell King | |
e65f38ed RK |
5 | * Copyright (c) 2003 ARM Limited |
6 | * All Rights Reserved | |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Kernel startup code for all 32-bit CPUs | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/linkage.h> |
15 | #include <linux/init.h> | |
16 | ||
17 | #include <asm/assembler.h> | |
18 | #include <asm/domain.h> | |
1da177e4 | 19 | #include <asm/ptrace.h> |
e6ae744d | 20 | #include <asm/asm-offsets.h> |
f09b9979 | 21 | #include <asm/memory.h> |
4f7a1812 | 22 | #include <asm/thread_info.h> |
1da177e4 LT |
23 | #include <asm/system.h> |
24 | ||
c293393f JK |
25 | #ifdef CONFIG_DEBUG_LL |
26 | #include <mach/debug-macro.S> | |
27 | #endif | |
28 | ||
1da177e4 | 29 | /* |
37d07b72 | 30 | * swapper_pg_dir is the virtual address of the initial page table. |
f06b97ff RK |
31 | * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must |
32 | * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect | |
37d07b72 | 33 | * the least significant 16 bits to be 0x8000, but we could probably |
f06b97ff | 34 | * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. |
1da177e4 | 35 | */ |
72a20e22 | 36 | #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) |
f06b97ff RK |
37 | #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 |
38 | #error KERNEL_RAM_VADDR must start at 0xXXXX8000 | |
1da177e4 LT |
39 | #endif |
40 | ||
41 | .globl swapper_pg_dir | |
f06b97ff | 42 | .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 |
1da177e4 | 43 | |
72a20e22 RK |
44 | .macro pgtbl, rd, phys |
45 | add \rd, \phys, #TEXT_OFFSET - 0x4000 | |
1da177e4 | 46 | .endm |
1da177e4 | 47 | |
37d07b72 | 48 | #ifdef CONFIG_XIP_KERNEL |
e98ff7f6 NP |
49 | #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) |
50 | #define KERNEL_END _edata_loc | |
37d07b72 | 51 | #else |
e98ff7f6 NP |
52 | #define KERNEL_START KERNEL_RAM_VADDR |
53 | #define KERNEL_END _end | |
1da177e4 LT |
54 | #endif |
55 | ||
56 | /* | |
57 | * Kernel startup entry point. | |
58 | * --------------------------- | |
59 | * | |
60 | * This is normally called from the decompressor code. The requirements | |
61 | * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, | |
9d20fdd5 | 62 | * r1 = machine nr, r2 = atags pointer. |
1da177e4 LT |
63 | * |
64 | * This code is mostly position independent, so if you link the kernel at | |
65 | * 0xc0008000, you call this at __pa(0xc0008000). | |
66 | * | |
67 | * See linux/arch/arm/tools/mach-types for the complete list of machine | |
68 | * numbers for r1. | |
69 | * | |
70 | * We're trying to keep crap to a minimum; DO NOT add any machine specific | |
71 | * crap here - that's what the boot loader (or in extreme, well justified | |
72 | * circumstances, zImage) is for. | |
73 | */ | |
2abc1c50 | 74 | __HEAD |
1da177e4 | 75 | ENTRY(stext) |
b86040a5 | 76 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode |
1da177e4 | 77 | @ and irqs disabled |
0f44ba1d | 78 | mrc p15, 0, r9, c0, c0 @ get processor id |
1da177e4 LT |
79 | bl __lookup_processor_type @ r5=procinfo r9=cpuid |
80 | movs r10, r5 @ invalid processor (r5=0)? | |
a75e5248 | 81 | THUMB( it eq ) @ force fixup-able long branch encoding |
3c0bdac3 | 82 | beq __error_p @ yes, error 'p' |
0eb0511d | 83 | |
72a20e22 RK |
84 | #ifndef CONFIG_XIP_KERNEL |
85 | adr r3, 2f | |
86 | ldmia r3, {r4, r8} | |
87 | sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) | |
88 | add r8, r8, r4 @ PHYS_OFFSET | |
89 | #else | |
90 | ldr r8, =PLAT_PHYS_OFFSET | |
91 | #endif | |
92 | ||
0eb0511d RK |
93 | /* |
94 | * r1 = machine no, r2 = atags, | |
72a20e22 | 95 | * r8 = phys_offset, r9 = cpuid, r10 = procinfo |
0eb0511d | 96 | */ |
9d20fdd5 | 97 | bl __vet_atags |
f00ec48f RK |
98 | #ifdef CONFIG_SMP_ON_UP |
99 | bl __fixup_smp | |
dc21af99 RK |
100 | #endif |
101 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT | |
102 | bl __fixup_pv_table | |
f00ec48f | 103 | #endif |
1da177e4 LT |
104 | bl __create_page_tables |
105 | ||
106 | /* | |
107 | * The following calls CPU specific code in a position independent | |
108 | * manner. See arch/arm/mm/proc-*.S for details. r10 = base of | |
6fc31d54 | 109 | * xxx_proc_info structure selected by __lookup_processor_type |
1da177e4 LT |
110 | * above. On return, the CPU will be ready for the MMU to be |
111 | * turned on, and r0 will hold the CPU control register value. | |
112 | */ | |
a4ae4134 | 113 | ldr r13, =__mmap_switched @ address to jump to after |
1da177e4 | 114 | @ mmu has been enabled |
00945010 | 115 | adr lr, BSYM(1f) @ return (PIC) address |
b86040a5 CM |
116 | ARM( add pc, r10, #PROCINFO_INITFUNC ) |
117 | THUMB( add r12, r10, #PROCINFO_INITFUNC ) | |
118 | THUMB( mov pc, r12 ) | |
00945010 | 119 | 1: b __enable_mmu |
93ed3970 | 120 | ENDPROC(stext) |
a4ae4134 | 121 | .ltorg |
72a20e22 RK |
122 | #ifndef CONFIG_XIP_KERNEL |
123 | 2: .long . | |
124 | .long PAGE_OFFSET | |
125 | #endif | |
1da177e4 LT |
126 | |
127 | /* | |
128 | * Setup the initial page tables. We only setup the barest | |
129 | * amount which are required to get the kernel running, which | |
130 | * generally means mapping in the kernel code. | |
131 | * | |
72a20e22 | 132 | * r8 = phys_offset, r9 = cpuid, r10 = procinfo |
1da177e4 LT |
133 | * |
134 | * Returns: | |
786f1b73 | 135 | * r0, r3, r5-r7 corrupted |
1da177e4 LT |
136 | * r4 = physical page table address |
137 | */ | |
1da177e4 | 138 | __create_page_tables: |
72a20e22 | 139 | pgtbl r4, r8 @ page table address |
1da177e4 LT |
140 | |
141 | /* | |
142 | * Clear the 16K level 1 swapper page table | |
143 | */ | |
144 | mov r0, r4 | |
145 | mov r3, #0 | |
146 | add r6, r0, #0x4000 | |
147 | 1: str r3, [r0], #4 | |
148 | str r3, [r0], #4 | |
149 | str r3, [r0], #4 | |
150 | str r3, [r0], #4 | |
151 | teq r0, r6 | |
152 | bne 1b | |
153 | ||
8799ee9f | 154 | ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags |
1da177e4 LT |
155 | |
156 | /* | |
786f1b73 RK |
157 | * Create identity mapping to cater for __enable_mmu. |
158 | * This identity mapping will be removed by paging_init(). | |
1da177e4 | 159 | */ |
786f1b73 RK |
160 | adr r0, __enable_mmu_loc |
161 | ldmia r0, {r3, r5, r6} | |
162 | sub r0, r0, r3 @ virt->phys offset | |
163 | add r5, r5, r0 @ phys __enable_mmu | |
164 | add r6, r6, r0 @ phys __enable_mmu_end | |
165 | mov r5, r5, lsr #20 | |
166 | mov r6, r6, lsr #20 | |
167 | ||
168 | 1: orr r3, r7, r5, lsl #20 @ flags + kernel base | |
169 | str r3, [r4, r5, lsl #2] @ identity mapping | |
170 | teq r5, r6 | |
171 | addne r5, r5, #1 @ next section | |
172 | bne 1b | |
1da177e4 LT |
173 | |
174 | /* | |
175 | * Now setup the pagetables for our kernel direct | |
2552fc27 | 176 | * mapped region. |
1da177e4 | 177 | */ |
786f1b73 RK |
178 | mov r3, pc |
179 | mov r3, r3, lsr #20 | |
180 | orr r3, r7, r3, lsl #20 | |
e98ff7f6 NP |
181 | add r0, r4, #(KERNEL_START & 0xff000000) >> 18 |
182 | str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! | |
183 | ldr r6, =(KERNEL_END - 1) | |
184 | add r0, r0, #4 | |
185 | add r6, r4, r6, lsr #18 | |
186 | 1: cmp r0, r6 | |
187 | add r3, r3, #1 << 20 | |
188 | strls r3, [r0], #4 | |
189 | bls 1b | |
1da177e4 | 190 | |
ec3622d9 NP |
191 | #ifdef CONFIG_XIP_KERNEL |
192 | /* | |
193 | * Map some ram to cover our .data and .bss areas. | |
194 | */ | |
72a20e22 RK |
195 | add r3, r8, #TEXT_OFFSET |
196 | orr r3, r3, r7 | |
ec3622d9 NP |
197 | add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 |
198 | str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! | |
199 | ldr r6, =(_end - 1) | |
200 | add r0, r0, #4 | |
201 | add r6, r4, r6, lsr #18 | |
202 | 1: cmp r0, r6 | |
203 | add r3, r3, #1 << 20 | |
204 | strls r3, [r0], #4 | |
205 | bls 1b | |
206 | #endif | |
207 | ||
1da177e4 | 208 | /* |
4d901c42 RH |
209 | * Then map boot params address in r2 or |
210 | * the first 1MB of ram if boot params address is not specified. | |
1da177e4 | 211 | */ |
4d901c42 RH |
212 | mov r0, r2, lsr #20 |
213 | movs r0, r0, lsl #20 | |
214 | moveq r0, r8 | |
215 | sub r3, r0, r8 | |
216 | add r3, r3, #PAGE_OFFSET | |
217 | add r3, r4, r3, lsr #18 | |
218 | orr r6, r7, r0 | |
219 | str r6, [r3] | |
1da177e4 | 220 | |
c77b0427 | 221 | #ifdef CONFIG_DEBUG_LL |
c293393f | 222 | #ifndef CONFIG_DEBUG_ICEDCC |
1da177e4 LT |
223 | /* |
224 | * Map in IO space for serial debugging. | |
225 | * This allows debug messages to be output | |
226 | * via a serial console before paging_init. | |
227 | */ | |
c293393f JK |
228 | addruart r7, r3 |
229 | ||
230 | mov r3, r3, lsr #20 | |
231 | mov r3, r3, lsl #2 | |
232 | ||
1da177e4 LT |
233 | add r0, r4, r3 |
234 | rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) | |
235 | cmp r3, #0x0800 @ limit to 512MB | |
236 | movhi r3, #0x0800 | |
237 | add r6, r0, r3 | |
c293393f JK |
238 | mov r3, r7, lsr #20 |
239 | ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags | |
240 | orr r3, r7, r3, lsl #20 | |
1da177e4 LT |
241 | 1: str r3, [r0], #4 |
242 | add r3, r3, #1 << 20 | |
243 | teq r0, r6 | |
244 | bne 1b | |
c293393f JK |
245 | |
246 | #else /* CONFIG_DEBUG_ICEDCC */ | |
247 | /* we don't need any serial debugging mappings for ICEDCC */ | |
248 | ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags | |
249 | #endif /* !CONFIG_DEBUG_ICEDCC */ | |
250 | ||
1da177e4 LT |
251 | #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) |
252 | /* | |
3c0bdac3 RK |
253 | * If we're using the NetWinder or CATS, we also need to map |
254 | * in the 16550-type serial port for the debug messages | |
1da177e4 | 255 | */ |
c77b0427 RK |
256 | add r0, r4, #0xff000000 >> 18 |
257 | orr r3, r7, #0x7c000000 | |
258 | str r3, [r0] | |
1da177e4 | 259 | #endif |
1da177e4 LT |
260 | #ifdef CONFIG_ARCH_RPC |
261 | /* | |
262 | * Map in screen at 0x02000000 & SCREEN2_BASE | |
263 | * Similar reasons here - for debug. This is | |
264 | * only for Acorn RiscPC architectures. | |
265 | */ | |
c77b0427 RK |
266 | add r0, r4, #0x02000000 >> 18 |
267 | orr r3, r7, #0x02000000 | |
1da177e4 | 268 | str r3, [r0] |
c77b0427 | 269 | add r0, r4, #0xd8000000 >> 18 |
1da177e4 | 270 | str r3, [r0] |
c77b0427 | 271 | #endif |
1da177e4 LT |
272 | #endif |
273 | mov pc, lr | |
93ed3970 | 274 | ENDPROC(__create_page_tables) |
1da177e4 | 275 | .ltorg |
4f79a5dd | 276 | .align |
786f1b73 RK |
277 | __enable_mmu_loc: |
278 | .long . | |
279 | .long __enable_mmu | |
280 | .long __enable_mmu_end | |
1da177e4 | 281 | |
00945010 RK |
282 | #if defined(CONFIG_SMP) |
283 | __CPUINIT | |
284 | ENTRY(secondary_startup) | |
285 | /* | |
286 | * Common entry point for secondary CPUs. | |
287 | * | |
288 | * Ensure that we're in SVC mode, and IRQs are disabled. Lookup | |
289 | * the processor type - there is no need to check the machine type | |
290 | * as it has already been validated by the primary processor. | |
291 | */ | |
292 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 | |
293 | mrc p15, 0, r9, c0, c0 @ get processor id | |
294 | bl __lookup_processor_type | |
295 | movs r10, r5 @ invalid processor? | |
296 | moveq r0, #'p' @ yes, error 'p' | |
a75e5248 | 297 | THUMB( it eq ) @ force fixup-able long branch encoding |
00945010 RK |
298 | beq __error_p |
299 | ||
300 | /* | |
301 | * Use the page tables supplied from __cpu_up. | |
302 | */ | |
303 | adr r4, __secondary_data | |
304 | ldmia r4, {r5, r7, r12} @ address to jump to after | |
305 | sub r4, r4, r5 @ mmu has been enabled | |
306 | ldr r4, [r7, r4] @ get secondary_data.pgdir | |
307 | adr lr, BSYM(__enable_mmu) @ return address | |
308 | mov r13, r12 @ __secondary_switched address | |
309 | ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor | |
310 | @ (return control reg) | |
311 | THUMB( add r12, r10, #PROCINFO_INITFUNC ) | |
312 | THUMB( mov pc, r12 ) | |
313 | ENDPROC(secondary_startup) | |
314 | ||
315 | /* | |
316 | * r6 = &secondary_data | |
317 | */ | |
318 | ENTRY(__secondary_switched) | |
319 | ldr sp, [r7, #4] @ get secondary_data.stack | |
320 | mov fp, #0 | |
321 | b secondary_start_kernel | |
322 | ENDPROC(__secondary_switched) | |
323 | ||
4f79a5dd DM |
324 | .align |
325 | ||
00945010 RK |
326 | .type __secondary_data, %object |
327 | __secondary_data: | |
328 | .long . | |
329 | .long secondary_data | |
330 | .long __secondary_switched | |
331 | #endif /* defined(CONFIG_SMP) */ | |
332 | ||
333 | ||
334 | ||
335 | /* | |
336 | * Setup common bits before finally enabling the MMU. Essentially | |
337 | * this is just loading the page table pointer and domain access | |
338 | * registers. | |
865a4fae RK |
339 | * |
340 | * r0 = cp#15 control register | |
341 | * r1 = machine ID | |
342 | * r2 = atags pointer | |
343 | * r4 = page table pointer | |
344 | * r9 = processor ID | |
345 | * r13 = *virtual* address to jump to upon completion | |
00945010 RK |
346 | */ |
347 | __enable_mmu: | |
348 | #ifdef CONFIG_ALIGNMENT_TRAP | |
349 | orr r0, r0, #CR_A | |
350 | #else | |
351 | bic r0, r0, #CR_A | |
352 | #endif | |
353 | #ifdef CONFIG_CPU_DCACHE_DISABLE | |
354 | bic r0, r0, #CR_C | |
355 | #endif | |
356 | #ifdef CONFIG_CPU_BPREDICT_DISABLE | |
357 | bic r0, r0, #CR_Z | |
358 | #endif | |
359 | #ifdef CONFIG_CPU_ICACHE_DISABLE | |
360 | bic r0, r0, #CR_I | |
361 | #endif | |
362 | mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ | |
363 | domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ | |
364 | domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ | |
365 | domain_val(DOMAIN_IO, DOMAIN_CLIENT)) | |
366 | mcr p15, 0, r5, c3, c0, 0 @ load domain access register | |
367 | mcr p15, 0, r4, c2, c0, 0 @ load page table pointer | |
368 | b __turn_mmu_on | |
369 | ENDPROC(__enable_mmu) | |
370 | ||
371 | /* | |
372 | * Enable the MMU. This completely changes the structure of the visible | |
373 | * memory space. You will not be able to trace execution through this. | |
374 | * If you have an enquiry about this, *please* check the linux-arm-kernel | |
375 | * mailing list archives BEFORE sending another post to the list. | |
376 | * | |
377 | * r0 = cp#15 control register | |
865a4fae RK |
378 | * r1 = machine ID |
379 | * r2 = atags pointer | |
380 | * r9 = processor ID | |
00945010 RK |
381 | * r13 = *virtual* address to jump to upon completion |
382 | * | |
383 | * other registers depend on the function called upon completion | |
384 | */ | |
385 | .align 5 | |
386 | __turn_mmu_on: | |
387 | mov r0, r0 | |
388 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
389 | mrc p15, 0, r3, c0, c0, 0 @ read id reg | |
390 | mov r3, r3 | |
391 | mov r3, r13 | |
392 | mov pc, r3 | |
393 | __enable_mmu_end: | |
394 | ENDPROC(__turn_mmu_on) | |
395 | ||
1da177e4 | 396 | |
f00ec48f RK |
397 | #ifdef CONFIG_SMP_ON_UP |
398 | __fixup_smp: | |
e98ff0f5 RK |
399 | and r3, r9, #0x000f0000 @ architecture version |
400 | teq r3, #0x000f0000 @ CPU ID supported? | |
f00ec48f RK |
401 | bne __fixup_smp_on_up @ no, assume UP |
402 | ||
e98ff0f5 RK |
403 | bic r3, r9, #0x00ff0000 |
404 | bic r3, r3, #0x0000000f @ mask 0xff00fff0 | |
405 | mov r4, #0x41000000 | |
0eb0511d | 406 | orr r4, r4, #0x0000b000 |
e98ff0f5 RK |
407 | orr r4, r4, #0x00000020 @ val 0x4100b020 |
408 | teq r3, r4 @ ARM 11MPCore? | |
f00ec48f RK |
409 | moveq pc, lr @ yes, assume SMP |
410 | ||
411 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR | |
e98ff0f5 RK |
412 | and r0, r0, #0xc0000000 @ multiprocessing extensions and |
413 | teq r0, #0x80000000 @ not part of a uniprocessor system? | |
414 | moveq pc, lr @ yes, assume SMP | |
f00ec48f RK |
415 | |
416 | __fixup_smp_on_up: | |
417 | adr r0, 1f | |
0eb0511d | 418 | ldmia r0, {r3 - r5} |
f00ec48f | 419 | sub r3, r0, r3 |
0eb0511d RK |
420 | add r4, r4, r3 |
421 | add r5, r5, r3 | |
422 | 2: cmp r4, r5 | |
ed3768a8 | 423 | movhs pc, lr |
0eb0511d | 424 | ldmia r4!, {r0, r6} |
ed3768a8 DM |
425 | ARM( str r6, [r0, r3] ) |
426 | THUMB( add r0, r0, r3 ) | |
427 | #ifdef __ARMEB__ | |
428 | THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. | |
429 | #endif | |
430 | THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords | |
431 | THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. | |
432 | THUMB( strh r6, [r0] ) | |
433 | b 2b | |
f00ec48f RK |
434 | ENDPROC(__fixup_smp) |
435 | ||
4f79a5dd | 436 | .align |
f00ec48f RK |
437 | 1: .word . |
438 | .word __smpalt_begin | |
439 | .word __smpalt_end | |
440 | ||
441 | .pushsection .data | |
442 | .globl smp_on_up | |
443 | smp_on_up: | |
444 | ALT_SMP(.long 1) | |
445 | ALT_UP(.long 0) | |
446 | .popsection | |
447 | ||
448 | #endif | |
449 | ||
dc21af99 RK |
450 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT |
451 | ||
452 | /* __fixup_pv_table - patch the stub instructions with the delta between | |
453 | * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and | |
454 | * can be expressed by an immediate shifter operand. The stub instruction | |
455 | * has a form of '(add|sub) rd, rn, #imm'. | |
456 | */ | |
457 | __HEAD | |
458 | __fixup_pv_table: | |
459 | adr r0, 1f | |
460 | ldmia r0, {r3-r5, r7} | |
461 | sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET | |
462 | add r4, r4, r3 @ adjust table start address | |
463 | add r5, r5, r3 @ adjust table end address | |
464 | str r8, [r7, r3]! @ save computed PHYS_OFFSET to __pv_phys_offset | |
cada3c08 | 465 | #ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT |
dc21af99 RK |
466 | mov r6, r3, lsr #24 @ constant for add/sub instructions |
467 | teq r3, r6, lsl #24 @ must be 16MiB aligned | |
cada3c08 RK |
468 | #else |
469 | mov r6, r3, lsr #16 @ constant for add/sub instructions | |
470 | teq r3, r6, lsl #16 @ must be 64kiB aligned | |
471 | #endif | |
dc21af99 RK |
472 | bne __error |
473 | str r6, [r7, #4] @ save to __pv_offset | |
474 | b __fixup_a_pv_table | |
475 | ENDPROC(__fixup_pv_table) | |
476 | ||
477 | .align | |
478 | 1: .long . | |
479 | .long __pv_table_begin | |
480 | .long __pv_table_end | |
481 | 2: .long __pv_phys_offset | |
482 | ||
483 | .text | |
484 | __fixup_a_pv_table: | |
cada3c08 RK |
485 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT |
486 | and r0, r6, #255 @ offset bits 23-16 | |
487 | mov r6, r6, lsr #8 @ offset bits 31-24 | |
488 | #else | |
489 | mov r0, #0 @ just in case... | |
490 | #endif | |
dc21af99 RK |
491 | b 3f |
492 | 2: ldr ip, [r7, r3] | |
493 | bic ip, ip, #0x000000ff | |
cada3c08 RK |
494 | tst ip, #0x400 @ rotate shift tells us LS or MS byte |
495 | orrne ip, ip, r6 @ mask in offset bits 31-24 | |
496 | orreq ip, ip, r0 @ mask in offset bits 23-16 | |
dc21af99 RK |
497 | str ip, [r7, r3] |
498 | 3: cmp r4, r5 | |
499 | ldrcc r7, [r4], #4 @ use branch for delay slot | |
500 | bcc 2b | |
501 | mov pc, lr | |
502 | ENDPROC(__fixup_a_pv_table) | |
503 | ||
504 | ENTRY(fixup_pv_table) | |
505 | stmfd sp!, {r4 - r7, lr} | |
506 | ldr r2, 2f @ get address of __pv_phys_offset | |
507 | mov r3, #0 @ no offset | |
508 | mov r4, r0 @ r0 = table start | |
509 | add r5, r0, r1 @ r1 = table size | |
510 | ldr r6, [r2, #4] @ get __pv_offset | |
511 | bl __fixup_a_pv_table | |
512 | ldmfd sp!, {r4 - r7, pc} | |
513 | ENDPROC(fixup_pv_table) | |
514 | ||
515 | .align | |
516 | 2: .long __pv_phys_offset | |
517 | ||
518 | .data | |
519 | .globl __pv_phys_offset | |
520 | .type __pv_phys_offset, %object | |
521 | __pv_phys_offset: | |
522 | .long 0 | |
523 | .size __pv_phys_offset, . - __pv_phys_offset | |
524 | __pv_offset: | |
525 | .long 0 | |
526 | #endif | |
527 | ||
75d90832 | 528 | #include "head-common.S" |