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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/head.S | |
3 | * | |
4 | * Copyright (C) 1994-2002 Russell King | |
e65f38ed RK |
5 | * Copyright (c) 2003 ARM Limited |
6 | * All Rights Reserved | |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Kernel startup code for all 32-bit CPUs | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/linkage.h> |
15 | #include <linux/init.h> | |
16 | ||
17 | #include <asm/assembler.h> | |
18 | #include <asm/domain.h> | |
1da177e4 | 19 | #include <asm/ptrace.h> |
e6ae744d | 20 | #include <asm/asm-offsets.h> |
f09b9979 | 21 | #include <asm/memory.h> |
4f7a1812 | 22 | #include <asm/thread_info.h> |
1da177e4 LT |
23 | #include <asm/system.h> |
24 | ||
c293393f JK |
25 | #ifdef CONFIG_DEBUG_LL |
26 | #include <mach/debug-macro.S> | |
27 | #endif | |
28 | ||
1da177e4 | 29 | /* |
37d07b72 | 30 | * swapper_pg_dir is the virtual address of the initial page table. |
f06b97ff RK |
31 | * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must |
32 | * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect | |
37d07b72 | 33 | * the least significant 16 bits to be 0x8000, but we could probably |
f06b97ff | 34 | * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. |
1da177e4 | 35 | */ |
72a20e22 | 36 | #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) |
f06b97ff RK |
37 | #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 |
38 | #error KERNEL_RAM_VADDR must start at 0xXXXX8000 | |
1da177e4 LT |
39 | #endif |
40 | ||
41 | .globl swapper_pg_dir | |
f06b97ff | 42 | .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 |
1da177e4 | 43 | |
72a20e22 RK |
44 | .macro pgtbl, rd, phys |
45 | add \rd, \phys, #TEXT_OFFSET - 0x4000 | |
1da177e4 | 46 | .endm |
1da177e4 | 47 | |
37d07b72 | 48 | #ifdef CONFIG_XIP_KERNEL |
e98ff7f6 NP |
49 | #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) |
50 | #define KERNEL_END _edata_loc | |
37d07b72 | 51 | #else |
e98ff7f6 NP |
52 | #define KERNEL_START KERNEL_RAM_VADDR |
53 | #define KERNEL_END _end | |
1da177e4 LT |
54 | #endif |
55 | ||
56 | /* | |
57 | * Kernel startup entry point. | |
58 | * --------------------------- | |
59 | * | |
60 | * This is normally called from the decompressor code. The requirements | |
61 | * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, | |
9d20fdd5 | 62 | * r1 = machine nr, r2 = atags pointer. |
1da177e4 LT |
63 | * |
64 | * This code is mostly position independent, so if you link the kernel at | |
65 | * 0xc0008000, you call this at __pa(0xc0008000). | |
66 | * | |
67 | * See linux/arch/arm/tools/mach-types for the complete list of machine | |
68 | * numbers for r1. | |
69 | * | |
70 | * We're trying to keep crap to a minimum; DO NOT add any machine specific | |
71 | * crap here - that's what the boot loader (or in extreme, well justified | |
72 | * circumstances, zImage) is for. | |
73 | */ | |
2abc1c50 | 74 | __HEAD |
1da177e4 | 75 | ENTRY(stext) |
b86040a5 | 76 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode |
1da177e4 | 77 | @ and irqs disabled |
0f44ba1d | 78 | mrc p15, 0, r9, c0, c0 @ get processor id |
1da177e4 LT |
79 | bl __lookup_processor_type @ r5=procinfo r9=cpuid |
80 | movs r10, r5 @ invalid processor (r5=0)? | |
a75e5248 | 81 | THUMB( it eq ) @ force fixup-able long branch encoding |
3c0bdac3 | 82 | beq __error_p @ yes, error 'p' |
0eb0511d | 83 | |
72a20e22 RK |
84 | #ifndef CONFIG_XIP_KERNEL |
85 | adr r3, 2f | |
86 | ldmia r3, {r4, r8} | |
87 | sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) | |
88 | add r8, r8, r4 @ PHYS_OFFSET | |
89 | #else | |
90 | ldr r8, =PLAT_PHYS_OFFSET | |
91 | #endif | |
92 | ||
0eb0511d RK |
93 | /* |
94 | * r1 = machine no, r2 = atags, | |
72a20e22 | 95 | * r8 = phys_offset, r9 = cpuid, r10 = procinfo |
0eb0511d | 96 | */ |
9d20fdd5 | 97 | bl __vet_atags |
f00ec48f RK |
98 | #ifdef CONFIG_SMP_ON_UP |
99 | bl __fixup_smp | |
100 | #endif | |
1da177e4 LT |
101 | bl __create_page_tables |
102 | ||
103 | /* | |
104 | * The following calls CPU specific code in a position independent | |
105 | * manner. See arch/arm/mm/proc-*.S for details. r10 = base of | |
6fc31d54 | 106 | * xxx_proc_info structure selected by __lookup_processor_type |
1da177e4 LT |
107 | * above. On return, the CPU will be ready for the MMU to be |
108 | * turned on, and r0 will hold the CPU control register value. | |
109 | */ | |
a4ae4134 | 110 | ldr r13, =__mmap_switched @ address to jump to after |
1da177e4 | 111 | @ mmu has been enabled |
00945010 | 112 | adr lr, BSYM(1f) @ return (PIC) address |
b86040a5 CM |
113 | ARM( add pc, r10, #PROCINFO_INITFUNC ) |
114 | THUMB( add r12, r10, #PROCINFO_INITFUNC ) | |
115 | THUMB( mov pc, r12 ) | |
00945010 | 116 | 1: b __enable_mmu |
93ed3970 | 117 | ENDPROC(stext) |
a4ae4134 | 118 | .ltorg |
72a20e22 RK |
119 | #ifndef CONFIG_XIP_KERNEL |
120 | 2: .long . | |
121 | .long PAGE_OFFSET | |
122 | #endif | |
1da177e4 LT |
123 | |
124 | /* | |
125 | * Setup the initial page tables. We only setup the barest | |
126 | * amount which are required to get the kernel running, which | |
127 | * generally means mapping in the kernel code. | |
128 | * | |
72a20e22 | 129 | * r8 = phys_offset, r9 = cpuid, r10 = procinfo |
1da177e4 LT |
130 | * |
131 | * Returns: | |
786f1b73 | 132 | * r0, r3, r5-r7 corrupted |
1da177e4 LT |
133 | * r4 = physical page table address |
134 | */ | |
1da177e4 | 135 | __create_page_tables: |
72a20e22 | 136 | pgtbl r4, r8 @ page table address |
1da177e4 LT |
137 | |
138 | /* | |
139 | * Clear the 16K level 1 swapper page table | |
140 | */ | |
141 | mov r0, r4 | |
142 | mov r3, #0 | |
143 | add r6, r0, #0x4000 | |
144 | 1: str r3, [r0], #4 | |
145 | str r3, [r0], #4 | |
146 | str r3, [r0], #4 | |
147 | str r3, [r0], #4 | |
148 | teq r0, r6 | |
149 | bne 1b | |
150 | ||
8799ee9f | 151 | ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags |
1da177e4 LT |
152 | |
153 | /* | |
786f1b73 RK |
154 | * Create identity mapping to cater for __enable_mmu. |
155 | * This identity mapping will be removed by paging_init(). | |
1da177e4 | 156 | */ |
786f1b73 RK |
157 | adr r0, __enable_mmu_loc |
158 | ldmia r0, {r3, r5, r6} | |
159 | sub r0, r0, r3 @ virt->phys offset | |
160 | add r5, r5, r0 @ phys __enable_mmu | |
161 | add r6, r6, r0 @ phys __enable_mmu_end | |
162 | mov r5, r5, lsr #20 | |
163 | mov r6, r6, lsr #20 | |
164 | ||
165 | 1: orr r3, r7, r5, lsl #20 @ flags + kernel base | |
166 | str r3, [r4, r5, lsl #2] @ identity mapping | |
167 | teq r5, r6 | |
168 | addne r5, r5, #1 @ next section | |
169 | bne 1b | |
1da177e4 LT |
170 | |
171 | /* | |
172 | * Now setup the pagetables for our kernel direct | |
2552fc27 | 173 | * mapped region. |
1da177e4 | 174 | */ |
786f1b73 RK |
175 | mov r3, pc |
176 | mov r3, r3, lsr #20 | |
177 | orr r3, r7, r3, lsl #20 | |
e98ff7f6 NP |
178 | add r0, r4, #(KERNEL_START & 0xff000000) >> 18 |
179 | str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! | |
180 | ldr r6, =(KERNEL_END - 1) | |
181 | add r0, r0, #4 | |
182 | add r6, r4, r6, lsr #18 | |
183 | 1: cmp r0, r6 | |
184 | add r3, r3, #1 << 20 | |
185 | strls r3, [r0], #4 | |
186 | bls 1b | |
1da177e4 | 187 | |
ec3622d9 NP |
188 | #ifdef CONFIG_XIP_KERNEL |
189 | /* | |
190 | * Map some ram to cover our .data and .bss areas. | |
191 | */ | |
72a20e22 RK |
192 | add r3, r8, #TEXT_OFFSET |
193 | orr r3, r3, r7 | |
ec3622d9 NP |
194 | add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 |
195 | str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! | |
196 | ldr r6, =(_end - 1) | |
197 | add r0, r0, #4 | |
198 | add r6, r4, r6, lsr #18 | |
199 | 1: cmp r0, r6 | |
200 | add r3, r3, #1 << 20 | |
201 | strls r3, [r0], #4 | |
202 | bls 1b | |
203 | #endif | |
204 | ||
1da177e4 LT |
205 | /* |
206 | * Then map first 1MB of ram in case it contains our boot params. | |
207 | */ | |
f09b9979 | 208 | add r0, r4, #PAGE_OFFSET >> 18 |
72a20e22 | 209 | orr r6, r7, r8 |
1da177e4 LT |
210 | str r6, [r0] |
211 | ||
c77b0427 | 212 | #ifdef CONFIG_DEBUG_LL |
c293393f | 213 | #ifndef CONFIG_DEBUG_ICEDCC |
1da177e4 LT |
214 | /* |
215 | * Map in IO space for serial debugging. | |
216 | * This allows debug messages to be output | |
217 | * via a serial console before paging_init. | |
218 | */ | |
c293393f JK |
219 | addruart r7, r3 |
220 | ||
221 | mov r3, r3, lsr #20 | |
222 | mov r3, r3, lsl #2 | |
223 | ||
1da177e4 LT |
224 | add r0, r4, r3 |
225 | rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) | |
226 | cmp r3, #0x0800 @ limit to 512MB | |
227 | movhi r3, #0x0800 | |
228 | add r6, r0, r3 | |
c293393f JK |
229 | mov r3, r7, lsr #20 |
230 | ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags | |
231 | orr r3, r7, r3, lsl #20 | |
1da177e4 LT |
232 | 1: str r3, [r0], #4 |
233 | add r3, r3, #1 << 20 | |
234 | teq r0, r6 | |
235 | bne 1b | |
c293393f JK |
236 | |
237 | #else /* CONFIG_DEBUG_ICEDCC */ | |
238 | /* we don't need any serial debugging mappings for ICEDCC */ | |
239 | ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags | |
240 | #endif /* !CONFIG_DEBUG_ICEDCC */ | |
241 | ||
1da177e4 LT |
242 | #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) |
243 | /* | |
3c0bdac3 RK |
244 | * If we're using the NetWinder or CATS, we also need to map |
245 | * in the 16550-type serial port for the debug messages | |
1da177e4 | 246 | */ |
c77b0427 RK |
247 | add r0, r4, #0xff000000 >> 18 |
248 | orr r3, r7, #0x7c000000 | |
249 | str r3, [r0] | |
1da177e4 | 250 | #endif |
1da177e4 LT |
251 | #ifdef CONFIG_ARCH_RPC |
252 | /* | |
253 | * Map in screen at 0x02000000 & SCREEN2_BASE | |
254 | * Similar reasons here - for debug. This is | |
255 | * only for Acorn RiscPC architectures. | |
256 | */ | |
c77b0427 RK |
257 | add r0, r4, #0x02000000 >> 18 |
258 | orr r3, r7, #0x02000000 | |
1da177e4 | 259 | str r3, [r0] |
c77b0427 | 260 | add r0, r4, #0xd8000000 >> 18 |
1da177e4 | 261 | str r3, [r0] |
c77b0427 | 262 | #endif |
1da177e4 LT |
263 | #endif |
264 | mov pc, lr | |
93ed3970 | 265 | ENDPROC(__create_page_tables) |
1da177e4 | 266 | .ltorg |
4f79a5dd | 267 | .align |
786f1b73 RK |
268 | __enable_mmu_loc: |
269 | .long . | |
270 | .long __enable_mmu | |
271 | .long __enable_mmu_end | |
1da177e4 | 272 | |
00945010 RK |
273 | #if defined(CONFIG_SMP) |
274 | __CPUINIT | |
275 | ENTRY(secondary_startup) | |
276 | /* | |
277 | * Common entry point for secondary CPUs. | |
278 | * | |
279 | * Ensure that we're in SVC mode, and IRQs are disabled. Lookup | |
280 | * the processor type - there is no need to check the machine type | |
281 | * as it has already been validated by the primary processor. | |
282 | */ | |
283 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 | |
284 | mrc p15, 0, r9, c0, c0 @ get processor id | |
285 | bl __lookup_processor_type | |
286 | movs r10, r5 @ invalid processor? | |
287 | moveq r0, #'p' @ yes, error 'p' | |
a75e5248 | 288 | THUMB( it eq ) @ force fixup-able long branch encoding |
00945010 RK |
289 | beq __error_p |
290 | ||
291 | /* | |
292 | * Use the page tables supplied from __cpu_up. | |
293 | */ | |
294 | adr r4, __secondary_data | |
295 | ldmia r4, {r5, r7, r12} @ address to jump to after | |
296 | sub r4, r4, r5 @ mmu has been enabled | |
297 | ldr r4, [r7, r4] @ get secondary_data.pgdir | |
298 | adr lr, BSYM(__enable_mmu) @ return address | |
299 | mov r13, r12 @ __secondary_switched address | |
300 | ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor | |
301 | @ (return control reg) | |
302 | THUMB( add r12, r10, #PROCINFO_INITFUNC ) | |
303 | THUMB( mov pc, r12 ) | |
304 | ENDPROC(secondary_startup) | |
305 | ||
306 | /* | |
307 | * r6 = &secondary_data | |
308 | */ | |
309 | ENTRY(__secondary_switched) | |
310 | ldr sp, [r7, #4] @ get secondary_data.stack | |
311 | mov fp, #0 | |
312 | b secondary_start_kernel | |
313 | ENDPROC(__secondary_switched) | |
314 | ||
4f79a5dd DM |
315 | .align |
316 | ||
00945010 RK |
317 | .type __secondary_data, %object |
318 | __secondary_data: | |
319 | .long . | |
320 | .long secondary_data | |
321 | .long __secondary_switched | |
322 | #endif /* defined(CONFIG_SMP) */ | |
323 | ||
324 | ||
325 | ||
326 | /* | |
327 | * Setup common bits before finally enabling the MMU. Essentially | |
328 | * this is just loading the page table pointer and domain access | |
329 | * registers. | |
865a4fae RK |
330 | * |
331 | * r0 = cp#15 control register | |
332 | * r1 = machine ID | |
333 | * r2 = atags pointer | |
334 | * r4 = page table pointer | |
335 | * r9 = processor ID | |
336 | * r13 = *virtual* address to jump to upon completion | |
00945010 RK |
337 | */ |
338 | __enable_mmu: | |
339 | #ifdef CONFIG_ALIGNMENT_TRAP | |
340 | orr r0, r0, #CR_A | |
341 | #else | |
342 | bic r0, r0, #CR_A | |
343 | #endif | |
344 | #ifdef CONFIG_CPU_DCACHE_DISABLE | |
345 | bic r0, r0, #CR_C | |
346 | #endif | |
347 | #ifdef CONFIG_CPU_BPREDICT_DISABLE | |
348 | bic r0, r0, #CR_Z | |
349 | #endif | |
350 | #ifdef CONFIG_CPU_ICACHE_DISABLE | |
351 | bic r0, r0, #CR_I | |
352 | #endif | |
353 | mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ | |
354 | domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ | |
355 | domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ | |
356 | domain_val(DOMAIN_IO, DOMAIN_CLIENT)) | |
357 | mcr p15, 0, r5, c3, c0, 0 @ load domain access register | |
358 | mcr p15, 0, r4, c2, c0, 0 @ load page table pointer | |
359 | b __turn_mmu_on | |
360 | ENDPROC(__enable_mmu) | |
361 | ||
362 | /* | |
363 | * Enable the MMU. This completely changes the structure of the visible | |
364 | * memory space. You will not be able to trace execution through this. | |
365 | * If you have an enquiry about this, *please* check the linux-arm-kernel | |
366 | * mailing list archives BEFORE sending another post to the list. | |
367 | * | |
368 | * r0 = cp#15 control register | |
865a4fae RK |
369 | * r1 = machine ID |
370 | * r2 = atags pointer | |
371 | * r9 = processor ID | |
00945010 RK |
372 | * r13 = *virtual* address to jump to upon completion |
373 | * | |
374 | * other registers depend on the function called upon completion | |
375 | */ | |
376 | .align 5 | |
377 | __turn_mmu_on: | |
378 | mov r0, r0 | |
379 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
380 | mrc p15, 0, r3, c0, c0, 0 @ read id reg | |
381 | mov r3, r3 | |
382 | mov r3, r13 | |
383 | mov pc, r3 | |
384 | __enable_mmu_end: | |
385 | ENDPROC(__turn_mmu_on) | |
386 | ||
1da177e4 | 387 | |
f00ec48f RK |
388 | #ifdef CONFIG_SMP_ON_UP |
389 | __fixup_smp: | |
e98ff0f5 RK |
390 | and r3, r9, #0x000f0000 @ architecture version |
391 | teq r3, #0x000f0000 @ CPU ID supported? | |
f00ec48f RK |
392 | bne __fixup_smp_on_up @ no, assume UP |
393 | ||
e98ff0f5 RK |
394 | bic r3, r9, #0x00ff0000 |
395 | bic r3, r3, #0x0000000f @ mask 0xff00fff0 | |
396 | mov r4, #0x41000000 | |
0eb0511d | 397 | orr r4, r4, #0x0000b000 |
e98ff0f5 RK |
398 | orr r4, r4, #0x00000020 @ val 0x4100b020 |
399 | teq r3, r4 @ ARM 11MPCore? | |
f00ec48f RK |
400 | moveq pc, lr @ yes, assume SMP |
401 | ||
402 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR | |
e98ff0f5 RK |
403 | and r0, r0, #0xc0000000 @ multiprocessing extensions and |
404 | teq r0, #0x80000000 @ not part of a uniprocessor system? | |
405 | moveq pc, lr @ yes, assume SMP | |
f00ec48f RK |
406 | |
407 | __fixup_smp_on_up: | |
408 | adr r0, 1f | |
0eb0511d | 409 | ldmia r0, {r3 - r5} |
f00ec48f | 410 | sub r3, r0, r3 |
0eb0511d RK |
411 | add r4, r4, r3 |
412 | add r5, r5, r3 | |
413 | 2: cmp r4, r5 | |
ed3768a8 | 414 | movhs pc, lr |
0eb0511d | 415 | ldmia r4!, {r0, r6} |
ed3768a8 DM |
416 | ARM( str r6, [r0, r3] ) |
417 | THUMB( add r0, r0, r3 ) | |
418 | #ifdef __ARMEB__ | |
419 | THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. | |
420 | #endif | |
421 | THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords | |
422 | THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. | |
423 | THUMB( strh r6, [r0] ) | |
424 | b 2b | |
f00ec48f RK |
425 | ENDPROC(__fixup_smp) |
426 | ||
4f79a5dd | 427 | .align |
f00ec48f RK |
428 | 1: .word . |
429 | .word __smpalt_begin | |
430 | .word __smpalt_end | |
431 | ||
432 | .pushsection .data | |
433 | .globl smp_on_up | |
434 | smp_on_up: | |
435 | ALT_SMP(.long 1) | |
436 | ALT_UP(.long 0) | |
437 | .popsection | |
438 | ||
439 | #endif | |
440 | ||
75d90832 | 441 | #include "head-common.S" |