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80c59daf DM |
1 | /* |
2 | * Copyright (c) 2012 Linaro Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/linkage.h> | |
21 | #include <asm/assembler.h> | |
22 | #include <asm/virt.h> | |
23 | ||
424e5994 | 24 | #ifndef ZIMAGE |
80c59daf DM |
25 | /* |
26 | * For the kernel proper, we need to find out the CPU boot mode long after | |
27 | * boot, so we need to store it in a writable variable. | |
28 | * | |
29 | * This is not in .bss, because we set it sufficiently early that the boot-time | |
30 | * zeroing of .bss would clobber it. | |
31 | */ | |
32 | .data | |
33 | ENTRY(__boot_cpu_mode) | |
34 | .long 0 | |
35 | .text | |
36 | ||
37 | /* | |
38 | * Save the primary CPU boot mode. Requires 3 scratch registers. | |
39 | */ | |
40 | .macro store_primary_cpu_mode reg1, reg2, reg3 | |
41 | mrs \reg1, cpsr | |
42 | and \reg1, \reg1, #MODE_MASK | |
43 | adr \reg2, .L__boot_cpu_mode_offset | |
44 | ldr \reg3, [\reg2] | |
45 | str \reg1, [\reg2, \reg3] | |
46 | .endm | |
47 | ||
48 | /* | |
49 | * Compare the current mode with the one saved on the primary CPU. | |
50 | * If they don't match, record that fact. The Z bit indicates | |
51 | * if there's a match or not. | |
52 | * Requires 3 additionnal scratch registers. | |
53 | */ | |
54 | .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3 | |
55 | adr \reg2, .L__boot_cpu_mode_offset | |
56 | ldr \reg3, [\reg2] | |
57 | ldr \reg1, [\reg2, \reg3] | |
58 | cmp \mode, \reg1 @ matches primary CPU boot mode? | |
b60d5db6 MR |
59 | orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH |
60 | strne \reg1, [\reg2, \reg3] @ record what happened and give up | |
80c59daf DM |
61 | .endm |
62 | ||
424e5994 DM |
63 | #else /* ZIMAGE */ |
64 | ||
65 | .macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req | |
66 | .endm | |
67 | ||
68 | /* | |
69 | * The zImage loader only runs on one CPU, so we don't bother with mult-CPU | |
70 | * consistency checking: | |
71 | */ | |
72 | .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3 | |
73 | cmp \mode, \mode | |
74 | .endm | |
75 | ||
76 | #endif /* ZIMAGE */ | |
77 | ||
80c59daf DM |
78 | /* |
79 | * Hypervisor stub installation functions. | |
80 | * | |
81 | * These must be called with the MMU and D-cache off. | |
82 | * They are not ABI compliant and are only intended to be called from the kernel | |
83 | * entry points in head.S. | |
84 | */ | |
85 | @ Call this from the primary CPU | |
86 | ENTRY(__hyp_stub_install) | |
87 | store_primary_cpu_mode r4, r5, r6 | |
88 | ENDPROC(__hyp_stub_install) | |
89 | ||
90 | @ fall through... | |
91 | ||
92 | @ Secondary CPUs should call here | |
93 | ENTRY(__hyp_stub_install_secondary) | |
94 | mrs r4, cpsr | |
95 | and r4, r4, #MODE_MASK | |
96 | ||
97 | /* | |
98 | * If the secondary has booted with a different mode, give up | |
99 | * immediately. | |
100 | */ | |
101 | compare_cpu_mode_with_primary r4, r5, r6, r7 | |
6ebbf2ce | 102 | retne lr |
80c59daf DM |
103 | |
104 | /* | |
105 | * Once we have given up on one CPU, we do not try to install the | |
106 | * stub hypervisor on the remaining ones: because the saved boot mode | |
107 | * is modified, it can't compare equal to the CPSR mode field any | |
108 | * more. | |
109 | * | |
110 | * Otherwise... | |
111 | */ | |
112 | ||
113 | cmp r4, #HYP_MODE | |
6ebbf2ce | 114 | retne lr @ give up if the CPU is not in HYP mode |
80c59daf DM |
115 | |
116 | /* | |
117 | * Configure HSCTLR to set correct exception endianness/instruction set | |
118 | * state etc. | |
119 | * Turn off all traps | |
120 | * Eventually, CPU-specific code might be needed -- assume not for now | |
121 | * | |
122 | * This code relies on the "eret" instruction to synchronize the | |
d0172347 MZ |
123 | * various coprocessor accesses. This is done when we switch to SVC |
124 | * (see safe_svcmode_maskall). | |
80c59daf DM |
125 | */ |
126 | @ Now install the hypervisor stub: | |
127 | adr r7, __hyp_stub_vectors | |
128 | mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR) | |
129 | ||
130 | @ Disable all traps, so we don't get any nasty surprise | |
131 | mov r7, #0 | |
132 | mcr p15, 4, r7, c1, c1, 0 @ HCR | |
133 | mcr p15, 4, r7, c1, c1, 2 @ HCPTR | |
134 | mcr p15, 4, r7, c1, c1, 3 @ HSTR | |
135 | ||
136 | THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE | |
137 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
138 | orr r7, #(1 << 9) @ HSCTLR.EE | |
139 | #endif | |
140 | mcr p15, 4, r7, c1, c0, 0 @ HSCTLR | |
141 | ||
142 | mrc p15, 4, r7, c1, c1, 1 @ HDCR | |
143 | and r7, #0x1f @ Preserve HPMN | |
144 | mcr p15, 4, r7, c1, c1, 1 @ HDCR | |
145 | ||
8ec58be9 MZ |
146 | #if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER) |
147 | @ make CNTP_* and CNTPCT accessible from PL1 | |
148 | mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 | |
149 | lsr r7, #16 | |
150 | and r7, #0xf | |
151 | cmp r7, #1 | |
152 | bne 1f | |
153 | mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL | |
154 | orr r7, r7, #3 @ PL1PCEN | PL1PCTEN | |
155 | mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL | |
0af0b189 MZ |
156 | mov r7, #0 |
157 | mcrr p15, 4, r7, r7, c14 @ CNTVOFF | |
3f71be23 MZ |
158 | |
159 | @ Disable virtual timer in case it was counting | |
160 | mrc p15, 0, r7, c14, c3, 1 @ CNTV_CTL | |
161 | bic r7, #1 @ Clear ENABLE | |
162 | mcr p15, 0, r7, c14, c3, 1 @ CNTV_CTL | |
8ec58be9 MZ |
163 | 1: |
164 | #endif | |
165 | ||
d0172347 | 166 | bx lr @ The boot CPU mode is left in r4. |
80c59daf DM |
167 | ENDPROC(__hyp_stub_install_secondary) |
168 | ||
169 | __hyp_stub_do_trap: | |
170 | cmp r0, #-1 | |
171 | mrceq p15, 4, r0, c12, c0, 0 @ get HVBAR | |
172 | mcrne p15, 4, r0, c12, c0, 0 @ set HVBAR | |
173 | __ERET | |
174 | ENDPROC(__hyp_stub_do_trap) | |
175 | ||
176 | /* | |
177 | * __hyp_set_vectors: Call this after boot to set the initial hypervisor | |
178 | * vectors as part of hypervisor installation. On an SMP system, this should | |
179 | * be called on each CPU. | |
180 | * | |
181 | * r0 must be the physical address of the new vector table (which must lie in | |
182 | * the bottom 4GB of physical address space. | |
183 | * | |
184 | * r0 must be 32-byte aligned. | |
185 | * | |
186 | * Before calling this, you must check that the stub hypervisor is installed | |
187 | * everywhere, by waiting for any secondary CPUs to be brought up and then | |
188 | * checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true. | |
189 | * | |
190 | * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or | |
191 | * something else went wrong... in such cases, trying to install a new | |
192 | * hypervisor is unlikely to work as desired. | |
193 | * | |
194 | * When you call into your shiny new hypervisor, sp_hyp will contain junk, | |
195 | * so you will need to set that to something sensible at the new hypervisor's | |
196 | * initialisation entry point. | |
197 | */ | |
198 | ENTRY(__hyp_get_vectors) | |
199 | mov r0, #-1 | |
200 | ENDPROC(__hyp_get_vectors) | |
201 | @ fall through | |
202 | ENTRY(__hyp_set_vectors) | |
203 | __HVC(0) | |
6ebbf2ce | 204 | ret lr |
80c59daf DM |
205 | ENDPROC(__hyp_set_vectors) |
206 | ||
424e5994 | 207 | #ifndef ZIMAGE |
80c59daf DM |
208 | .align 2 |
209 | .L__boot_cpu_mode_offset: | |
210 | .long __boot_cpu_mode - . | |
424e5994 | 211 | #endif |
80c59daf DM |
212 | |
213 | .align 5 | |
214 | __hyp_stub_vectors: | |
215 | __hyp_stub_reset: W(b) . | |
216 | __hyp_stub_und: W(b) . | |
217 | __hyp_stub_svc: W(b) . | |
218 | __hyp_stub_pabort: W(b) . | |
219 | __hyp_stub_dabort: W(b) . | |
220 | __hyp_stub_trap: W(b) __hyp_stub_do_trap | |
221 | __hyp_stub_irq: W(b) . | |
222 | __hyp_stub_fiq: W(b) . | |
223 | ENDPROC(__hyp_stub_vectors) | |
224 |