[deliverable/linux.git] / arch / arm / kernel / kprobes-thumb.c

/*
 * arch/arm/kernel/kprobes-thumb.c
 *
 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/kprobes.h>

#include "kprobes.h"


/*
 * True if current instruction is in an IT block.
 */
#define in_it_block(cpsr)	((cpsr & 0x06000c00) != 0x00000000)

/*
 * Return the condition code to check for the currently executing instruction.
 * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
 * in_it_block returns true.
 */
#define current_cond(cpsr)	((cpsr >> 12) & 0xf)

/*
 * Return the PC value for a probe in thumb code.
 * This is the address of the probed instruction plus 4.
 * We subtract one because the address will have bit zero set to indicate
 * a pointer to thumb code.
 */
static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p)
{
	return (unsigned long)p->addr - 1 + 4;
}

static void __kprobes
t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
{
	kprobe_opcode_t insn = p->opcode;
	unsigned long pc = thumb_probe_pc(p);
	int rm = (insn >> 3) & 0xf;
	unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];

	if (insn & (1 << 7)) /* BLX ? */
		regs->ARM_lr = (unsigned long)p->addr + 2;

	bx_write_pc(rmv, regs);
}

static void __kprobes
t16_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
{
	kprobe_opcode_t insn = p->opcode;
	unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3);
	long index = insn & 0xff;
	int rt = (insn >> 8) & 0x7;
	regs->uregs[rt] = base[index];
}

static void __kprobes
t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs)
{
	kprobe_opcode_t insn = p->opcode;
	unsigned long* base = (unsigned long *)regs->ARM_sp;
	long index = insn & 0xff;
	int rt = (insn >> 8) & 0x7;
	if (insn & 0x800) /* LDR */
		regs->uregs[rt] = base[index];
	else /* STR */
		base[index] = regs->uregs[rt];
}

static void __kprobes
t16_simulate_reladr(struct kprobe *p, struct pt_regs *regs)
{
	kprobe_opcode_t insn = p->opcode;
	unsigned long base = (insn & 0x800) ? regs->ARM_sp
					    : (thumb_probe_pc(p) & ~3);
	long offset = insn & 0xff;
	int rt = (insn >> 8) & 0x7;
	regs->uregs[rt] = base + offset * 4;
}

static void __kprobes
t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs)
{
	kprobe_opcode_t insn = p->opcode;
	long imm = insn & 0x7f;
	if (insn & 0x80) /* SUB */
		regs->ARM_sp -= imm * 4;
	else /* ADD */
		regs->ARM_sp += imm * 4;
}

static void __kprobes
t16_simulate_cbz(struct kprobe *p, struct pt_regs *regs)
{
	kprobe_opcode_t insn = p->opcode;
	int rn = insn & 0x7;
	kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
	if (nonzero & 0x800) {
		long i = insn & 0x200;
		long imm5 = insn & 0xf8;
		unsigned long pc = thumb_probe_pc(p);
		regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
	}
}

static unsigned long __kprobes
t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
{
	unsigned long oldcpsr = regs->ARM_cpsr;
	unsigned long newcpsr;

	__asm__ __volatile__ (
		"msr	cpsr_fs, %[oldcpsr]	\n\t"
		"ldmia	%[regs], {r0-r7}	\n\t"
		"blx	%[fn]			\n\t"
		"stmia	%[regs], {r0-r7}	\n\t"
		"mrs	%[newcpsr], cpsr	\n\t"
		: [newcpsr] "=r" (newcpsr)
		: [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
		  [fn] "r" (p->ainsn.insn_fn)
		: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
		  "lr", "memory", "cc"
		);

	return (oldcpsr & ~APSR_MASK) | (newcpsr & APSR_MASK);
}

static void __kprobes
t16_emulate_loregs_rwflags(struct kprobe *p, struct pt_regs *regs)
{
	regs->ARM_cpsr = t16_emulate_loregs(p, regs);
}

static void __kprobes
t16_emulate_loregs_noitrwflags(struct kprobe *p, struct pt_regs *regs)
{
	unsigned long cpsr = t16_emulate_loregs(p, regs);
	if (!in_it_block(cpsr))
		regs->ARM_cpsr = cpsr;
}

static void __kprobes
t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
{
	kprobe_opcode_t insn = p->opcode;
	unsigned long pc = thumb_probe_pc(p);
	int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
	int rm = (insn >> 3) & 0xf;

	register unsigned long rdnv asm("r1");
	register unsigned long rmv asm("r0");
	unsigned long cpsr = regs->ARM_cpsr;

	rdnv = (rdn == 15) ? pc : regs->uregs[rdn];
	rmv = (rm == 15) ? pc : regs->uregs[rm];

	__asm__ __volatile__ (
		"msr	cpsr_fs, %[cpsr]	\n\t"
		"blx    %[fn]			\n\t"
		"mrs	%[cpsr], cpsr		\n\t"
		: "=r" (rdnv), [cpsr] "=r" (cpsr)
		: "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
		: "lr", "memory", "cc"
	);

	if (rdn == 15)
		rdnv &= ~1;

	regs->uregs[rdn] = rdnv;
	regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
}

static enum kprobe_insn __kprobes
t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi)
{
	insn &= ~0x00ff;
	insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
	((u16 *)asi->insn)[0] = insn;
	asi->insn_handler = t16_emulate_hiregs;
	return INSN_GOOD;
}

static const union decode_item t16_table_1011[] = {
	/* Miscellaneous 16-bit instructions		    */

	/* ADD (SP plus immediate)	1011 0000 0xxx xxxx */
	/* SUB (SP minus immediate)	1011 0000 1xxx xxxx */
	DECODE_SIMULATE	(0xff00, 0xb000, t16_simulate_add_sp_imm),

	/* CBZ				1011 00x1 xxxx xxxx */
	/* CBNZ				1011 10x1 xxxx xxxx */
	DECODE_SIMULATE	(0xf500, 0xb100, t16_simulate_cbz),

	/* SXTH				1011 0010 00xx xxxx */
	/* SXTB				1011 0010 01xx xxxx */
	/* UXTH				1011 0010 10xx xxxx */
	/* UXTB				1011 0010 11xx xxxx */
	/* REV				1011 1010 00xx xxxx */
	/* REV16			1011 1010 01xx xxxx */
	/* ???				1011 1010 10xx xxxx */
	/* REVSH			1011 1010 11xx xxxx */
	DECODE_REJECT	(0xffc0, 0xba80),
	DECODE_EMULATE	(0xf500, 0xb000, t16_emulate_loregs_rwflags),

	/*
	 * If-Then, and hints
	 *				1011 1111 xxxx xxxx
	 */

	/* YIELD			1011 1111 0001 0000 */
	DECODE_OR	(0xffff, 0xbf10),
	/* SEV				1011 1111 0100 0000 */
	DECODE_EMULATE	(0xffff, 0xbf40, kprobe_emulate_none),
	/* NOP				1011 1111 0000 0000 */
	/* WFE				1011 1111 0010 0000 */
	/* WFI				1011 1111 0011 0000 */
	DECODE_SIMULATE	(0xffcf, 0xbf00, kprobe_simulate_nop),
	/* Unassigned hints		1011 1111 xxxx 0000 */
	DECODE_REJECT	(0xff0f, 0xbf00),

	DECODE_END
};

const union decode_item kprobe_decode_thumb16_table[] = {

	/*
	 * Shift (immediate), add, subtract, move, and compare
	 *				00xx xxxx xxxx xxxx
	 */

	/* CMP (immediate)		0010 1xxx xxxx xxxx */
	DECODE_EMULATE	(0xf800, 0x2800, t16_emulate_loregs_rwflags),

	/* ADD (register)		0001 100x xxxx xxxx */
	/* SUB (register)		0001 101x xxxx xxxx */
	/* LSL (immediate)		0000 0xxx xxxx xxxx */
	/* LSR (immediate)		0000 1xxx xxxx xxxx */
	/* ASR (immediate)		0001 0xxx xxxx xxxx */
	/* ADD (immediate, Thumb)	0001 110x xxxx xxxx */
	/* SUB (immediate, Thumb)	0001 111x xxxx xxxx */
	/* MOV (immediate)		0010 0xxx xxxx xxxx */
	/* ADD (immediate, Thumb)	0011 0xxx xxxx xxxx */
	/* SUB (immediate, Thumb)	0011 1xxx xxxx xxxx */
	DECODE_EMULATE	(0xc000, 0x0000, t16_emulate_loregs_noitrwflags),

	/*
	 * 16-bit Thumb data-processing instructions
	 *				0100 00xx xxxx xxxx
	 */

	/* TST (register)		0100 0010 00xx xxxx */
	DECODE_EMULATE	(0xffc0, 0x4200, t16_emulate_loregs_rwflags),
	/* CMP (register)		0100 0010 10xx xxxx */
	/* CMN (register)		0100 0010 11xx xxxx */
	DECODE_EMULATE	(0xff80, 0x4280, t16_emulate_loregs_rwflags),
	/* AND (register)		0100 0000 00xx xxxx */
	/* EOR (register)		0100 0000 01xx xxxx */
	/* LSL (register)		0100 0000 10xx xxxx */
	/* LSR (register)		0100 0000 11xx xxxx */
	/* ASR (register)		0100 0001 00xx xxxx */
	/* ADC (register)		0100 0001 01xx xxxx */
	/* SBC (register)		0100 0001 10xx xxxx */
	/* ROR (register)		0100 0001 11xx xxxx */
	/* RSB (immediate)		0100 0010 01xx xxxx */
	/* ORR (register)		0100 0011 00xx xxxx */
	/* MUL				0100 0011 00xx xxxx */
	/* BIC (register)		0100 0011 10xx xxxx */
	/* MVN (register)		0100 0011 10xx xxxx */
	DECODE_EMULATE	(0xfc00, 0x4000, t16_emulate_loregs_noitrwflags),

	/*
	 * Special data instructions and branch and exchange
	 *				0100 01xx xxxx xxxx
	 */

	/* BLX pc			0100 0111 1111 1xxx */
	DECODE_REJECT	(0xfff8, 0x47f8),

	/* BX (register)		0100 0111 0xxx xxxx */
	/* BLX (register)		0100 0111 1xxx xxxx */
	DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx),

	/* ADD pc, pc			0100 0100 1111 1111 */
	DECODE_REJECT	(0xffff, 0x44ff),

	/* ADD (register)		0100 0100 xxxx xxxx */
	/* CMP (register)		0100 0101 xxxx xxxx */
	/* MOV (register)		0100 0110 xxxx xxxx */
	DECODE_CUSTOM	(0xfc00, 0x4400, t16_decode_hiregs),

	/*
	 * Load from Literal Pool
	 * LDR (literal)		0100 1xxx xxxx xxxx
	 */
	DECODE_SIMULATE	(0xf800, 0x4800, t16_simulate_ldr_literal),

	/*
	 * 16-bit Thumb Load/store instructions
	 *				0101 xxxx xxxx xxxx
	 *				011x xxxx xxxx xxxx
	 *				100x xxxx xxxx xxxx
	 */

	/* STR (register)		0101 000x xxxx xxxx */
	/* STRH (register)		0101 001x xxxx xxxx */
	/* STRB (register)		0101 010x xxxx xxxx */
	/* LDRSB (register)		0101 011x xxxx xxxx */
	/* LDR (register)		0101 100x xxxx xxxx */
	/* LDRH (register)		0101 101x xxxx xxxx */
	/* LDRB (register)		0101 110x xxxx xxxx */
	/* LDRSH (register)		0101 111x xxxx xxxx */
	/* STR (immediate, Thumb)	0110 0xxx xxxx xxxx */
	/* LDR (immediate, Thumb)	0110 1xxx xxxx xxxx */
	/* STRB (immediate, Thumb)	0111 0xxx xxxx xxxx */
	/* LDRB (immediate, Thumb)	0111 1xxx xxxx xxxx */
	DECODE_EMULATE	(0xc000, 0x4000, t16_emulate_loregs_rwflags),
	/* STRH (immediate, Thumb)	1000 0xxx xxxx xxxx */
	/* LDRH (immediate, Thumb)	1000 1xxx xxxx xxxx */
	DECODE_EMULATE	(0xf000, 0x8000, t16_emulate_loregs_rwflags),
	/* STR (immediate, Thumb)	1001 0xxx xxxx xxxx */
	/* LDR (immediate, Thumb)	1001 1xxx xxxx xxxx */
	DECODE_SIMULATE	(0xf000, 0x9000, t16_simulate_ldrstr_sp_relative),

	/*
	 * Generate PC-/SP-relative address
	 * ADR (literal)		1010 0xxx xxxx xxxx
	 * ADD (SP plus immediate)	1010 1xxx xxxx xxxx
	 */
	DECODE_SIMULATE	(0xf000, 0xa000, t16_simulate_reladr),

	/*
	 * Miscellaneous 16-bit instructions
	 *				1011 xxxx xxxx xxxx
	 */
	DECODE_TABLE	(0xf000, 0xb000, t16_table_1011),

	/* STM				1100 0xxx xxxx xxxx */
	/* LDM				1100 1xxx xxxx xxxx */
	DECODE_EMULATE	(0xf000, 0xc000, t16_emulate_loregs_rwflags),

	DECODE_END
};

static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
{
	if (unlikely(in_it_block(cpsr)))
		return kprobe_condition_checks[current_cond(cpsr)](cpsr);
	return true;
}

static void __kprobes thumb16_singlestep(struct kprobe *p, struct pt_regs *regs)
{
	regs->ARM_pc += 2;
	p->ainsn.insn_handler(p, regs);
	regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
}

static void __kprobes thumb32_singlestep(struct kprobe *p, struct pt_regs *regs)
{
	regs->ARM_pc += 4;
	p->ainsn.insn_handler(p, regs);
	regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
}

enum kprobe_insn __kprobes
thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
{
	asi->insn_singlestep = thumb16_singlestep;
	asi->insn_check_cc = thumb_check_cc;
	return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true);
}

enum kprobe_insn __kprobes
thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
{
	asi->insn_singlestep = thumb32_singlestep;
	asi->insn_check_cc = thumb_check_cc;
	return INSN_REJECTED;
}
Commit	Line	Data
24371707 JM	1	/*
	2	* arch/arm/kernel/kprobes-thumb.c
	3	*
	4	* Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/kprobes.h>
	13
	14	#include "kprobes.h"
	15
eaf4f33f JM	16
	17	/*
	18	* True if current instruction is in an IT block.
	19	*/
	20	#define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000)
	21
	22	/*
	23	* Return the condition code to check for the currently executing instruction.
	24	* This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
	25	* in_it_block returns true.
	26	*/
	27	#define current_cond(cpsr) ((cpsr >> 12) & 0xf)
	28
a9c3c29e JM	29	/*
	30	* Return the PC value for a probe in thumb code.
	31	* This is the address of the probed instruction plus 4.
	32	* We subtract one because the address will have bit zero set to indicate
	33	* a pointer to thumb code.
	34	*/
	35	static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p)
	36	{
	37	return (unsigned long)p->addr - 1 + 4;
	38	}
	39
	40	static void __kprobes
	41	t16_simulate_bxblx(struct kprobe p, struct pt_regs regs)
	42	{
	43	kprobe_opcode_t insn = p->opcode;
	44	unsigned long pc = thumb_probe_pc(p);
	45	int rm = (insn >> 3) & 0xf;
	46	unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];
	47
	48	if (insn & (1 << 7)) /* BLX ? */
	49	regs->ARM_lr = (unsigned long)p->addr + 2;
	50
	51	bx_write_pc(rmv, regs);
	52	}
	53
f8695142 JM	54	static void __kprobes
	55	t16_simulate_ldr_literal(struct kprobe p, struct pt_regs regs)
	56	{
	57	kprobe_opcode_t insn = p->opcode;
	58	unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3);
	59	long index = insn & 0xff;
	60	int rt = (insn >> 8) & 0x7;
	61	regs->uregs[rt] = base[index];
	62	}
	63
	64	static void __kprobes
	65	t16_simulate_ldrstr_sp_relative(struct kprobe p, struct pt_regs regs)
	66	{
	67	kprobe_opcode_t insn = p->opcode;
	68	unsigned long* base = (unsigned long *)regs->ARM_sp;
	69	long index = insn & 0xff;
	70	int rt = (insn >> 8) & 0x7;
	71	if (insn & 0x800) /* LDR */
	72	regs->uregs[rt] = base[index];
	73	else /* STR */
	74	base[index] = regs->uregs[rt];
	75	}
	76
2f335829 JM	77	static void __kprobes
	78	t16_simulate_reladr(struct kprobe p, struct pt_regs regs)
	79	{
	80	kprobe_opcode_t insn = p->opcode;
	81	unsigned long base = (insn & 0x800) ? regs->ARM_sp
	82	: (thumb_probe_pc(p) & ~3);
	83	long offset = insn & 0xff;
	84	int rt = (insn >> 8) & 0x7;
	85	regs->uregs[rt] = base + offset * 4;
	86	}
	87
	88	static void __kprobes
	89	t16_simulate_add_sp_imm(struct kprobe p, struct pt_regs regs)
	90	{
	91	kprobe_opcode_t insn = p->opcode;
	92	long imm = insn & 0x7f;
	93	if (insn & 0x80) /* SUB */
	94	regs->ARM_sp -= imm * 4;
	95	else /* ADD */
	96	regs->ARM_sp += imm * 4;
	97	}
	98
32818f31 JM	99	static void __kprobes
	100	t16_simulate_cbz(struct kprobe p, struct pt_regs regs)
	101	{
	102	kprobe_opcode_t insn = p->opcode;
	103	int rn = insn & 0x7;
	104	kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
	105	if (nonzero & 0x800) {
	106	long i = insn & 0x200;
	107	long imm5 = insn & 0xf8;
	108	unsigned long pc = thumb_probe_pc(p);
	109	regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
	110	}
	111	}
	112
02d194f6 JM	113	static unsigned long __kprobes
	114	t16_emulate_loregs(struct kprobe p, struct pt_regs regs)
	115	{
	116	unsigned long oldcpsr = regs->ARM_cpsr;
	117	unsigned long newcpsr;
	118
	119	__asm__ __volatile__ (
	120	"msr cpsr_fs, %[oldcpsr] \n\t"
	121	"ldmia %[regs], {r0-r7} \n\t"
	122	"blx %[fn] \n\t"
	123	"stmia %[regs], {r0-r7} \n\t"
	124	"mrs %[newcpsr], cpsr \n\t"
	125	: [newcpsr] "=r" (newcpsr)
	126	: [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
	127	[fn] "r" (p->ainsn.insn_fn)
	128	: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
	129	"lr", "memory", "cc"
	130	);
	131
	132	return (oldcpsr & ~APSR_MASK) \| (newcpsr & APSR_MASK);
	133	}
	134
	135	static void __kprobes
	136	t16_emulate_loregs_rwflags(struct kprobe p, struct pt_regs regs)
	137	{
	138	regs->ARM_cpsr = t16_emulate_loregs(p, regs);
	139	}
	140
	141	static void __kprobes
	142	t16_emulate_loregs_noitrwflags(struct kprobe p, struct pt_regs regs)
	143	{
	144	unsigned long cpsr = t16_emulate_loregs(p, regs);
	145	if (!in_it_block(cpsr))
	146	regs->ARM_cpsr = cpsr;
	147	}
	148
3b5940e8 JM	149	static void __kprobes
	150	t16_emulate_hiregs(struct kprobe p, struct pt_regs regs)
	151	{
	152	kprobe_opcode_t insn = p->opcode;
	153	unsigned long pc = thumb_probe_pc(p);
	154	int rdn = (insn & 0x7) \| ((insn & 0x80) >> 4);
	155	int rm = (insn >> 3) & 0xf;
	156
	157	register unsigned long rdnv asm("r1");
	158	register unsigned long rmv asm("r0");
	159	unsigned long cpsr = regs->ARM_cpsr;
	160
	161	rdnv = (rdn == 15) ? pc : regs->uregs[rdn];
	162	rmv = (rm == 15) ? pc : regs->uregs[rm];
	163
	164	__asm__ __volatile__ (
	165	"msr cpsr_fs, %[cpsr] \n\t"
	166	"blx %[fn] \n\t"
	167	"mrs %[cpsr], cpsr \n\t"
	168	: "=r" (rdnv), [cpsr] "=r" (cpsr)
	169	: "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
	170	: "lr", "memory", "cc"
	171	);
	172
	173	if (rdn == 15)
	174	rdnv &= ~1;
	175
	176	regs->uregs[rdn] = rdnv;
	177	regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) \| (cpsr & APSR_MASK);
	178	}
	179
	180	static enum kprobe_insn __kprobes
	181	t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi)
	182	{
	183	insn &= ~0x00ff;
	184	insn \|= 0x001; /* Set Rdn = R1 and Rm = R0 */
	185	((u16 *)asi->insn)[0] = insn;
	186	asi->insn_handler = t16_emulate_hiregs;
	187	return INSN_GOOD;
	188	}
	189
3f92dfed JM	190	static const union decode_item t16_table_1011[] = {
	191	/* Miscellaneous 16-bit instructions */
	192
2f335829 JM	193	/* ADD (SP plus immediate) 1011 0000 0xxx xxxx */
	194	/* SUB (SP minus immediate) 1011 0000 1xxx xxxx */
	195	DECODE_SIMULATE (0xff00, 0xb000, t16_simulate_add_sp_imm),
	196
32818f31 JM	197	/* CBZ 1011 00x1 xxxx xxxx */
	198	/* CBNZ 1011 10x1 xxxx xxxx */
	199	DECODE_SIMULATE (0xf500, 0xb100, t16_simulate_cbz),
	200
	201	/* SXTH 1011 0010 00xx xxxx */
	202	/* SXTB 1011 0010 01xx xxxx */
	203	/* UXTH 1011 0010 10xx xxxx */
	204	/* UXTB 1011 0010 11xx xxxx */
	205	/* REV 1011 1010 00xx xxxx */
	206	/* REV16 1011 1010 01xx xxxx */
	207	/* ??? 1011 1010 10xx xxxx */
	208	/* REVSH 1011 1010 11xx xxxx */
	209	DECODE_REJECT (0xffc0, 0xba80),
	210	DECODE_EMULATE (0xf500, 0xb000, t16_emulate_loregs_rwflags),
	211
3f92dfed JM	212	/*
	213	* If-Then, and hints
	214	* 1011 1111 xxxx xxxx
	215	*/
	216
	217	/* YIELD 1011 1111 0001 0000 */
	218	DECODE_OR (0xffff, 0xbf10),
	219	/* SEV 1011 1111 0100 0000 */
	220	DECODE_EMULATE (0xffff, 0xbf40, kprobe_emulate_none),
	221	/* NOP 1011 1111 0000 0000 */
	222	/* WFE 1011 1111 0010 0000 */
	223	/* WFI 1011 1111 0011 0000 */
	224	DECODE_SIMULATE (0xffcf, 0xbf00, kprobe_simulate_nop),
	225	/* Unassigned hints 1011 1111 xxxx 0000 */
	226	DECODE_REJECT (0xff0f, 0xbf00),
	227
	228	DECODE_END
	229	};
	230
	231	const union decode_item kprobe_decode_thumb16_table[] = {
	232
02d194f6 JM	233	/*
	234	* Shift (immediate), add, subtract, move, and compare
	235	* 00xx xxxx xxxx xxxx
	236	*/
	237
	238	/* CMP (immediate) 0010 1xxx xxxx xxxx */
	239	DECODE_EMULATE (0xf800, 0x2800, t16_emulate_loregs_rwflags),
	240
	241	/* ADD (register) 0001 100x xxxx xxxx */
	242	/* SUB (register) 0001 101x xxxx xxxx */
	243	/* LSL (immediate) 0000 0xxx xxxx xxxx */
	244	/* LSR (immediate) 0000 1xxx xxxx xxxx */
	245	/* ASR (immediate) 0001 0xxx xxxx xxxx */
	246	/* ADD (immediate, Thumb) 0001 110x xxxx xxxx */
	247	/* SUB (immediate, Thumb) 0001 111x xxxx xxxx */
	248	/* MOV (immediate) 0010 0xxx xxxx xxxx */
	249	/* ADD (immediate, Thumb) 0011 0xxx xxxx xxxx */
	250	/* SUB (immediate, Thumb) 0011 1xxx xxxx xxxx */
	251	DECODE_EMULATE (0xc000, 0x0000, t16_emulate_loregs_noitrwflags),
	252
	253	/*
	254	* 16-bit Thumb data-processing instructions
	255	* 0100 00xx xxxx xxxx
	256	*/
	257
	258	/* TST (register) 0100 0010 00xx xxxx */
	259	DECODE_EMULATE (0xffc0, 0x4200, t16_emulate_loregs_rwflags),
	260	/* CMP (register) 0100 0010 10xx xxxx */
	261	/* CMN (register) 0100 0010 11xx xxxx */
	262	DECODE_EMULATE (0xff80, 0x4280, t16_emulate_loregs_rwflags),
	263	/* AND (register) 0100 0000 00xx xxxx */
	264	/* EOR (register) 0100 0000 01xx xxxx */
	265	/* LSL (register) 0100 0000 10xx xxxx */
	266	/* LSR (register) 0100 0000 11xx xxxx */
	267	/* ASR (register) 0100 0001 00xx xxxx */
	268	/* ADC (register) 0100 0001 01xx xxxx */
	269	/* SBC (register) 0100 0001 10xx xxxx */
	270	/* ROR (register) 0100 0001 11xx xxxx */
	271	/* RSB (immediate) 0100 0010 01xx xxxx */
	272	/* ORR (register) 0100 0011 00xx xxxx */
	273	/* MUL 0100 0011 00xx xxxx */
	274	/* BIC (register) 0100 0011 10xx xxxx */
	275	/* MVN (register) 0100 0011 10xx xxxx */
	276	DECODE_EMULATE (0xfc00, 0x4000, t16_emulate_loregs_noitrwflags),
	277
a9c3c29e JM	278	/*
	279	* Special data instructions and branch and exchange
	280	* 0100 01xx xxxx xxxx
	281	*/
	282
	283	/* BLX pc 0100 0111 1111 1xxx */
	284	DECODE_REJECT (0xfff8, 0x47f8),
	285
	286	/* BX (register) 0100 0111 0xxx xxxx */
	287	/* BLX (register) 0100 0111 1xxx xxxx */
	288	DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx),
	289
3b5940e8 JM	290	/* ADD pc, pc 0100 0100 1111 1111 */
	291	DECODE_REJECT (0xffff, 0x44ff),
	292
	293	/* ADD (register) 0100 0100 xxxx xxxx */
	294	/* CMP (register) 0100 0101 xxxx xxxx */
	295	/* MOV (register) 0100 0110 xxxx xxxx */
	296	DECODE_CUSTOM (0xfc00, 0x4400, t16_decode_hiregs),
	297
f8695142 JM	298	/*
	299	* Load from Literal Pool
	300	* LDR (literal) 0100 1xxx xxxx xxxx
	301	*/
	302	DECODE_SIMULATE (0xf800, 0x4800, t16_simulate_ldr_literal),
	303
	304	/*
	305	* 16-bit Thumb Load/store instructions
	306	* 0101 xxxx xxxx xxxx
	307	* 011x xxxx xxxx xxxx
	308	* 100x xxxx xxxx xxxx
	309	*/
	310
	311	/* STR (register) 0101 000x xxxx xxxx */
	312	/* STRH (register) 0101 001x xxxx xxxx */
	313	/* STRB (register) 0101 010x xxxx xxxx */
	314	/* LDRSB (register) 0101 011x xxxx xxxx */
	315	/* LDR (register) 0101 100x xxxx xxxx */
	316	/* LDRH (register) 0101 101x xxxx xxxx */
	317	/* LDRB (register) 0101 110x xxxx xxxx */
	318	/* LDRSH (register) 0101 111x xxxx xxxx */
	319	/* STR (immediate, Thumb) 0110 0xxx xxxx xxxx */
	320	/* LDR (immediate, Thumb) 0110 1xxx xxxx xxxx */
	321	/* STRB (immediate, Thumb) 0111 0xxx xxxx xxxx */
	322	/* LDRB (immediate, Thumb) 0111 1xxx xxxx xxxx */
	323	DECODE_EMULATE (0xc000, 0x4000, t16_emulate_loregs_rwflags),
	324	/* STRH (immediate, Thumb) 1000 0xxx xxxx xxxx */
	325	/* LDRH (immediate, Thumb) 1000 1xxx xxxx xxxx */
	326	DECODE_EMULATE (0xf000, 0x8000, t16_emulate_loregs_rwflags),
	327	/* STR (immediate, Thumb) 1001 0xxx xxxx xxxx */
	328	/* LDR (immediate, Thumb) 1001 1xxx xxxx xxxx */
	329	DECODE_SIMULATE (0xf000, 0x9000, t16_simulate_ldrstr_sp_relative),
	330
2f335829 JM	331	/*
	332	* Generate PC-/SP-relative address
	333	* ADR (literal) 1010 0xxx xxxx xxxx
	334	* ADD (SP plus immediate) 1010 1xxx xxxx xxxx
	335	*/
	336	DECODE_SIMULATE (0xf000, 0xa000, t16_simulate_reladr),
	337
3f92dfed JM	338	/*
	339	* Miscellaneous 16-bit instructions
	340	* 1011 xxxx xxxx xxxx
	341	*/
	342	DECODE_TABLE (0xf000, 0xb000, t16_table_1011),
	343
f8695142 JM	344	/* STM 1100 0xxx xxxx xxxx */
	345	/* LDM 1100 1xxx xxxx xxxx */
	346	DECODE_EMULATE (0xf000, 0xc000, t16_emulate_loregs_rwflags),
	347
3f92dfed JM	348	DECODE_END
	349	};
	350
eaf4f33f JM	351	static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
	352	{
	353	if (unlikely(in_it_block(cpsr)))
	354	return kprobe_condition_checks[current_cond(cpsr)](cpsr);
	355	return true;
	356	}
	357
c6a7d97d JM	358	static void __kprobes thumb16_singlestep(struct kprobe p, struct pt_regs regs)
	359	{
	360	regs->ARM_pc += 2;
	361	p->ainsn.insn_handler(p, regs);
	362	regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
	363	}
	364
	365	static void __kprobes thumb32_singlestep(struct kprobe p, struct pt_regs regs)
	366	{
	367	regs->ARM_pc += 4;
	368	p->ainsn.insn_handler(p, regs);
	369	regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
	370	}
	371
24371707 JM	372	enum kprobe_insn __kprobes
	373	thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
	374	{
c6a7d97d	375	asi->insn_singlestep = thumb16_singlestep;
eaf4f33f	376	asi->insn_check_cc = thumb_check_cc;
3f92dfed	377	return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true);
24371707 JM	378	}
	379
	380	enum kprobe_insn __kprobes
	381	thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
	382	{
c6a7d97d	383	asi->insn_singlestep = thumb32_singlestep;
eaf4f33f	384	asi->insn_check_cc = thumb_check_cc;
24371707 JM	385	return INSN_REJECTED;
24371707 JM	386	}