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ARM: kprobes: Decode 32-bit Thumb table branch instructions
[deliverable/linux.git] / arch / arm / kernel / kprobes-thumb.c
CommitLineData
24371707
JM		 1/*
2 * arch/arm/kernel/kprobes-thumb.c
3 *
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/kprobes.h>
13
14#include "kprobes.h"
15
eaf4f33f
JM		 16
17/*
18 * True if current instruction is in an IT block.
19 */
20#define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000)
21
22/*
23 * Return the condition code to check for the currently executing instruction.
24 * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
25 * in_it_block returns true.
26 */
27#define current_cond(cpsr) ((cpsr >> 12) & 0xf)
28
a9c3c29e
JM		 29/*
30 * Return the PC value for a probe in thumb code.
31 * This is the address of the probed instruction plus 4.
32 * We subtract one because the address will have bit zero set to indicate
33 * a pointer to thumb code.
34 */
35static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p)
36{
37 return (unsigned long)p->addr - 1 + 4;
38}
39
dd212bd3
JM		 40static void __kprobes
41t32_simulate_table_branch(struct kprobe *p, struct pt_regs *regs)
42{
43 kprobe_opcode_t insn = p->opcode;
44 unsigned long pc = thumb_probe_pc(p);
45 int rn = (insn >> 16) & 0xf;
46 int rm = insn & 0xf;
47
48 unsigned long rnv = (rn == 15) ? pc : regs->uregs[rn];
49 unsigned long rmv = regs->uregs[rm];
50 unsigned int halfwords;
51
52 if (insn & 0x10)
53 halfwords = ((u16 *)rnv)[rmv];
54 else
55 halfwords = ((u8 *)rnv)[rmv];
56
57 regs->ARM_pc = pc + 2 * halfwords;
58}
59
eaf1d065
JM		 60static enum kprobe_insn __kprobes
61t32_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
62{
63 enum kprobe_insn ret = kprobe_decode_ldmstm(insn, asi);
64
65 /* Fixup modified instruction to have halfwords in correct order...*/
66 insn = asi->insn[0];
67 ((u16 *)asi->insn)[0] = insn >> 16;
68 ((u16 *)asi->insn)[1] = insn & 0xffff;
69
70 return ret;
71}
72
b48354d3
JM		 73static void __kprobes
74t32_emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
75{
76 kprobe_opcode_t insn = p->opcode;
77 unsigned long pc = thumb_probe_pc(p) & ~3;
78 int rt1 = (insn >> 12) & 0xf;
79 int rt2 = (insn >> 8) & 0xf;
80 int rn = (insn >> 16) & 0xf;
81
82 register unsigned long rt1v asm("r0") = regs->uregs[rt1];
83 register unsigned long rt2v asm("r1") = regs->uregs[rt2];
84 register unsigned long rnv asm("r2") = (rn == 15) ? pc
85 : regs->uregs[rn];
86
87 __asm__ __volatile__ (
88 "blx %[fn]"
89 : "=r" (rt1v), "=r" (rt2v), "=r" (rnv)
90 : "0" (rt1v), "1" (rt2v), "2" (rnv), [fn] "r" (p->ainsn.insn_fn)
91 : "lr", "memory", "cc"
92 );
93
94 if (rn != 15)
95 regs->uregs[rn] = rnv; /* Writeback base register */
96 regs->uregs[rt1] = rt1v;
97 regs->uregs[rt2] = rt2v;
98}
99
eaf1d065
JM		 100static const union decode_item t32_table_1110_100x_x0xx[] = {
101 /* Load/store multiple instructions */
102
103 /* Rn is PC 1110 100x x0xx 1111 xxxx xxxx xxxx xxxx */
104 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
105
106 /* SRS 1110 1000 00x0 xxxx xxxx xxxx xxxx xxxx */
107 /* RFE 1110 1000 00x1 xxxx xxxx xxxx xxxx xxxx */
108 DECODE_REJECT (0xffc00000, 0xe8000000),
109 /* SRS 1110 1001 10x0 xxxx xxxx xxxx xxxx xxxx */
110 /* RFE 1110 1001 10x1 xxxx xxxx xxxx xxxx xxxx */
111 DECODE_REJECT (0xffc00000, 0xe9800000),
112
113 /* STM Rn, {...pc} 1110 100x x0x0 xxxx 1xxx xxxx xxxx xxxx */
114 DECODE_REJECT (0xfe508000, 0xe8008000),
115 /* LDM Rn, {...lr,pc} 1110 100x x0x1 xxxx 11xx xxxx xxxx xxxx */
116 DECODE_REJECT (0xfe50c000, 0xe810c000),
117 /* LDM/STM Rn, {...sp} 1110 100x x0xx xxxx xx1x xxxx xxxx xxxx */
118 DECODE_REJECT (0xfe402000, 0xe8002000),
119
120 /* STMIA 1110 1000 10x0 xxxx xxxx xxxx xxxx xxxx */
121 /* LDMIA 1110 1000 10x1 xxxx xxxx xxxx xxxx xxxx */
122 /* STMDB 1110 1001 00x0 xxxx xxxx xxxx xxxx xxxx */
123 /* LDMDB 1110 1001 00x1 xxxx xxxx xxxx xxxx xxxx */
124 DECODE_CUSTOM (0xfe400000, 0xe8000000, t32_decode_ldmstm),
125
126 DECODE_END
127};
128
b48354d3
JM		 129static const union decode_item t32_table_1110_100x_x1xx[] = {
130 /* Load/store dual, load/store exclusive, table branch */
131
132 /* STRD (immediate) 1110 1000 x110 xxxx xxxx xxxx xxxx xxxx */
133 /* LDRD (immediate) 1110 1000 x111 xxxx xxxx xxxx xxxx xxxx */
134 DECODE_OR (0xff600000, 0xe8600000),
135 /* STRD (immediate) 1110 1001 x1x0 xxxx xxxx xxxx xxxx xxxx */
136 /* LDRD (immediate) 1110 1001 x1x1 xxxx xxxx xxxx xxxx xxxx */
137 DECODE_EMULATEX (0xff400000, 0xe9400000, t32_emulate_ldrdstrd,
138 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
139
dd212bd3
JM		 140 /* TBB 1110 1000 1101 xxxx xxxx xxxx 0000 xxxx */
141 /* TBH 1110 1000 1101 xxxx xxxx xxxx 0001 xxxx */
142 DECODE_SIMULATEX(0xfff000e0, 0xe8d00000, t32_simulate_table_branch,
143 REGS(NOSP, 0, 0, 0, NOSPPC)),
144
b48354d3
JM		 145 /* STREX 1110 1000 0100 xxxx xxxx xxxx xxxx xxxx */
146 /* LDREX 1110 1000 0101 xxxx xxxx xxxx xxxx xxxx */
147 /* STREXB 1110 1000 1100 xxxx xxxx xxxx 0100 xxxx */
148 /* STREXH 1110 1000 1100 xxxx xxxx xxxx 0101 xxxx */
149 /* STREXD 1110 1000 1100 xxxx xxxx xxxx 0111 xxxx */
150 /* LDREXB 1110 1000 1101 xxxx xxxx xxxx 0100 xxxx */
151 /* LDREXH 1110 1000 1101 xxxx xxxx xxxx 0101 xxxx */
152 /* LDREXD 1110 1000 1101 xxxx xxxx xxxx 0111 xxxx */
153 /* And unallocated instructions... */
154 DECODE_END
155};
156
f39ca8b4
JM		 157static const union decode_item t32_table_1111_0xxx___1[] = {
158 /* Branches and miscellaneous control */
159
160 /* YIELD 1111 0011 1010 xxxx 10x0 x000 0000 0001 */
161 DECODE_OR (0xfff0d7ff, 0xf3a08001),
162 /* SEV 1111 0011 1010 xxxx 10x0 x000 0000 0100 */
163 DECODE_EMULATE (0xfff0d7ff, 0xf3a08004, kprobe_emulate_none),
164 /* NOP 1111 0011 1010 xxxx 10x0 x000 0000 0000 */
165 /* WFE 1111 0011 1010 xxxx 10x0 x000 0000 0010 */
166 /* WFI 1111 0011 1010 xxxx 10x0 x000 0000 0011 */
167 DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, kprobe_simulate_nop),
168
169 DECODE_END
170};
171
172const union decode_item kprobe_decode_thumb32_table[] = {
173
eaf1d065
JM		 174 /*
175 * Load/store multiple instructions
176 * 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx
177 */
178 DECODE_TABLE (0xfe400000, 0xe8000000, t32_table_1110_100x_x0xx),
179
b48354d3
JM		 180 /*
181 * Load/store dual, load/store exclusive, table branch
182 * 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx
183 */
184 DECODE_TABLE (0xfe400000, 0xe8400000, t32_table_1110_100x_x1xx),
185
f39ca8b4
JM		 186 /*
187 * Branches and miscellaneous control
188 * 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx
189 */
190 DECODE_TABLE (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1),
191
192 DECODE_END
193};
194
a9c3c29e
JM		 195static void __kprobes
196t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
197{
198 kprobe_opcode_t insn = p->opcode;
199 unsigned long pc = thumb_probe_pc(p);
200 int rm = (insn >> 3) & 0xf;
201 unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];
202
203 if (insn & (1 << 7)) /* BLX ? */
204 regs->ARM_lr = (unsigned long)p->addr + 2;
205
206 bx_write_pc(rmv, regs);
207}
208
f8695142
JM		 209static void __kprobes
210t16_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
211{
212 kprobe_opcode_t insn = p->opcode;
213 unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3);
214 long index = insn & 0xff;
215 int rt = (insn >> 8) & 0x7;
216 regs->uregs[rt] = base[index];
217}
218
219static void __kprobes
220t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs)
221{
222 kprobe_opcode_t insn = p->opcode;
223 unsigned long* base = (unsigned long *)regs->ARM_sp;
224 long index = insn & 0xff;
225 int rt = (insn >> 8) & 0x7;
226 if (insn & 0x800) /* LDR */
227 regs->uregs[rt] = base[index];
228 else /* STR */
229 base[index] = regs->uregs[rt];
230}
231
2f335829
JM		 232static void __kprobes
233t16_simulate_reladr(struct kprobe *p, struct pt_regs *regs)
234{
235 kprobe_opcode_t insn = p->opcode;
236 unsigned long base = (insn & 0x800) ? regs->ARM_sp
237 : (thumb_probe_pc(p) & ~3);
238 long offset = insn & 0xff;
239 int rt = (insn >> 8) & 0x7;
240 regs->uregs[rt] = base + offset * 4;
241}
242
243static void __kprobes
244t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs)
245{
246 kprobe_opcode_t insn = p->opcode;
247 long imm = insn & 0x7f;
248 if (insn & 0x80) /* SUB */
249 regs->ARM_sp -= imm * 4;
250 else /* ADD */
251 regs->ARM_sp += imm * 4;
252}
253
32818f31
JM		 254static void __kprobes
255t16_simulate_cbz(struct kprobe *p, struct pt_regs *regs)
256{
257 kprobe_opcode_t insn = p->opcode;
258 int rn = insn & 0x7;
259 kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
260 if (nonzero & 0x800) {
261 long i = insn & 0x200;
262 long imm5 = insn & 0xf8;
263 unsigned long pc = thumb_probe_pc(p);
264 regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
265 }
266}
267
5b94faf8
JM		 268static void __kprobes
269t16_simulate_it(struct kprobe *p, struct pt_regs *regs)
270{
271 /*
272 * The 8 IT state bits are split into two parts in CPSR:
273 * ITSTATE<1:0> are in CPSR<26:25>
274 * ITSTATE<7:2> are in CPSR<15:10>
275 * The new IT state is in the lower byte of insn.
276 */
277 kprobe_opcode_t insn = p->opcode;
278 unsigned long cpsr = regs->ARM_cpsr;
279 cpsr &= ~PSR_IT_MASK;
280 cpsr |= (insn & 0xfc) << 8;
281 cpsr |= (insn & 0x03) << 25;
282 regs->ARM_cpsr = cpsr;
283}
284
285static void __kprobes
286t16_singlestep_it(struct kprobe *p, struct pt_regs *regs)
287{
288 regs->ARM_pc += 2;
289 t16_simulate_it(p, regs);
290}
291
292static enum kprobe_insn __kprobes
293t16_decode_it(kprobe_opcode_t insn, struct arch_specific_insn *asi)
294{
295 asi->insn_singlestep = t16_singlestep_it;
296 return INSN_GOOD_NO_SLOT;
297}
298
396b41f6
JM		 299static void __kprobes
300t16_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
301{
302 kprobe_opcode_t insn = p->opcode;
303 unsigned long pc = thumb_probe_pc(p);
304 long offset = insn & 0x7f;
305 offset -= insn & 0x80; /* Apply sign bit */
306 regs->ARM_pc = pc + (offset * 2);
307}
308
309static enum kprobe_insn __kprobes
310t16_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
311{
312 int cc = (insn >> 8) & 0xf;
313 asi->insn_check_cc = kprobe_condition_checks[cc];
314 asi->insn_handler = t16_simulate_cond_branch;
315 return INSN_GOOD_NO_SLOT;
316}
317
318static void __kprobes
319t16_simulate_branch(struct kprobe *p, struct pt_regs *regs)
320{
321 kprobe_opcode_t insn = p->opcode;
322 unsigned long pc = thumb_probe_pc(p);
323 long offset = insn & 0x3ff;
324 offset -= insn & 0x400; /* Apply sign bit */
325 regs->ARM_pc = pc + (offset * 2);
326}
327
02d194f6
JM		 328static unsigned long __kprobes
329t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
330{
331 unsigned long oldcpsr = regs->ARM_cpsr;
332 unsigned long newcpsr;
333
334 __asm__ __volatile__ (
335 "msr cpsr_fs, %[oldcpsr] \n\t"
336 "ldmia %[regs], {r0-r7} \n\t"
337 "blx %[fn] \n\t"
338 "stmia %[regs], {r0-r7} \n\t"
339 "mrs %[newcpsr], cpsr \n\t"
340 : [newcpsr] "=r" (newcpsr)
341 : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
342 [fn] "r" (p->ainsn.insn_fn)
343 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
344 "lr", "memory", "cc"
345 );
346
347 return (oldcpsr & ~APSR_MASK) | (newcpsr & APSR_MASK);
348}
349
350static void __kprobes
351t16_emulate_loregs_rwflags(struct kprobe *p, struct pt_regs *regs)
352{
353 regs->ARM_cpsr = t16_emulate_loregs(p, regs);
354}
355
356static void __kprobes
357t16_emulate_loregs_noitrwflags(struct kprobe *p, struct pt_regs *regs)
358{
359 unsigned long cpsr = t16_emulate_loregs(p, regs);
360 if (!in_it_block(cpsr))
361 regs->ARM_cpsr = cpsr;
362}
363
3b5940e8
JM		 364static void __kprobes
365t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
366{
367 kprobe_opcode_t insn = p->opcode;
368 unsigned long pc = thumb_probe_pc(p);
369 int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
370 int rm = (insn >> 3) & 0xf;
371
372 register unsigned long rdnv asm("r1");
373 register unsigned long rmv asm("r0");
374 unsigned long cpsr = regs->ARM_cpsr;
375
376 rdnv = (rdn == 15) ? pc : regs->uregs[rdn];
377 rmv = (rm == 15) ? pc : regs->uregs[rm];
378
379 __asm__ __volatile__ (
380 "msr cpsr_fs, %[cpsr] \n\t"
381 "blx %[fn] \n\t"
382 "mrs %[cpsr], cpsr \n\t"
383 : "=r" (rdnv), [cpsr] "=r" (cpsr)
384 : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
385 : "lr", "memory", "cc"
386 );
387
388 if (rdn == 15)
389 rdnv &= ~1;
390
391 regs->uregs[rdn] = rdnv;
392 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
393}
394
395static enum kprobe_insn __kprobes
396t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi)
397{
398 insn &= ~0x00ff;
399 insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
400 ((u16 *)asi->insn)[0] = insn;
401 asi->insn_handler = t16_emulate_hiregs;
402 return INSN_GOOD;
403}
404
fd0c8d8a
JM		 405static void __kprobes
406t16_emulate_push(struct kprobe *p, struct pt_regs *regs)
407{
408 __asm__ __volatile__ (
409 "ldr r9, [%[regs], #13*4] \n\t"
410 "ldr r8, [%[regs], #14*4] \n\t"
411 "ldmia %[regs], {r0-r7} \n\t"
412 "blx %[fn] \n\t"
413 "str r9, [%[regs], #13*4] \n\t"
414 :
415 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
416 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
417 "lr", "memory", "cc"
418 );
419}
420
421static enum kprobe_insn __kprobes
422t16_decode_push(kprobe_opcode_t insn, struct arch_specific_insn *asi)
423{
424 /*
425 * To simulate a PUSH we use a Thumb-2 "STMDB R9!, {registers}"
426 * and call it with R9=SP and LR in the register list represented
427 * by R8.
428 */
429 ((u16 *)asi->insn)[0] = 0xe929; /* 1st half STMDB R9!,{} */
430 ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
431 asi->insn_handler = t16_emulate_push;
432 return INSN_GOOD;
433}
434
435static void __kprobes
436t16_emulate_pop_nopc(struct kprobe *p, struct pt_regs *regs)
437{
438 __asm__ __volatile__ (
439 "ldr r9, [%[regs], #13*4] \n\t"
440 "ldmia %[regs], {r0-r7} \n\t"
441 "blx %[fn] \n\t"
442 "stmia %[regs], {r0-r7} \n\t"
443 "str r9, [%[regs], #13*4] \n\t"
444 :
445 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
446 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
447 "lr", "memory", "cc"
448 );
449}
450
451static void __kprobes
452t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
453{
454 register unsigned long pc asm("r8");
455
456 __asm__ __volatile__ (
457 "ldr r9, [%[regs], #13*4] \n\t"
458 "ldmia %[regs], {r0-r7} \n\t"
459 "blx %[fn] \n\t"
460 "stmia %[regs], {r0-r7} \n\t"
461 "str r9, [%[regs], #13*4] \n\t"
462 : "=r" (pc)
463 : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
464 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
465 "lr", "memory", "cc"
466 );
467
468 bx_write_pc(pc, regs);
469}
470
471static enum kprobe_insn __kprobes
472t16_decode_pop(kprobe_opcode_t insn, struct arch_specific_insn *asi)
473{
474 /*
475 * To simulate a POP we use a Thumb-2 "LDMDB R9!, {registers}"
476 * and call it with R9=SP and PC in the register list represented
477 * by R8.
478 */
479 ((u16 *)asi->insn)[0] = 0xe8b9; /* 1st half LDMIA R9!,{} */
480 ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
481 asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc
482 : t16_emulate_pop_nopc;
483 return INSN_GOOD;
484}
485
3f92dfed
JM		 486static const union decode_item t16_table_1011[] = {
487 /* Miscellaneous 16-bit instructions */
488
2f335829
JM		 489 /* ADD (SP plus immediate) 1011 0000 0xxx xxxx */
490 /* SUB (SP minus immediate) 1011 0000 1xxx xxxx */
491 DECODE_SIMULATE (0xff00, 0xb000, t16_simulate_add_sp_imm),
492
32818f31
JM		 493 /* CBZ 1011 00x1 xxxx xxxx */
494 /* CBNZ 1011 10x1 xxxx xxxx */
495 DECODE_SIMULATE (0xf500, 0xb100, t16_simulate_cbz),
496
497 /* SXTH 1011 0010 00xx xxxx */
498 /* SXTB 1011 0010 01xx xxxx */
499 /* UXTH 1011 0010 10xx xxxx */
500 /* UXTB 1011 0010 11xx xxxx */
501 /* REV 1011 1010 00xx xxxx */
502 /* REV16 1011 1010 01xx xxxx */
503 /* ??? 1011 1010 10xx xxxx */
504 /* REVSH 1011 1010 11xx xxxx */
505 DECODE_REJECT (0xffc0, 0xba80),
506 DECODE_EMULATE (0xf500, 0xb000, t16_emulate_loregs_rwflags),
507
fd0c8d8a
JM		 508 /* PUSH 1011 010x xxxx xxxx */
509 DECODE_CUSTOM (0xfe00, 0xb400, t16_decode_push),
510 /* POP 1011 110x xxxx xxxx */
511 DECODE_CUSTOM (0xfe00, 0xbc00, t16_decode_pop),
512
3f92dfed
JM		 513 /*
514 * If-Then, and hints
515 * 1011 1111 xxxx xxxx
516 */
517
518 /* YIELD 1011 1111 0001 0000 */
519 DECODE_OR (0xffff, 0xbf10),
520 /* SEV 1011 1111 0100 0000 */
521 DECODE_EMULATE (0xffff, 0xbf40, kprobe_emulate_none),
522 /* NOP 1011 1111 0000 0000 */
523 /* WFE 1011 1111 0010 0000 */
524 /* WFI 1011 1111 0011 0000 */
525 DECODE_SIMULATE (0xffcf, 0xbf00, kprobe_simulate_nop),
526 /* Unassigned hints 1011 1111 xxxx 0000 */
527 DECODE_REJECT (0xff0f, 0xbf00),
5b94faf8
JM		 528 /* IT 1011 1111 xxxx xxxx */
529 DECODE_CUSTOM (0xff00, 0xbf00, t16_decode_it),
3f92dfed 530
0a188ccb
JM		 531 /* SETEND 1011 0110 010x xxxx */
532 /* CPS 1011 0110 011x xxxx */
533 /* BKPT 1011 1110 xxxx xxxx */
534 /* And unallocated instructions... */
3f92dfed
JM		 535 DECODE_END
536};
537
538const union decode_item kprobe_decode_thumb16_table[] = {
539
02d194f6
JM		 540 /*
541 * Shift (immediate), add, subtract, move, and compare
542 * 00xx xxxx xxxx xxxx
543 */
544
545 /* CMP (immediate) 0010 1xxx xxxx xxxx */
546 DECODE_EMULATE (0xf800, 0x2800, t16_emulate_loregs_rwflags),
547
548 /* ADD (register) 0001 100x xxxx xxxx */
549 /* SUB (register) 0001 101x xxxx xxxx */
550 /* LSL (immediate) 0000 0xxx xxxx xxxx */
551 /* LSR (immediate) 0000 1xxx xxxx xxxx */
552 /* ASR (immediate) 0001 0xxx xxxx xxxx */
553 /* ADD (immediate, Thumb) 0001 110x xxxx xxxx */
554 /* SUB (immediate, Thumb) 0001 111x xxxx xxxx */
555 /* MOV (immediate) 0010 0xxx xxxx xxxx */
556 /* ADD (immediate, Thumb) 0011 0xxx xxxx xxxx */
557 /* SUB (immediate, Thumb) 0011 1xxx xxxx xxxx */
558 DECODE_EMULATE (0xc000, 0x0000, t16_emulate_loregs_noitrwflags),
559
560 /*
561 * 16-bit Thumb data-processing instructions
562 * 0100 00xx xxxx xxxx
563 */
564
565 /* TST (register) 0100 0010 00xx xxxx */
566 DECODE_EMULATE (0xffc0, 0x4200, t16_emulate_loregs_rwflags),
567 /* CMP (register) 0100 0010 10xx xxxx */
568 /* CMN (register) 0100 0010 11xx xxxx */
569 DECODE_EMULATE (0xff80, 0x4280, t16_emulate_loregs_rwflags),
570 /* AND (register) 0100 0000 00xx xxxx */
571 /* EOR (register) 0100 0000 01xx xxxx */
572 /* LSL (register) 0100 0000 10xx xxxx */
573 /* LSR (register) 0100 0000 11xx xxxx */
574 /* ASR (register) 0100 0001 00xx xxxx */
575 /* ADC (register) 0100 0001 01xx xxxx */
576 /* SBC (register) 0100 0001 10xx xxxx */
577 /* ROR (register) 0100 0001 11xx xxxx */
578 /* RSB (immediate) 0100 0010 01xx xxxx */
579 /* ORR (register) 0100 0011 00xx xxxx */
580 /* MUL 0100 0011 00xx xxxx */
581 /* BIC (register) 0100 0011 10xx xxxx */
582 /* MVN (register) 0100 0011 10xx xxxx */
583 DECODE_EMULATE (0xfc00, 0x4000, t16_emulate_loregs_noitrwflags),
584
a9c3c29e
JM		 585 /*
586 * Special data instructions and branch and exchange
587 * 0100 01xx xxxx xxxx
588 */
589
590 /* BLX pc 0100 0111 1111 1xxx */
591 DECODE_REJECT (0xfff8, 0x47f8),
592
593 /* BX (register) 0100 0111 0xxx xxxx */
594 /* BLX (register) 0100 0111 1xxx xxxx */
595 DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx),
596
3b5940e8
JM		 597 /* ADD pc, pc 0100 0100 1111 1111 */
598 DECODE_REJECT (0xffff, 0x44ff),
599
600 /* ADD (register) 0100 0100 xxxx xxxx */
601 /* CMP (register) 0100 0101 xxxx xxxx */
602 /* MOV (register) 0100 0110 xxxx xxxx */
603 DECODE_CUSTOM (0xfc00, 0x4400, t16_decode_hiregs),
604
f8695142
JM		 605 /*
606 * Load from Literal Pool
607 * LDR (literal) 0100 1xxx xxxx xxxx
608 */
609 DECODE_SIMULATE (0xf800, 0x4800, t16_simulate_ldr_literal),
610
611 /*
612 * 16-bit Thumb Load/store instructions
613 * 0101 xxxx xxxx xxxx
614 * 011x xxxx xxxx xxxx
615 * 100x xxxx xxxx xxxx
616 */
617
618 /* STR (register) 0101 000x xxxx xxxx */
619 /* STRH (register) 0101 001x xxxx xxxx */
620 /* STRB (register) 0101 010x xxxx xxxx */
621 /* LDRSB (register) 0101 011x xxxx xxxx */
622 /* LDR (register) 0101 100x xxxx xxxx */
623 /* LDRH (register) 0101 101x xxxx xxxx */
624 /* LDRB (register) 0101 110x xxxx xxxx */
625 /* LDRSH (register) 0101 111x xxxx xxxx */
626 /* STR (immediate, Thumb) 0110 0xxx xxxx xxxx */
627 /* LDR (immediate, Thumb) 0110 1xxx xxxx xxxx */
628 /* STRB (immediate, Thumb) 0111 0xxx xxxx xxxx */
629 /* LDRB (immediate, Thumb) 0111 1xxx xxxx xxxx */
630 DECODE_EMULATE (0xc000, 0x4000, t16_emulate_loregs_rwflags),
631 /* STRH (immediate, Thumb) 1000 0xxx xxxx xxxx */
632 /* LDRH (immediate, Thumb) 1000 1xxx xxxx xxxx */
633 DECODE_EMULATE (0xf000, 0x8000, t16_emulate_loregs_rwflags),
634 /* STR (immediate, Thumb) 1001 0xxx xxxx xxxx */
635 /* LDR (immediate, Thumb) 1001 1xxx xxxx xxxx */
636 DECODE_SIMULATE (0xf000, 0x9000, t16_simulate_ldrstr_sp_relative),
637
2f335829
JM		 638 /*
639 * Generate PC-/SP-relative address
640 * ADR (literal) 1010 0xxx xxxx xxxx
641 * ADD (SP plus immediate) 1010 1xxx xxxx xxxx
642 */
643 DECODE_SIMULATE (0xf000, 0xa000, t16_simulate_reladr),
644
3f92dfed
JM		 645 /*
646 * Miscellaneous 16-bit instructions
647 * 1011 xxxx xxxx xxxx
648 */
649 DECODE_TABLE (0xf000, 0xb000, t16_table_1011),
650
f8695142
JM		 651 /* STM 1100 0xxx xxxx xxxx */
652 /* LDM 1100 1xxx xxxx xxxx */
653 DECODE_EMULATE (0xf000, 0xc000, t16_emulate_loregs_rwflags),
654
44495667
JM		 655 /*
656 * Conditional branch, and Supervisor Call
657 */
658
659 /* Permanently UNDEFINED 1101 1110 xxxx xxxx */
660 /* SVC 1101 1111 xxxx xxxx */
661 DECODE_REJECT (0xfe00, 0xde00),
662
396b41f6
JM		 663 /* Conditional branch 1101 xxxx xxxx xxxx */
664 DECODE_CUSTOM (0xf000, 0xd000, t16_decode_cond_branch),
665
666 /*
667 * Unconditional branch
668 * B 1110 0xxx xxxx xxxx
669 */
670 DECODE_SIMULATE (0xf800, 0xe000, t16_simulate_branch),
671
3f92dfed
JM		 672 DECODE_END
673};
674
eaf4f33f
JM		 675static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
676{
677 if (unlikely(in_it_block(cpsr)))
678 return kprobe_condition_checks[current_cond(cpsr)](cpsr);
679 return true;
680}
681
c6a7d97d
JM		 682static void __kprobes thumb16_singlestep(struct kprobe *p, struct pt_regs *regs)
683{
684 regs->ARM_pc += 2;
685 p->ainsn.insn_handler(p, regs);
686 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
687}
688
689static void __kprobes thumb32_singlestep(struct kprobe *p, struct pt_regs *regs)
690{
691 regs->ARM_pc += 4;
692 p->ainsn.insn_handler(p, regs);
693 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
694}
695
24371707
JM		 696enum kprobe_insn __kprobes
697thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
698{
c6a7d97d 699 asi->insn_singlestep = thumb16_singlestep;
eaf4f33f 700 asi->insn_check_cc = thumb_check_cc;
3f92dfed 701 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true);
24371707
JM		 702}
703
704enum kprobe_insn __kprobes
705thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
706{
c6a7d97d 707 asi->insn_singlestep = thumb32_singlestep;
eaf4f33f 708 asi->insn_check_cc = thumb_check_cc;
f39ca8b4 709 return kprobe_decode_insn(insn, asi, kprobe_decode_thumb32_table, true);
24371707 710}
Linux kernel - Deliverables
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