Commit | Line | Data |
---|---|---|
1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
1b8873a0 | 15 | #include <linux/kernel.h> |
49c006b9 | 16 | #include <linux/platform_device.h> |
7be2958e | 17 | #include <linux/pm_runtime.h> |
5505b206 | 18 | #include <linux/uaccess.h> |
bbd64559 SB |
19 | #include <linux/irq.h> |
20 | #include <linux/irqdesc.h> | |
1b8873a0 | 21 | |
1b8873a0 JI |
22 | #include <asm/irq_regs.h> |
23 | #include <asm/pmu.h> | |
24 | #include <asm/stacktrace.h> | |
25 | ||
1b8873a0 | 26 | static int |
e1f431b5 MR |
27 | armpmu_map_cache_event(const unsigned (*cache_map) |
28 | [PERF_COUNT_HW_CACHE_MAX] | |
29 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
30 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
31 | u64 config) | |
1b8873a0 JI |
32 | { |
33 | unsigned int cache_type, cache_op, cache_result, ret; | |
34 | ||
35 | cache_type = (config >> 0) & 0xff; | |
36 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
37 | return -EINVAL; | |
38 | ||
39 | cache_op = (config >> 8) & 0xff; | |
40 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
41 | return -EINVAL; | |
42 | ||
43 | cache_result = (config >> 16) & 0xff; | |
44 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
45 | return -EINVAL; | |
46 | ||
e1f431b5 | 47 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
48 | |
49 | if (ret == CACHE_OP_UNSUPPORTED) | |
50 | return -ENOENT; | |
51 | ||
52 | return ret; | |
53 | } | |
54 | ||
84fee97a | 55 | static int |
6dbc0029 | 56 | armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 57 | { |
d9f96635 SB |
58 | int mapping; |
59 | ||
60 | if (config >= PERF_COUNT_HW_MAX) | |
61 | return -EINVAL; | |
62 | ||
63 | mapping = (*event_map)[config]; | |
e1f431b5 | 64 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; |
84fee97a WD |
65 | } |
66 | ||
67 | static int | |
e1f431b5 | 68 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 69 | { |
e1f431b5 MR |
70 | return (int)(config & raw_event_mask); |
71 | } | |
72 | ||
6dbc0029 WD |
73 | int |
74 | armpmu_map_event(struct perf_event *event, | |
75 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
76 | const unsigned (*cache_map) | |
77 | [PERF_COUNT_HW_CACHE_MAX] | |
78 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
79 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
80 | u32 raw_event_mask) | |
e1f431b5 MR |
81 | { |
82 | u64 config = event->attr.config; | |
83 | ||
84 | switch (event->attr.type) { | |
85 | case PERF_TYPE_HARDWARE: | |
6dbc0029 | 86 | return armpmu_map_hw_event(event_map, config); |
e1f431b5 MR |
87 | case PERF_TYPE_HW_CACHE: |
88 | return armpmu_map_cache_event(cache_map, config); | |
89 | case PERF_TYPE_RAW: | |
90 | return armpmu_map_raw_event(raw_event_mask, config); | |
91 | } | |
92 | ||
93 | return -ENOENT; | |
84fee97a WD |
94 | } |
95 | ||
ed6f2a52 | 96 | int armpmu_event_set_period(struct perf_event *event) |
1b8873a0 | 97 | { |
8a16b34e | 98 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 99 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 100 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
101 | s64 period = hwc->sample_period; |
102 | int ret = 0; | |
103 | ||
104 | if (unlikely(left <= -period)) { | |
105 | left = period; | |
e7850595 | 106 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
107 | hwc->last_period = period; |
108 | ret = 1; | |
109 | } | |
110 | ||
111 | if (unlikely(left <= 0)) { | |
112 | left += period; | |
e7850595 | 113 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
114 | hwc->last_period = period; |
115 | ret = 1; | |
116 | } | |
117 | ||
118 | if (left > (s64)armpmu->max_period) | |
119 | left = armpmu->max_period; | |
120 | ||
e7850595 | 121 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 | 122 | |
ed6f2a52 | 123 | armpmu->write_counter(event, (u64)(-left) & 0xffffffff); |
1b8873a0 JI |
124 | |
125 | perf_event_update_userpage(event); | |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
ed6f2a52 | 130 | u64 armpmu_event_update(struct perf_event *event) |
1b8873a0 | 131 | { |
8a16b34e | 132 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 133 | struct hw_perf_event *hwc = &event->hw; |
a737823d | 134 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
135 | |
136 | again: | |
e7850595 | 137 | prev_raw_count = local64_read(&hwc->prev_count); |
ed6f2a52 | 138 | new_raw_count = armpmu->read_counter(event); |
1b8873a0 | 139 | |
e7850595 | 140 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
141 | new_raw_count) != prev_raw_count) |
142 | goto again; | |
143 | ||
57273471 | 144 | delta = (new_raw_count - prev_raw_count) & armpmu->max_period; |
1b8873a0 | 145 | |
e7850595 PZ |
146 | local64_add(delta, &event->count); |
147 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
148 | |
149 | return new_raw_count; | |
150 | } | |
151 | ||
152 | static void | |
a4eaf7f1 | 153 | armpmu_read(struct perf_event *event) |
1b8873a0 | 154 | { |
ed6f2a52 | 155 | armpmu_event_update(event); |
1b8873a0 JI |
156 | } |
157 | ||
158 | static void | |
a4eaf7f1 | 159 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 160 | { |
8a16b34e | 161 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
162 | struct hw_perf_event *hwc = &event->hw; |
163 | ||
a4eaf7f1 PZ |
164 | /* |
165 | * ARM pmu always has to update the counter, so ignore | |
166 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
167 | */ | |
168 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
ed6f2a52 SK |
169 | armpmu->disable(event); |
170 | armpmu_event_update(event); | |
a4eaf7f1 PZ |
171 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
172 | } | |
1b8873a0 JI |
173 | } |
174 | ||
ed6f2a52 | 175 | static void armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 176 | { |
8a16b34e | 177 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
178 | struct hw_perf_event *hwc = &event->hw; |
179 | ||
a4eaf7f1 PZ |
180 | /* |
181 | * ARM pmu always has to reprogram the period, so ignore | |
182 | * PERF_EF_RELOAD, see the comment below. | |
183 | */ | |
184 | if (flags & PERF_EF_RELOAD) | |
185 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
186 | ||
187 | hwc->state = 0; | |
1b8873a0 JI |
188 | /* |
189 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 190 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
191 | * may have been left counting. If we don't do this step then we may |
192 | * get an interrupt too soon or *way* too late if the overflow has | |
193 | * happened since disabling. | |
194 | */ | |
ed6f2a52 SK |
195 | armpmu_event_set_period(event); |
196 | armpmu->enable(event); | |
1b8873a0 JI |
197 | } |
198 | ||
a4eaf7f1 PZ |
199 | static void |
200 | armpmu_del(struct perf_event *event, int flags) | |
201 | { | |
8a16b34e | 202 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 203 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
a4eaf7f1 PZ |
204 | struct hw_perf_event *hwc = &event->hw; |
205 | int idx = hwc->idx; | |
206 | ||
a4eaf7f1 | 207 | armpmu_stop(event, PERF_EF_UPDATE); |
8be3f9a2 MR |
208 | hw_events->events[idx] = NULL; |
209 | clear_bit(idx, hw_events->used_mask); | |
a4eaf7f1 PZ |
210 | |
211 | perf_event_update_userpage(event); | |
212 | } | |
213 | ||
1b8873a0 | 214 | static int |
a4eaf7f1 | 215 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 216 | { |
8a16b34e | 217 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 218 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
1b8873a0 JI |
219 | struct hw_perf_event *hwc = &event->hw; |
220 | int idx; | |
221 | int err = 0; | |
222 | ||
33696fc0 | 223 | perf_pmu_disable(event->pmu); |
24cd7f54 | 224 | |
1b8873a0 | 225 | /* If we don't have a space for the counter then finish early. */ |
ed6f2a52 | 226 | idx = armpmu->get_event_idx(hw_events, event); |
1b8873a0 JI |
227 | if (idx < 0) { |
228 | err = idx; | |
229 | goto out; | |
230 | } | |
231 | ||
232 | /* | |
233 | * If there is an event in the counter we are going to use then make | |
234 | * sure it is disabled. | |
235 | */ | |
236 | event->hw.idx = idx; | |
ed6f2a52 | 237 | armpmu->disable(event); |
8be3f9a2 | 238 | hw_events->events[idx] = event; |
1b8873a0 | 239 | |
a4eaf7f1 PZ |
240 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
241 | if (flags & PERF_EF_START) | |
242 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
243 | |
244 | /* Propagate our changes to the userspace mapping. */ | |
245 | perf_event_update_userpage(event); | |
246 | ||
247 | out: | |
33696fc0 | 248 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
249 | return err; |
250 | } | |
251 | ||
1b8873a0 | 252 | static int |
8be3f9a2 | 253 | validate_event(struct pmu_hw_events *hw_events, |
1b8873a0 JI |
254 | struct perf_event *event) |
255 | { | |
8a16b34e | 256 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 257 | |
c95eb318 WD |
258 | if (is_software_event(event)) |
259 | return 1; | |
260 | ||
2dfcb802 | 261 | if (event->state < PERF_EVENT_STATE_OFF) |
cb2d8b34 WD |
262 | return 1; |
263 | ||
264 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) | |
65b4711f | 265 | return 1; |
1b8873a0 | 266 | |
ed6f2a52 | 267 | return armpmu->get_event_idx(hw_events, event) >= 0; |
1b8873a0 JI |
268 | } |
269 | ||
270 | static int | |
271 | validate_group(struct perf_event *event) | |
272 | { | |
273 | struct perf_event *sibling, *leader = event->group_leader; | |
8be3f9a2 | 274 | struct pmu_hw_events fake_pmu; |
bce34d14 | 275 | DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS); |
1b8873a0 | 276 | |
bce34d14 WD |
277 | /* |
278 | * Initialise the fake PMU. We only need to populate the | |
279 | * used_mask for the purposes of validation. | |
280 | */ | |
281 | memset(fake_used_mask, 0, sizeof(fake_used_mask)); | |
282 | fake_pmu.used_mask = fake_used_mask; | |
1b8873a0 JI |
283 | |
284 | if (!validate_event(&fake_pmu, leader)) | |
aa2bc1ad | 285 | return -EINVAL; |
1b8873a0 JI |
286 | |
287 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
288 | if (!validate_event(&fake_pmu, sibling)) | |
aa2bc1ad | 289 | return -EINVAL; |
1b8873a0 JI |
290 | } |
291 | ||
292 | if (!validate_event(&fake_pmu, event)) | |
aa2bc1ad | 293 | return -EINVAL; |
1b8873a0 JI |
294 | |
295 | return 0; | |
296 | } | |
297 | ||
051f1b13 | 298 | static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) |
0e25a5c9 | 299 | { |
bbd64559 SB |
300 | struct arm_pmu *armpmu; |
301 | struct platform_device *plat_device; | |
302 | struct arm_pmu_platdata *plat; | |
303 | ||
304 | if (irq_is_percpu(irq)) | |
305 | dev = *(void **)dev; | |
306 | armpmu = dev; | |
307 | plat_device = armpmu->plat_device; | |
308 | plat = dev_get_platdata(&plat_device->dev); | |
0e25a5c9 | 309 | |
051f1b13 SK |
310 | if (plat && plat->handle_irq) |
311 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
312 | else | |
313 | return armpmu->handle_irq(irq, dev); | |
0e25a5c9 RV |
314 | } |
315 | ||
0b390e21 | 316 | static void |
8a16b34e | 317 | armpmu_release_hardware(struct arm_pmu *armpmu) |
0b390e21 | 318 | { |
ed6f2a52 | 319 | armpmu->free_irq(armpmu); |
051f1b13 | 320 | pm_runtime_put_sync(&armpmu->plat_device->dev); |
0b390e21 WD |
321 | } |
322 | ||
1b8873a0 | 323 | static int |
8a16b34e | 324 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
1b8873a0 | 325 | { |
051f1b13 | 326 | int err; |
a9356a04 | 327 | struct platform_device *pmu_device = armpmu->plat_device; |
1b8873a0 | 328 | |
e5a21327 WD |
329 | if (!pmu_device) |
330 | return -ENODEV; | |
331 | ||
7be2958e | 332 | pm_runtime_get_sync(&pmu_device->dev); |
ed6f2a52 | 333 | err = armpmu->request_irq(armpmu, armpmu_dispatch_irq); |
051f1b13 SK |
334 | if (err) { |
335 | armpmu_release_hardware(armpmu); | |
336 | return err; | |
49c006b9 | 337 | } |
1b8873a0 | 338 | |
0b390e21 | 339 | return 0; |
1b8873a0 JI |
340 | } |
341 | ||
1b8873a0 JI |
342 | static void |
343 | hw_perf_event_destroy(struct perf_event *event) | |
344 | { | |
8a16b34e | 345 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
03b7898d MR |
346 | atomic_t *active_events = &armpmu->active_events; |
347 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
348 | ||
349 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
8a16b34e | 350 | armpmu_release_hardware(armpmu); |
03b7898d | 351 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
352 | } |
353 | } | |
354 | ||
05d22fde WD |
355 | static int |
356 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
357 | { | |
358 | return attr->exclude_idle || attr->exclude_user || | |
359 | attr->exclude_kernel || attr->exclude_hv; | |
360 | } | |
361 | ||
1b8873a0 JI |
362 | static int |
363 | __hw_perf_event_init(struct perf_event *event) | |
364 | { | |
8a16b34e | 365 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 366 | struct hw_perf_event *hwc = &event->hw; |
9dcbf466 | 367 | int mapping; |
1b8873a0 | 368 | |
e1f431b5 | 369 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
370 | |
371 | if (mapping < 0) { | |
372 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
373 | event->attr.config); | |
374 | return mapping; | |
375 | } | |
376 | ||
05d22fde WD |
377 | /* |
378 | * We don't assign an index until we actually place the event onto | |
379 | * hardware. Use -1 to signify that we haven't decided where to put it | |
380 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
381 | * clever allocation or constraints checking at this point. | |
382 | */ | |
383 | hwc->idx = -1; | |
384 | hwc->config_base = 0; | |
385 | hwc->config = 0; | |
386 | hwc->event_base = 0; | |
387 | ||
1b8873a0 JI |
388 | /* |
389 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 390 | */ |
05d22fde WD |
391 | if ((!armpmu->set_event_filter || |
392 | armpmu->set_event_filter(hwc, &event->attr)) && | |
393 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
394 | pr_debug("ARM performance counters do not support " |
395 | "mode exclusion\n"); | |
fdeb8e35 | 396 | return -EOPNOTSUPP; |
1b8873a0 JI |
397 | } |
398 | ||
399 | /* | |
05d22fde | 400 | * Store the event encoding into the config_base field. |
1b8873a0 | 401 | */ |
05d22fde | 402 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
403 | |
404 | if (!hwc->sample_period) { | |
57273471 WD |
405 | /* |
406 | * For non-sampling runs, limit the sample_period to half | |
407 | * of the counter width. That way, the new counter value | |
408 | * is far less likely to overtake the previous one unless | |
409 | * you have some serious IRQ latency issues. | |
410 | */ | |
411 | hwc->sample_period = armpmu->max_period >> 1; | |
1b8873a0 | 412 | hwc->last_period = hwc->sample_period; |
e7850595 | 413 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
414 | } |
415 | ||
1b8873a0 | 416 | if (event->group_leader != event) { |
e595ede6 | 417 | if (validate_group(event) != 0) |
1b8873a0 JI |
418 | return -EINVAL; |
419 | } | |
420 | ||
9dcbf466 | 421 | return 0; |
1b8873a0 JI |
422 | } |
423 | ||
b0a873eb | 424 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 425 | { |
8a16b34e | 426 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 427 | int err = 0; |
03b7898d | 428 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 429 | |
2481c5fa SE |
430 | /* does not support taken branch sampling */ |
431 | if (has_branch_stack(event)) | |
432 | return -EOPNOTSUPP; | |
433 | ||
e1f431b5 | 434 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 435 | return -ENOENT; |
b0a873eb | 436 | |
1b8873a0 JI |
437 | event->destroy = hw_perf_event_destroy; |
438 | ||
03b7898d MR |
439 | if (!atomic_inc_not_zero(active_events)) { |
440 | mutex_lock(&armpmu->reserve_mutex); | |
441 | if (atomic_read(active_events) == 0) | |
8a16b34e | 442 | err = armpmu_reserve_hardware(armpmu); |
1b8873a0 JI |
443 | |
444 | if (!err) | |
03b7898d MR |
445 | atomic_inc(active_events); |
446 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
447 | } |
448 | ||
449 | if (err) | |
b0a873eb | 450 | return err; |
1b8873a0 JI |
451 | |
452 | err = __hw_perf_event_init(event); | |
453 | if (err) | |
454 | hw_perf_event_destroy(event); | |
455 | ||
b0a873eb | 456 | return err; |
1b8873a0 JI |
457 | } |
458 | ||
a4eaf7f1 | 459 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 460 | { |
8be3f9a2 | 461 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
8be3f9a2 | 462 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
7325eaec | 463 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
1b8873a0 | 464 | |
f4f38430 | 465 | if (enabled) |
ed6f2a52 | 466 | armpmu->start(armpmu); |
1b8873a0 JI |
467 | } |
468 | ||
a4eaf7f1 | 469 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 470 | { |
8a16b34e | 471 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
ed6f2a52 | 472 | armpmu->stop(armpmu); |
1b8873a0 JI |
473 | } |
474 | ||
7be2958e JH |
475 | #ifdef CONFIG_PM_RUNTIME |
476 | static int armpmu_runtime_resume(struct device *dev) | |
477 | { | |
478 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
479 | ||
480 | if (plat && plat->runtime_resume) | |
481 | return plat->runtime_resume(dev); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | static int armpmu_runtime_suspend(struct device *dev) | |
487 | { | |
488 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
489 | ||
490 | if (plat && plat->runtime_suspend) | |
491 | return plat->runtime_suspend(dev); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | #endif | |
496 | ||
6dbc0029 WD |
497 | const struct dev_pm_ops armpmu_dev_pm_ops = { |
498 | SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) | |
499 | }; | |
500 | ||
44d6b1fc | 501 | static void armpmu_init(struct arm_pmu *armpmu) |
03b7898d MR |
502 | { |
503 | atomic_set(&armpmu->active_events, 0); | |
504 | mutex_init(&armpmu->reserve_mutex); | |
8a16b34e MR |
505 | |
506 | armpmu->pmu = (struct pmu) { | |
507 | .pmu_enable = armpmu_enable, | |
508 | .pmu_disable = armpmu_disable, | |
509 | .event_init = armpmu_event_init, | |
510 | .add = armpmu_add, | |
511 | .del = armpmu_del, | |
512 | .start = armpmu_start, | |
513 | .stop = armpmu_stop, | |
514 | .read = armpmu_read, | |
515 | }; | |
516 | } | |
517 | ||
0305230a | 518 | int armpmu_register(struct arm_pmu *armpmu, int type) |
8a16b34e MR |
519 | { |
520 | armpmu_init(armpmu); | |
2ac29a14 | 521 | pm_runtime_enable(&armpmu->plat_device->dev); |
04236f9f WD |
522 | pr_info("enabled with %s PMU driver, %d counters available\n", |
523 | armpmu->name, armpmu->num_events); | |
0305230a | 524 | return perf_pmu_register(&armpmu->pmu, armpmu->name, type); |
03b7898d MR |
525 | } |
526 | ||
1b8873a0 JI |
527 | /* |
528 | * Callchain handling code. | |
529 | */ | |
1b8873a0 JI |
530 | |
531 | /* | |
532 | * The registers we're interested in are at the end of the variable | |
533 | * length saved register structure. The fp points at the end of this | |
534 | * structure so the address of this struct is: | |
535 | * (struct frame_tail *)(xxx->fp)-1 | |
536 | * | |
537 | * This code has been adapted from the ARM OProfile support. | |
538 | */ | |
539 | struct frame_tail { | |
4d6b7a77 WD |
540 | struct frame_tail __user *fp; |
541 | unsigned long sp; | |
542 | unsigned long lr; | |
1b8873a0 JI |
543 | } __attribute__((packed)); |
544 | ||
545 | /* | |
546 | * Get the return address for a single stackframe and return a pointer to the | |
547 | * next frame tail. | |
548 | */ | |
4d6b7a77 WD |
549 | static struct frame_tail __user * |
550 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
551 | struct perf_callchain_entry *entry) |
552 | { | |
553 | struct frame_tail buftail; | |
554 | ||
555 | /* Also check accessibility of one struct frame_tail beyond */ | |
556 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
557 | return NULL; | |
558 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
559 | return NULL; | |
560 | ||
70791ce9 | 561 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
562 | |
563 | /* | |
564 | * Frame pointers should strictly progress back up the stack | |
565 | * (towards higher addresses). | |
566 | */ | |
cb06199b | 567 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
568 | return NULL; |
569 | ||
570 | return buftail.fp - 1; | |
571 | } | |
572 | ||
56962b44 FW |
573 | void |
574 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 575 | { |
4d6b7a77 | 576 | struct frame_tail __user *tail; |
1b8873a0 | 577 | |
e50c5418 MZ |
578 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
579 | /* We don't support guest os callchain now */ | |
580 | return; | |
581 | } | |
1b8873a0 | 582 | |
c5f927a6 | 583 | perf_callchain_store(entry, regs->ARM_pc); |
4d6b7a77 | 584 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 585 | |
860ad782 SR |
586 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
587 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
588 | tail = user_backtrace(tail, entry); |
589 | } | |
590 | ||
591 | /* | |
592 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
593 | * whist unwinding the stackframe and is like a subroutine return so we use | |
594 | * the PC. | |
595 | */ | |
596 | static int | |
597 | callchain_trace(struct stackframe *fr, | |
598 | void *data) | |
599 | { | |
600 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 601 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
602 | return 0; |
603 | } | |
604 | ||
56962b44 FW |
605 | void |
606 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
607 | { |
608 | struct stackframe fr; | |
609 | ||
e50c5418 MZ |
610 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
611 | /* We don't support guest os callchain now */ | |
612 | return; | |
613 | } | |
614 | ||
1b8873a0 JI |
615 | fr.fp = regs->ARM_fp; |
616 | fr.sp = regs->ARM_sp; | |
617 | fr.lr = regs->ARM_lr; | |
618 | fr.pc = regs->ARM_pc; | |
619 | walk_stackframe(&fr, callchain_trace, entry); | |
620 | } | |
e50c5418 MZ |
621 | |
622 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
623 | { | |
624 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) | |
625 | return perf_guest_cbs->get_guest_ip(); | |
626 | ||
627 | return instruction_pointer(regs); | |
628 | } | |
629 | ||
630 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
631 | { | |
632 | int misc = 0; | |
633 | ||
634 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { | |
635 | if (perf_guest_cbs->is_user_mode()) | |
636 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
637 | else | |
638 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
639 | } else { | |
640 | if (user_mode(regs)) | |
641 | misc |= PERF_RECORD_MISC_USER; | |
642 | else | |
643 | misc |= PERF_RECORD_MISC_KERNEL; | |
644 | } | |
645 | ||
646 | return misc; | |
647 | } |