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perf: Add helper function to return number of counters
[deliverable/linux.git] / arch / arm / kernel / perf_event.c
CommitLineData
1b8873a0
JI		 1#undef DEBUG
2
3/*
4 * ARM performance counter support.
5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 *
796d1295
JP		 8 * ARMv7 support: Jean Pihet <jpihet@mvista.com>
9 * 2010 (c) MontaVista Software, LLC.
10 *
1b8873a0
JI		 11 * This code is based on the sparc64 perf event code, which is in turn based
12 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 * code.
14 */
15#define pr_fmt(fmt) "hw perfevents: " fmt
16
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
181193f3 19#include <linux/module.h>
1b8873a0 20#include <linux/perf_event.h>
49c006b9 21#include <linux/platform_device.h>
1b8873a0
JI		 22#include <linux/spinlock.h>
23#include <linux/uaccess.h>
24
25#include <asm/cputype.h>
26#include <asm/irq.h>
27#include <asm/irq_regs.h>
28#include <asm/pmu.h>
29#include <asm/stacktrace.h>
30
49c006b9 31static struct platform_device *pmu_device;
1b8873a0
JI		 32
33/*
34 * Hardware lock to serialize accesses to PMU registers. Needed for the
35 * read/modify/write sequences.
36 */
37DEFINE_SPINLOCK(pmu_lock);
38
39/*
40 * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
41 * another platform that supports more, we need to increase this to be the
42 * largest of all platforms.
796d1295
JP		 43 *
44 * ARMv7 supports up to 32 events:
45 * cycle counter CCNT + 31 events counters CNT0..30.
46 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
1b8873a0 47 */
796d1295 48#define ARMPMU_MAX_HWEVENTS 33
1b8873a0
JI		 49
50/* The events for a given CPU. */
51struct cpu_hw_events {
52 /*
53 * The events that are active on the CPU for the given index. Index 0
54 * is reserved.
55 */
56 struct perf_event *events[ARMPMU_MAX_HWEVENTS];
57
58 /*
59 * A 1 bit for an index indicates that the counter is being used for
60 * an event. A 0 means that the counter can be used.
61 */
62 unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
63
64 /*
65 * A 1 bit for an index indicates that the counter is actively being
66 * used.
67 */
68 unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
69};
70DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
71
181193f3
WD		 72/* PMU names. */
73static const char *arm_pmu_names[] = {
74 [ARM_PERF_PMU_ID_XSCALE1] = "xscale1",
75 [ARM_PERF_PMU_ID_XSCALE2] = "xscale2",
76 [ARM_PERF_PMU_ID_V6] = "v6",
77 [ARM_PERF_PMU_ID_V6MP] = "v6mpcore",
78 [ARM_PERF_PMU_ID_CA8] = "ARMv7 Cortex-A8",
79 [ARM_PERF_PMU_ID_CA9] = "ARMv7 Cortex-A9",
80};
81
1b8873a0 82struct arm_pmu {
181193f3 83 enum arm_perf_pmu_ids id;
1b8873a0
JI		 84 irqreturn_t (*handle_irq)(int irq_num, void *dev);
85 void (*enable)(struct hw_perf_event *evt, int idx);
86 void (*disable)(struct hw_perf_event *evt, int idx);
87 int (*event_map)(int evt);
88 u64 (*raw_event)(u64);
89 int (*get_event_idx)(struct cpu_hw_events *cpuc,
90 struct hw_perf_event *hwc);
91 u32 (*read_counter)(int idx);
92 void (*write_counter)(int idx, u32 val);
93 void (*start)(void);
94 void (*stop)(void);
95 int num_events;
96 u64 max_period;
97};
98
99/* Set at runtime when we know what CPU type we are. */
100static const struct arm_pmu *armpmu;
101
181193f3
WD		 102enum arm_perf_pmu_ids
103armpmu_get_pmu_id(void)
104{
105 int id = -ENODEV;
106
107 if (armpmu != NULL)
108 id = armpmu->id;
109
110 return id;
111}
112EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
113
929f5199
WD		 114int
115armpmu_get_max_events(void)
116{
117 int max_events = 0;
118
119 if (armpmu != NULL)
120 max_events = armpmu->num_events;
121
122 return max_events;
123}
124EXPORT_SYMBOL_GPL(armpmu_get_max_events);
125
3bf101ba
MF		 126int perf_num_counters(void)
127{
128 return armpmu_get_max_events();
129}
130EXPORT_SYMBOL_GPL(perf_num_counters);
131
1b8873a0
JI		 132#define HW_OP_UNSUPPORTED 0xFFFF
133
134#define C(_x) \
135 PERF_COUNT_HW_CACHE_##_x
136
137#define CACHE_OP_UNSUPPORTED 0xFFFF
138
139static unsigned armpmu_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
140 [PERF_COUNT_HW_CACHE_OP_MAX]
141 [PERF_COUNT_HW_CACHE_RESULT_MAX];
142
143static int
144armpmu_map_cache_event(u64 config)
145{
146 unsigned int cache_type, cache_op, cache_result, ret;
147
148 cache_type = (config >> 0) & 0xff;
149 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
150 return -EINVAL;
151
152 cache_op = (config >> 8) & 0xff;
153 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
154 return -EINVAL;
155
156 cache_result = (config >> 16) & 0xff;
157 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
158 return -EINVAL;
159
160 ret = (int)armpmu_perf_cache_map[cache_type][cache_op][cache_result];
161
162 if (ret == CACHE_OP_UNSUPPORTED)
163 return -ENOENT;
164
165 return ret;
166}
167
168static int
169armpmu_event_set_period(struct perf_event *event,
170 struct hw_perf_event *hwc,
171 int idx)
172{
e7850595 173 s64 left = local64_read(&hwc->period_left);
1b8873a0
JI		 174 s64 period = hwc->sample_period;
175 int ret = 0;
176
177 if (unlikely(left <= -period)) {
178 left = period;
e7850595 179 local64_set(&hwc->period_left, left);
1b8873a0
JI		 180 hwc->last_period = period;
181 ret = 1;
182 }
183
184 if (unlikely(left <= 0)) {
185 left += period;
e7850595 186 local64_set(&hwc->period_left, left);
1b8873a0
JI		 187 hwc->last_period = period;
188 ret = 1;
189 }
190
191 if (left > (s64)armpmu->max_period)
192 left = armpmu->max_period;
193
e7850595 194 local64_set(&hwc->prev_count, (u64)-left);
1b8873a0
JI		 195
196 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
197
198 perf_event_update_userpage(event);
199
200 return ret;
201}
202
203static u64
204armpmu_event_update(struct perf_event *event,
205 struct hw_perf_event *hwc,
206 int idx)
207{
208 int shift = 64 - 32;
209 s64 prev_raw_count, new_raw_count;
446a5a8b 210 u64 delta;
1b8873a0
JI		 211
212again:
e7850595 213 prev_raw_count = local64_read(&hwc->prev_count);
1b8873a0
JI		 214 new_raw_count = armpmu->read_counter(idx);
215
e7850595 216 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
1b8873a0
JI		 217 new_raw_count) != prev_raw_count)
218 goto again;
219
220 delta = (new_raw_count << shift) - (prev_raw_count << shift);
221 delta >>= shift;
222
e7850595
PZ		 223 local64_add(delta, &event->count);
224 local64_sub(delta, &hwc->period_left);
1b8873a0
JI		 225
226 return new_raw_count;
227}
228
229static void
230armpmu_disable(struct perf_event *event)
231{
232 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
233 struct hw_perf_event *hwc = &event->hw;
234 int idx = hwc->idx;
235
236 WARN_ON(idx < 0);
237
238 clear_bit(idx, cpuc->active_mask);
239 armpmu->disable(hwc, idx);
240
241 barrier();
242
243 armpmu_event_update(event, hwc, idx);
244 cpuc->events[idx] = NULL;
245 clear_bit(idx, cpuc->used_mask);
246
247 perf_event_update_userpage(event);
248}
249
250static void
251armpmu_read(struct perf_event *event)
252{
253 struct hw_perf_event *hwc = &event->hw;
254
255 /* Don't read disabled counters! */
256 if (hwc->idx < 0)
257 return;
258
259 armpmu_event_update(event, hwc, hwc->idx);
260}
261
262static void
263armpmu_unthrottle(struct perf_event *event)
264{
265 struct hw_perf_event *hwc = &event->hw;
266
267 /*
268 * Set the period again. Some counters can't be stopped, so when we
269 * were throttled we simply disabled the IRQ source and the counter
270 * may have been left counting. If we don't do this step then we may
271 * get an interrupt too soon or *way* too late if the overflow has
272 * happened since disabling.
273 */
274 armpmu_event_set_period(event, hwc, hwc->idx);
275 armpmu->enable(hwc, hwc->idx);
276}
277
278static int
279armpmu_enable(struct perf_event *event)
280{
281 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
282 struct hw_perf_event *hwc = &event->hw;
283 int idx;
284 int err = 0;
285
286 /* If we don't have a space for the counter then finish early. */
287 idx = armpmu->get_event_idx(cpuc, hwc);
288 if (idx < 0) {
289 err = idx;
290 goto out;
291 }
292
293 /*
294 * If there is an event in the counter we are going to use then make
295 * sure it is disabled.
296 */
297 event->hw.idx = idx;
298 armpmu->disable(hwc, idx);
299 cpuc->events[idx] = event;
300 set_bit(idx, cpuc->active_mask);
301
302 /* Set the period for the event. */
303 armpmu_event_set_period(event, hwc, idx);
304
305 /* Enable the event. */
306 armpmu->enable(hwc, idx);
307
308 /* Propagate our changes to the userspace mapping. */
309 perf_event_update_userpage(event);
310
311out:
312 return err;
313}
314
315static struct pmu pmu = {
316 .enable = armpmu_enable,
317 .disable = armpmu_disable,
318 .unthrottle = armpmu_unthrottle,
319 .read = armpmu_read,
320};
321
322static int
323validate_event(struct cpu_hw_events *cpuc,
324 struct perf_event *event)
325{
326 struct hw_perf_event fake_event = event->hw;
327
328 if (event->pmu && event->pmu != &pmu)
329 return 0;
330
331 return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
332}
333
334static int
335validate_group(struct perf_event *event)
336{
337 struct perf_event *sibling, *leader = event->group_leader;
338 struct cpu_hw_events fake_pmu;
339
340 memset(&fake_pmu, 0, sizeof(fake_pmu));
341
342 if (!validate_event(&fake_pmu, leader))
343 return -ENOSPC;
344
345 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
346 if (!validate_event(&fake_pmu, sibling))
347 return -ENOSPC;
348 }
349
350 if (!validate_event(&fake_pmu, event))
351 return -ENOSPC;
352
353 return 0;
354}
355
356static int
357armpmu_reserve_hardware(void)
358{
49c006b9 359 int i, err = -ENODEV, irq;
1b8873a0 360
49c006b9
WD		 361 pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
362 if (IS_ERR(pmu_device)) {
1b8873a0 363 pr_warning("unable to reserve pmu\n");
49c006b9 364 return PTR_ERR(pmu_device);
1b8873a0
JI		 365 }
366
49c006b9 367 init_pmu(ARM_PMU_DEVICE_CPU);
1b8873a0 368
49c006b9 369 if (pmu_device->num_resources < 1) {
1b8873a0
JI		 370 pr_err("no irqs for PMUs defined\n");
371 return -ENODEV;
372 }
373
49c006b9
WD		 374 for (i = 0; i < pmu_device->num_resources; ++i) {
375 irq = platform_get_irq(pmu_device, i);
376 if (irq < 0)
377 continue;
378
379 err = request_irq(irq, armpmu->handle_irq,
ddee87f2
WD		 380 IRQF_DISABLED | IRQF_NOBALANCING,
381 "armpmu", NULL);
1b8873a0 382 if (err) {
49c006b9
WD		 383 pr_warning("unable to request IRQ%d for ARM perf "
384 "counters\n", irq);
1b8873a0
JI		 385 break;
386 }
387 }
388
389 if (err) {
49c006b9
WD		 390 for (i = i - 1; i >= 0; --i) {
391 irq = platform_get_irq(pmu_device, i);
392 if (irq >= 0)
393 free_irq(irq, NULL);
394 }
395 release_pmu(pmu_device);
396 pmu_device = NULL;
1b8873a0
JI		 397 }
398
399 return err;
400}
401
402static void
403armpmu_release_hardware(void)
404{
49c006b9 405 int i, irq;
1b8873a0 406
49c006b9
WD		 407 for (i = pmu_device->num_resources - 1; i >= 0; --i) {
408 irq = platform_get_irq(pmu_device, i);
409 if (irq >= 0)
410 free_irq(irq, NULL);
411 }
1b8873a0
JI		 412 armpmu->stop();
413
49c006b9
WD		 414 release_pmu(pmu_device);
415 pmu_device = NULL;
1b8873a0
JI		 416}
417
418static atomic_t active_events = ATOMIC_INIT(0);
419static DEFINE_MUTEX(pmu_reserve_mutex);
420
421static void
422hw_perf_event_destroy(struct perf_event *event)
423{
424 if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
425 armpmu_release_hardware();
426 mutex_unlock(&pmu_reserve_mutex);
427 }
428}
429
430static int
431__hw_perf_event_init(struct perf_event *event)
432{
433 struct hw_perf_event *hwc = &event->hw;
434 int mapping, err;
435
436 /* Decode the generic type into an ARM event identifier. */
437 if (PERF_TYPE_HARDWARE == event->attr.type) {
438 mapping = armpmu->event_map(event->attr.config);
439 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
440 mapping = armpmu_map_cache_event(event->attr.config);
441 } else if (PERF_TYPE_RAW == event->attr.type) {
442 mapping = armpmu->raw_event(event->attr.config);
443 } else {
444 pr_debug("event type %x not supported\n", event->attr.type);
445 return -EOPNOTSUPP;
446 }
447
448 if (mapping < 0) {
449 pr_debug("event %x:%llx not supported\n", event->attr.type,
450 event->attr.config);
451 return mapping;
452 }
453
454 /*
455 * Check whether we need to exclude the counter from certain modes.
456 * The ARM performance counters are on all of the time so if someone
457 * has asked us for some excludes then we have to fail.
458 */
459 if (event->attr.exclude_kernel || event->attr.exclude_user ||
460 event->attr.exclude_hv || event->attr.exclude_idle) {
461 pr_debug("ARM performance counters do not support "
462 "mode exclusion\n");
463 return -EPERM;
464 }
465
466 /*
467 * We don't assign an index until we actually place the event onto
468 * hardware. Use -1 to signify that we haven't decided where to put it
469 * yet. For SMP systems, each core has it's own PMU so we can't do any
470 * clever allocation or constraints checking at this point.
471 */
472 hwc->idx = -1;
473
474 /*
475 * Store the event encoding into the config_base field. config and
476 * event_base are unused as the only 2 things we need to know are
477 * the event mapping and the counter to use. The counter to use is
478 * also the indx and the config_base is the event type.
479 */
480 hwc->config_base = (unsigned long)mapping;
481 hwc->config = 0;
482 hwc->event_base = 0;
483
484 if (!hwc->sample_period) {
485 hwc->sample_period = armpmu->max_period;
486 hwc->last_period = hwc->sample_period;
e7850595 487 local64_set(&hwc->period_left, hwc->sample_period);
1b8873a0
JI		 488 }
489
490 err = 0;
491 if (event->group_leader != event) {
492 err = validate_group(event);
493 if (err)
494 return -EINVAL;
495 }
496
497 return err;
498}
499
500const struct pmu *
501hw_perf_event_init(struct perf_event *event)
502{
503 int err = 0;
504
505 if (!armpmu)
506 return ERR_PTR(-ENODEV);
507
508 event->destroy = hw_perf_event_destroy;
509
510 if (!atomic_inc_not_zero(&active_events)) {
511 if (atomic_read(&active_events) > perf_max_events) {
512 atomic_dec(&active_events);
513 return ERR_PTR(-ENOSPC);
514 }
515
516 mutex_lock(&pmu_reserve_mutex);
517 if (atomic_read(&active_events) == 0) {
518 err = armpmu_reserve_hardware();
519 }
520
521 if (!err)
522 atomic_inc(&active_events);
523 mutex_unlock(&pmu_reserve_mutex);
524 }
525
526 if (err)
527 return ERR_PTR(err);
528
529 err = __hw_perf_event_init(event);
530 if (err)
531 hw_perf_event_destroy(event);
532
533 return err ? ERR_PTR(err) : &pmu;
534}
535
536void
537hw_perf_enable(void)
538{
539 /* Enable all of the perf events on hardware. */
540 int idx;
541 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
542
543 if (!armpmu)
544 return;
545
546 for (idx = 0; idx <= armpmu->num_events; ++idx) {
547 struct perf_event *event = cpuc->events[idx];
548
549 if (!event)
550 continue;
551
552 armpmu->enable(&event->hw, idx);
553 }
554
555 armpmu->start();
556}
557
558void
559hw_perf_disable(void)
560{
561 if (armpmu)
562 armpmu->stop();
563}
564
565/*
566 * ARMv6 Performance counter handling code.
567 *
568 * ARMv6 has 2 configurable performance counters and a single cycle counter.
569 * They all share a single reset bit but can be written to zero so we can use
570 * that for a reset.
571 *
572 * The counters can't be individually enabled or disabled so when we remove
573 * one event and replace it with another we could get spurious counts from the
574 * wrong event. However, we can take advantage of the fact that the
575 * performance counters can export events to the event bus, and the event bus
576 * itself can be monitored. This requires that we *don't* export the events to
577 * the event bus. The procedure for disabling a configurable counter is:
578 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
579 * effectively stops the counter from counting.
580 * - disable the counter's interrupt generation (each counter has it's
581 * own interrupt enable bit).
582 * Once stopped, the counter value can be written as 0 to reset.
583 *
584 * To enable a counter:
585 * - enable the counter's interrupt generation.
586 * - set the new event type.
587 *
588 * Note: the dedicated cycle counter only counts cycles and can't be
589 * enabled/disabled independently of the others. When we want to disable the
590 * cycle counter, we have to just disable the interrupt reporting and start
591 * ignoring that counter. When re-enabling, we have to reset the value and
592 * enable the interrupt.
593 */
594
595enum armv6_perf_types {
596 ARMV6_PERFCTR_ICACHE_MISS = 0x0,
597 ARMV6_PERFCTR_IBUF_STALL = 0x1,
598 ARMV6_PERFCTR_DDEP_STALL = 0x2,
599 ARMV6_PERFCTR_ITLB_MISS = 0x3,
600 ARMV6_PERFCTR_DTLB_MISS = 0x4,
601 ARMV6_PERFCTR_BR_EXEC = 0x5,
602 ARMV6_PERFCTR_BR_MISPREDICT = 0x6,
603 ARMV6_PERFCTR_INSTR_EXEC = 0x7,
604 ARMV6_PERFCTR_DCACHE_HIT = 0x9,
605 ARMV6_PERFCTR_DCACHE_ACCESS = 0xA,
606 ARMV6_PERFCTR_DCACHE_MISS = 0xB,
607 ARMV6_PERFCTR_DCACHE_WBACK = 0xC,
608 ARMV6_PERFCTR_SW_PC_CHANGE = 0xD,
609 ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF,
610 ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10,
611 ARMV6_PERFCTR_LSU_FULL_STALL = 0x11,
612 ARMV6_PERFCTR_WBUF_DRAINED = 0x12,
613 ARMV6_PERFCTR_CPU_CYCLES = 0xFF,
614 ARMV6_PERFCTR_NOP = 0x20,
615};
616
617enum armv6_counters {
618 ARMV6_CYCLE_COUNTER = 1,
619 ARMV6_COUNTER0,
620 ARMV6_COUNTER1,
621};
622
623/*
624 * The hardware events that we support. We do support cache operations but
625 * we have harvard caches and no way to combine instruction and data
626 * accesses/misses in hardware.
627 */
628static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
629 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES,
630 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC,
631 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
632 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
633 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
634 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT,
635 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
636};
637
638static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
639 [PERF_COUNT_HW_CACHE_OP_MAX]
640 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
641 [C(L1D)] = {
642 /*
643 * The performance counters don't differentiate between read
644 * and write accesses/misses so this isn't strictly correct,
645 * but it's the best we can do. Writes and reads get
646 * combined.
647 */
648 [C(OP_READ)] = {
649 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
650 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
651 },
652 [C(OP_WRITE)] = {
653 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
654 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
655 },
656 [C(OP_PREFETCH)] = {
657 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
658 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
659 },
660 },
661 [C(L1I)] = {
662 [C(OP_READ)] = {
663 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
664 [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
665 },
666 [C(OP_WRITE)] = {
667 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
668 [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
669 },
670 [C(OP_PREFETCH)] = {
671 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
672 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
673 },
674 },
675 [C(LL)] = {
676 [C(OP_READ)] = {
677 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
678 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
679 },
680 [C(OP_WRITE)] = {
681 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
682 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
683 },
684 [C(OP_PREFETCH)] = {
685 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
686 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
687 },
688 },
689 [C(DTLB)] = {
690 /*
691 * The ARM performance counters can count micro DTLB misses,
692 * micro ITLB misses and main TLB misses. There isn't an event
693 * for TLB misses, so use the micro misses here and if users
694 * want the main TLB misses they can use a raw counter.
695 */
696 [C(OP_READ)] = {
697 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
698 [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
699 },
700 [C(OP_WRITE)] = {
701 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
702 [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
703 },
704 [C(OP_PREFETCH)] = {
705 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
706 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
707 },
708 },
709 [C(ITLB)] = {
710 [C(OP_READ)] = {
711 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
712 [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
713 },
714 [C(OP_WRITE)] = {
715 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
716 [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
717 },
718 [C(OP_PREFETCH)] = {
719 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
720 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
721 },
722 },
723 [C(BPU)] = {
724 [C(OP_READ)] = {
725 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
726 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
727 },
728 [C(OP_WRITE)] = {
729 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
730 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
731 },
732 [C(OP_PREFETCH)] = {
733 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
734 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
735 },
736 },
737};
738
739enum armv6mpcore_perf_types {
740 ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0,
741 ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1,
742 ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2,
743 ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3,
744 ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4,
745 ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5,
746 ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6,
747 ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7,
748 ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8,
749 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
750 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB,
751 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
752 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD,
753 ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
754 ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF,
755 ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10,
756 ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
757 ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12,
758 ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13,
759 ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF,
760};
761
762/*
763 * The hardware events that we support. We do support cache operations but
764 * we have harvard caches and no way to combine instruction and data
765 * accesses/misses in hardware.
766 */
767static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
768 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
769 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
770 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
771 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
772 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
773 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
774 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
775};
776
777static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
778 [PERF_COUNT_HW_CACHE_OP_MAX]
779 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
780 [C(L1D)] = {
781 [C(OP_READ)] = {
782 [C(RESULT_ACCESS)] =
783 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
784 [C(RESULT_MISS)] =
785 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
786 },
787 [C(OP_WRITE)] = {
788 [C(RESULT_ACCESS)] =
789 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
790 [C(RESULT_MISS)] =
791 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
792 },
793 [C(OP_PREFETCH)] = {
794 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
795 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
796 },
797 },
798 [C(L1I)] = {
799 [C(OP_READ)] = {
800 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
801 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
802 },
803 [C(OP_WRITE)] = {
804 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
805 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
806 },
807 [C(OP_PREFETCH)] = {
808 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
809 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
810 },
811 },
812 [C(LL)] = {
813 [C(OP_READ)] = {
814 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
815 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
816 },
817 [C(OP_WRITE)] = {
818 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
819 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
820 },
821 [C(OP_PREFETCH)] = {
822 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
823 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
824 },
825 },
826 [C(DTLB)] = {
827 /*
828 * The ARM performance counters can count micro DTLB misses,
829 * micro ITLB misses and main TLB misses. There isn't an event
830 * for TLB misses, so use the micro misses here and if users
831 * want the main TLB misses they can use a raw counter.
832 */
833 [C(OP_READ)] = {
834 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
835 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
836 },
837 [C(OP_WRITE)] = {
838 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
839 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
840 },
841 [C(OP_PREFETCH)] = {
842 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
843 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
844 },
845 },
846 [C(ITLB)] = {
847 [C(OP_READ)] = {
848 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
849 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
850 },
851 [C(OP_WRITE)] = {
852 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
853 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
854 },
855 [C(OP_PREFETCH)] = {
856 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
857 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
858 },
859 },
860 [C(BPU)] = {
861 [C(OP_READ)] = {
862 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
863 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
864 },
865 [C(OP_WRITE)] = {
866 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
867 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
868 },
869 [C(OP_PREFETCH)] = {
870 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
871 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
872 },
873 },
874};
875
876static inline unsigned long
877armv6_pmcr_read(void)
878{
879 u32 val;
880 asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val));
881 return val;
882}
883
884static inline void
885armv6_pmcr_write(unsigned long val)
886{
887 asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val));
888}
889
890#define ARMV6_PMCR_ENABLE (1 << 0)
891#define ARMV6_PMCR_CTR01_RESET (1 << 1)
892#define ARMV6_PMCR_CCOUNT_RESET (1 << 2)
893#define ARMV6_PMCR_CCOUNT_DIV (1 << 3)
894#define ARMV6_PMCR_COUNT0_IEN (1 << 4)
895#define ARMV6_PMCR_COUNT1_IEN (1 << 5)
896#define ARMV6_PMCR_CCOUNT_IEN (1 << 6)
897#define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8)
898#define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9)
899#define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10)
900#define ARMV6_PMCR_EVT_COUNT0_SHIFT 20
901#define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
902#define ARMV6_PMCR_EVT_COUNT1_SHIFT 12
903#define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
904
905#define ARMV6_PMCR_OVERFLOWED_MASK \
906 (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
907 ARMV6_PMCR_CCOUNT_OVERFLOW)
908
909static inline int
910armv6_pmcr_has_overflowed(unsigned long pmcr)
911{
912 return (pmcr & ARMV6_PMCR_OVERFLOWED_MASK);
913}
914
915static inline int
916armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
917 enum armv6_counters counter)
918{
919 int ret = 0;
920
921 if (ARMV6_CYCLE_COUNTER == counter)
922 ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
923 else if (ARMV6_COUNTER0 == counter)
924 ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
925 else if (ARMV6_COUNTER1 == counter)
926 ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
927 else
928 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
929
930 return ret;
931}
932
933static inline u32
934armv6pmu_read_counter(int counter)
935{
936 unsigned long value = 0;
937
938 if (ARMV6_CYCLE_COUNTER == counter)
939 asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value));
940 else if (ARMV6_COUNTER0 == counter)
941 asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value));
942 else if (ARMV6_COUNTER1 == counter)
943 asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value));
944 else
945 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
946
947 return value;
948}
949
950static inline void
951armv6pmu_write_counter(int counter,
952 u32 value)
953{
954 if (ARMV6_CYCLE_COUNTER == counter)
955 asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value));
956 else if (ARMV6_COUNTER0 == counter)
957 asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value));
958 else if (ARMV6_COUNTER1 == counter)
959 asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value));
960 else
961 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
962}
963
964void
965armv6pmu_enable_event(struct hw_perf_event *hwc,
966 int idx)
967{
968 unsigned long val, mask, evt, flags;
969
970 if (ARMV6_CYCLE_COUNTER == idx) {
971 mask = 0;
972 evt = ARMV6_PMCR_CCOUNT_IEN;
973 } else if (ARMV6_COUNTER0 == idx) {
974 mask = ARMV6_PMCR_EVT_COUNT0_MASK;
975 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
976 ARMV6_PMCR_COUNT0_IEN;
977 } else if (ARMV6_COUNTER1 == idx) {
978 mask = ARMV6_PMCR_EVT_COUNT1_MASK;
979 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
980 ARMV6_PMCR_COUNT1_IEN;
981 } else {
982 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
983 return;
984 }
985
986 /*
987 * Mask out the current event and set the counter to count the event
988 * that we're interested in.
989 */
990 spin_lock_irqsave(&pmu_lock, flags);
991 val = armv6_pmcr_read();
992 val &= ~mask;
993 val |= evt;
994 armv6_pmcr_write(val);
995 spin_unlock_irqrestore(&pmu_lock, flags);
996}
997
998static irqreturn_t
999armv6pmu_handle_irq(int irq_num,
1000 void *dev)
1001{
1002 unsigned long pmcr = armv6_pmcr_read();
1003 struct perf_sample_data data;
1004 struct cpu_hw_events *cpuc;
1005 struct pt_regs *regs;
1006 int idx;
1007
1008 if (!armv6_pmcr_has_overflowed(pmcr))
1009 return IRQ_NONE;
1010
1011 regs = get_irq_regs();
1012
1013 /*
1014 * The interrupts are cleared by writing the overflow flags back to
1015 * the control register. All of the other bits don't have any effect
1016 * if they are rewritten, so write the whole value back.
1017 */
1018 armv6_pmcr_write(pmcr);
1019
dc1d628a 1020 perf_sample_data_init(&data, 0);
1b8873a0
JI		 1021
1022 cpuc = &__get_cpu_var(cpu_hw_events);
1023 for (idx = 0; idx <= armpmu->num_events; ++idx) {
1024 struct perf_event *event = cpuc->events[idx];
1025 struct hw_perf_event *hwc;
1026
1027 if (!test_bit(idx, cpuc->active_mask))
1028 continue;
1029
1030 /*
1031 * We have a single interrupt for all counters. Check that
1032 * each counter has overflowed before we process it.
1033 */
1034 if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
1035 continue;
1036
1037 hwc = &event->hw;
1038 armpmu_event_update(event, hwc, idx);
1039 data.period = event->hw.last_period;
1040 if (!armpmu_event_set_period(event, hwc, idx))
1041 continue;
1042
1043 if (perf_event_overflow(event, 0, &data, regs))
1044 armpmu->disable(hwc, idx);
1045 }
1046
1047 /*
1048 * Handle the pending perf events.
1049 *
1050 * Note: this call *must* be run with interrupts enabled. For
1051 * platforms that can have the PMU interrupts raised as a PMI, this
1052 * will not work.
1053 */
1054 perf_event_do_pending();
1055
1056 return IRQ_HANDLED;
1057}
1058
1059static void
1060armv6pmu_start(void)
1061{
1062 unsigned long flags, val;
1063
1064 spin_lock_irqsave(&pmu_lock, flags);
1065 val = armv6_pmcr_read();
1066 val |= ARMV6_PMCR_ENABLE;
1067 armv6_pmcr_write(val);
1068 spin_unlock_irqrestore(&pmu_lock, flags);
1069}
1070
1071void
1072armv6pmu_stop(void)
1073{
1074 unsigned long flags, val;
1075
1076 spin_lock_irqsave(&pmu_lock, flags);
1077 val = armv6_pmcr_read();
1078 val &= ~ARMV6_PMCR_ENABLE;
1079 armv6_pmcr_write(val);
1080 spin_unlock_irqrestore(&pmu_lock, flags);
1081}
1082
1083static inline int
1084armv6pmu_event_map(int config)
1085{
1086 int mapping = armv6_perf_map[config];
1087 if (HW_OP_UNSUPPORTED == mapping)
1088 mapping = -EOPNOTSUPP;
1089 return mapping;
1090}
1091
1092static inline int
1093armv6mpcore_pmu_event_map(int config)
1094{
1095 int mapping = armv6mpcore_perf_map[config];
1096 if (HW_OP_UNSUPPORTED == mapping)
1097 mapping = -EOPNOTSUPP;
1098 return mapping;
1099}
1100
1101static u64
1102armv6pmu_raw_event(u64 config)
1103{
1104 return config & 0xff;
1105}
1106
1107static int
1108armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
1109 struct hw_perf_event *event)
1110{
1111 /* Always place a cycle counter into the cycle counter. */
1112 if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
1113 if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
1114 return -EAGAIN;
1115
1116 return ARMV6_CYCLE_COUNTER;
1117 } else {
1118 /*
1119 * For anything other than a cycle counter, try and use
1120 * counter0 and counter1.
1121 */
1122 if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) {
1123 return ARMV6_COUNTER1;
1124 }
1125
1126 if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) {
1127 return ARMV6_COUNTER0;
1128 }
1129
1130 /* The counters are all in use. */
1131 return -EAGAIN;
1132 }
1133}
1134
1135static void
1136armv6pmu_disable_event(struct hw_perf_event *hwc,
1137 int idx)
1138{
1139 unsigned long val, mask, evt, flags;
1140
1141 if (ARMV6_CYCLE_COUNTER == idx) {
1142 mask = ARMV6_PMCR_CCOUNT_IEN;
1143 evt = 0;
1144 } else if (ARMV6_COUNTER0 == idx) {
1145 mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
1146 evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
1147 } else if (ARMV6_COUNTER1 == idx) {
1148 mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
1149 evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
1150 } else {
1151 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1152 return;
1153 }
1154
1155 /*
1156 * Mask out the current event and set the counter to count the number
1157 * of ETM bus signal assertion cycles. The external reporting should
1158 * be disabled and so this should never increment.
1159 */
1160 spin_lock_irqsave(&pmu_lock, flags);
1161 val = armv6_pmcr_read();
1162 val &= ~mask;
1163 val |= evt;
1164 armv6_pmcr_write(val);
1165 spin_unlock_irqrestore(&pmu_lock, flags);
1166}
1167
1168static void
1169armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
1170 int idx)
1171{
1172 unsigned long val, mask, flags, evt = 0;
1173
1174 if (ARMV6_CYCLE_COUNTER == idx) {
1175 mask = ARMV6_PMCR_CCOUNT_IEN;
1176 } else if (ARMV6_COUNTER0 == idx) {
1177 mask = ARMV6_PMCR_COUNT0_IEN;
1178 } else if (ARMV6_COUNTER1 == idx) {
1179 mask = ARMV6_PMCR_COUNT1_IEN;
1180 } else {
1181 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1182 return;
1183 }
1184
1185 /*
1186 * Unlike UP ARMv6, we don't have a way of stopping the counters. We
1187 * simply disable the interrupt reporting.
1188 */
1189 spin_lock_irqsave(&pmu_lock, flags);
1190 val = armv6_pmcr_read();
1191 val &= ~mask;
1192 val |= evt;
1193 armv6_pmcr_write(val);
1194 spin_unlock_irqrestore(&pmu_lock, flags);
1195}
1196
1197static const struct arm_pmu armv6pmu = {
181193f3 1198 .id = ARM_PERF_PMU_ID_V6,
1b8873a0
JI		 1199 .handle_irq = armv6pmu_handle_irq,
1200 .enable = armv6pmu_enable_event,
1201 .disable = armv6pmu_disable_event,
1202 .event_map = armv6pmu_event_map,
1203 .raw_event = armv6pmu_raw_event,
1204 .read_counter = armv6pmu_read_counter,
1205 .write_counter = armv6pmu_write_counter,
1206 .get_event_idx = armv6pmu_get_event_idx,
1207 .start = armv6pmu_start,
1208 .stop = armv6pmu_stop,
1209 .num_events = 3,
1210 .max_period = (1LLU << 32) - 1,
1211};
1212
1213/*
1214 * ARMv6mpcore is almost identical to single core ARMv6 with the exception
1215 * that some of the events have different enumerations and that there is no
1216 * *hack* to stop the programmable counters. To stop the counters we simply
1217 * disable the interrupt reporting and update the event. When unthrottling we
1218 * reset the period and enable the interrupt reporting.
1219 */
1220static const struct arm_pmu armv6mpcore_pmu = {
181193f3 1221 .id = ARM_PERF_PMU_ID_V6MP,
1b8873a0
JI		 1222 .handle_irq = armv6pmu_handle_irq,
1223 .enable = armv6pmu_enable_event,
1224 .disable = armv6mpcore_pmu_disable_event,
1225 .event_map = armv6mpcore_pmu_event_map,
1226 .raw_event = armv6pmu_raw_event,
1227 .read_counter = armv6pmu_read_counter,
1228 .write_counter = armv6pmu_write_counter,
1229 .get_event_idx = armv6pmu_get_event_idx,
1230 .start = armv6pmu_start,
1231 .stop = armv6pmu_stop,
1232 .num_events = 3,
1233 .max_period = (1LLU << 32) - 1,
1234};
1235
796d1295
JP		 1236/*
1237 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
1238 *
1239 * Copied from ARMv6 code, with the low level code inspired
1240 * by the ARMv7 Oprofile code.
1241 *
1242 * Cortex-A8 has up to 4 configurable performance counters and
1243 * a single cycle counter.
1244 * Cortex-A9 has up to 31 configurable performance counters and
1245 * a single cycle counter.
1246 *
1247 * All counters can be enabled/disabled and IRQ masked separately. The cycle
1248 * counter and all 4 performance counters together can be reset separately.
1249 */
1250
796d1295
JP		 1251/* Common ARMv7 event types */
1252enum armv7_perf_types {
1253 ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
1254 ARMV7_PERFCTR_IFETCH_MISS = 0x01,
1255 ARMV7_PERFCTR_ITLB_MISS = 0x02,
1256 ARMV7_PERFCTR_DCACHE_REFILL = 0x03,
1257 ARMV7_PERFCTR_DCACHE_ACCESS = 0x04,
1258 ARMV7_PERFCTR_DTLB_REFILL = 0x05,
1259 ARMV7_PERFCTR_DREAD = 0x06,
1260 ARMV7_PERFCTR_DWRITE = 0x07,
1261
1262 ARMV7_PERFCTR_EXC_TAKEN = 0x09,
1263 ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
1264 ARMV7_PERFCTR_CID_WRITE = 0x0B,
1265 /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
1266 * It counts:
1267 * - all branch instructions,
1268 * - instructions that explicitly write the PC,
1269 * - exception generating instructions.
1270 */
1271 ARMV7_PERFCTR_PC_WRITE = 0x0C,
1272 ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
1273 ARMV7_PERFCTR_UNALIGNED_ACCESS = 0x0F,
1274 ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
1275 ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
1276
1277 ARMV7_PERFCTR_PC_BRANCH_MIS_USED = 0x12,
1278
1279 ARMV7_PERFCTR_CPU_CYCLES = 0xFF
1280};
1281
1282/* ARMv7 Cortex-A8 specific event types */
1283enum armv7_a8_perf_types {
1284 ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
1285
1286 ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
1287
1288 ARMV7_PERFCTR_WRITE_BUFFER_FULL = 0x40,
1289 ARMV7_PERFCTR_L2_STORE_MERGED = 0x41,
1290 ARMV7_PERFCTR_L2_STORE_BUFF = 0x42,
1291 ARMV7_PERFCTR_L2_ACCESS = 0x43,
1292 ARMV7_PERFCTR_L2_CACH_MISS = 0x44,
1293 ARMV7_PERFCTR_AXI_READ_CYCLES = 0x45,
1294 ARMV7_PERFCTR_AXI_WRITE_CYCLES = 0x46,
1295 ARMV7_PERFCTR_MEMORY_REPLAY = 0x47,
1296 ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY = 0x48,
1297 ARMV7_PERFCTR_L1_DATA_MISS = 0x49,
1298 ARMV7_PERFCTR_L1_INST_MISS = 0x4A,
1299 ARMV7_PERFCTR_L1_DATA_COLORING = 0x4B,
1300 ARMV7_PERFCTR_L1_NEON_DATA = 0x4C,
1301 ARMV7_PERFCTR_L1_NEON_CACH_DATA = 0x4D,
1302 ARMV7_PERFCTR_L2_NEON = 0x4E,
1303 ARMV7_PERFCTR_L2_NEON_HIT = 0x4F,
1304 ARMV7_PERFCTR_L1_INST = 0x50,
1305 ARMV7_PERFCTR_PC_RETURN_MIS_PRED = 0x51,
1306 ARMV7_PERFCTR_PC_BRANCH_FAILED = 0x52,
1307 ARMV7_PERFCTR_PC_BRANCH_TAKEN = 0x53,
1308 ARMV7_PERFCTR_PC_BRANCH_EXECUTED = 0x54,
1309 ARMV7_PERFCTR_OP_EXECUTED = 0x55,
1310 ARMV7_PERFCTR_CYCLES_INST_STALL = 0x56,
1311 ARMV7_PERFCTR_CYCLES_INST = 0x57,
1312 ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL = 0x58,
1313 ARMV7_PERFCTR_CYCLES_NEON_INST_STALL = 0x59,
1314 ARMV7_PERFCTR_NEON_CYCLES = 0x5A,
1315
1316 ARMV7_PERFCTR_PMU0_EVENTS = 0x70,
1317 ARMV7_PERFCTR_PMU1_EVENTS = 0x71,
1318 ARMV7_PERFCTR_PMU_EVENTS = 0x72,
1319};
1320
1321/* ARMv7 Cortex-A9 specific event types */
1322enum armv7_a9_perf_types {
1323 ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC = 0x40,
1324 ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC = 0x41,
1325 ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC = 0x42,
1326
1327 ARMV7_PERFCTR_COHERENT_LINE_MISS = 0x50,
1328 ARMV7_PERFCTR_COHERENT_LINE_HIT = 0x51,
1329
1330 ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES = 0x60,
1331 ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES = 0x61,
1332 ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
1333 ARMV7_PERFCTR_STREX_EXECUTED_PASSED = 0x63,
1334 ARMV7_PERFCTR_STREX_EXECUTED_FAILED = 0x64,
1335 ARMV7_PERFCTR_DATA_EVICTION = 0x65,
1336 ARMV7_PERFCTR_ISSUE_STAGE_NO_INST = 0x66,
1337 ARMV7_PERFCTR_ISSUE_STAGE_EMPTY = 0x67,
1338 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE = 0x68,
1339
1340 ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
1341
1342 ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST = 0x70,
1343 ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
1344 ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST = 0x72,
1345 ARMV7_PERFCTR_FP_EXECUTED_INST = 0x73,
1346 ARMV7_PERFCTR_NEON_EXECUTED_INST = 0x74,
1347
1348 ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
1349 ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES = 0x81,
1350 ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES = 0x82,
1351 ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES = 0x83,
1352 ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES = 0x84,
1353 ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES = 0x85,
1354 ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES = 0x86,
1355
1356 ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES = 0x8A,
1357 ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
1358
1359 ARMV7_PERFCTR_ISB_INST = 0x90,
1360 ARMV7_PERFCTR_DSB_INST = 0x91,
1361 ARMV7_PERFCTR_DMB_INST = 0x92,
1362 ARMV7_PERFCTR_EXT_INTERRUPTS = 0x93,
1363
1364 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED = 0xA0,
1365 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED = 0xA1,
1366 ARMV7_PERFCTR_PLE_FIFO_FLUSH = 0xA2,
1367 ARMV7_PERFCTR_PLE_RQST_COMPLETED = 0xA3,
1368 ARMV7_PERFCTR_PLE_FIFO_OVERFLOW = 0xA4,
1369 ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5
1370};
1371
1372/*
1373 * Cortex-A8 HW events mapping
1374 *
1375 * The hardware events that we support. We do support cache operations but
1376 * we have harvard caches and no way to combine instruction and data
1377 * accesses/misses in hardware.
1378 */
1379static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
1380 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
1381 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
1382 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
1383 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
1384 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
1385 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1386 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
1387};
1388
1389static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
1390 [PERF_COUNT_HW_CACHE_OP_MAX]
1391 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1392 [C(L1D)] = {
1393 /*
1394 * The performance counters don't differentiate between read
1395 * and write accesses/misses so this isn't strictly correct,
1396 * but it's the best we can do. Writes and reads get
1397 * combined.
1398 */
1399 [C(OP_READ)] = {
1400 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1401 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1402 },
1403 [C(OP_WRITE)] = {
1404 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1405 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1406 },
1407 [C(OP_PREFETCH)] = {
1408 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1409 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1410 },
1411 },
1412 [C(L1I)] = {
1413 [C(OP_READ)] = {
1414 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST,
1415 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS,
1416 },
1417 [C(OP_WRITE)] = {
1418 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST,
1419 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS,
1420 },
1421 [C(OP_PREFETCH)] = {
1422 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1423 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1424 },
1425 },
1426 [C(LL)] = {
1427 [C(OP_READ)] = {
1428 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS,
1429 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS,
1430 },
1431 [C(OP_WRITE)] = {
1432 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS,
1433 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS,
1434 },
1435 [C(OP_PREFETCH)] = {
1436 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1437 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1438 },
1439 },
1440 [C(DTLB)] = {
1441 /*
1442 * Only ITLB misses and DTLB refills are supported.
1443 * If users want the DTLB refills misses a raw counter
1444 * must be used.
1445 */
1446 [C(OP_READ)] = {
1447 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1448 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1449 },
1450 [C(OP_WRITE)] = {
1451 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1452 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1453 },
1454 [C(OP_PREFETCH)] = {
1455 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1456 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1457 },
1458 },
1459 [C(ITLB)] = {
1460 [C(OP_READ)] = {
1461 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1462 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1463 },
1464 [C(OP_WRITE)] = {
1465 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1466 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1467 },
1468 [C(OP_PREFETCH)] = {
1469 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1470 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1471 },
1472 },
1473 [C(BPU)] = {
1474 [C(OP_READ)] = {
1475 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1476 [C(RESULT_MISS)]
1477 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1478 },
1479 [C(OP_WRITE)] = {
1480 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1481 [C(RESULT_MISS)]
1482 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1483 },
1484 [C(OP_PREFETCH)] = {
1485 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1486 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1487 },
1488 },
1489};
1490
1491/*
1492 * Cortex-A9 HW events mapping
1493 */
1494static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
1495 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
1496 [PERF_COUNT_HW_INSTRUCTIONS] =
1497 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
1498 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT,
1499 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS,
1500 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
1501 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1502 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
1503};
1504
1505static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
1506 [PERF_COUNT_HW_CACHE_OP_MAX]
1507 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1508 [C(L1D)] = {
1509 /*
1510 * The performance counters don't differentiate between read
1511 * and write accesses/misses so this isn't strictly correct,
1512 * but it's the best we can do. Writes and reads get
1513 * combined.
1514 */
1515 [C(OP_READ)] = {
1516 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1517 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1518 },
1519 [C(OP_WRITE)] = {
1520 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1521 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1522 },
1523 [C(OP_PREFETCH)] = {
1524 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1525 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1526 },
1527 },
1528 [C(L1I)] = {
1529 [C(OP_READ)] = {
1530 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1531 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
1532 },
1533 [C(OP_WRITE)] = {
1534 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1535 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
1536 },
1537 [C(OP_PREFETCH)] = {
1538 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1539 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1540 },
1541 },
1542 [C(LL)] = {
1543 [C(OP_READ)] = {
1544 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1545 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1546 },
1547 [C(OP_WRITE)] = {
1548 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1549 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1550 },
1551 [C(OP_PREFETCH)] = {
1552 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1553 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1554 },
1555 },
1556 [C(DTLB)] = {
1557 /*
1558 * Only ITLB misses and DTLB refills are supported.
1559 * If users want the DTLB refills misses a raw counter
1560 * must be used.
1561 */
1562 [C(OP_READ)] = {
1563 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1564 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1565 },
1566 [C(OP_WRITE)] = {
1567 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1568 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1569 },
1570 [C(OP_PREFETCH)] = {
1571 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1572 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1573 },
1574 },
1575 [C(ITLB)] = {
1576 [C(OP_READ)] = {
1577 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1578 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1579 },
1580 [C(OP_WRITE)] = {
1581 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1582 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1583 },
1584 [C(OP_PREFETCH)] = {
1585 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1586 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1587 },
1588 },
1589 [C(BPU)] = {
1590 [C(OP_READ)] = {
1591 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1592 [C(RESULT_MISS)]
1593 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1594 },
1595 [C(OP_WRITE)] = {
1596 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1597 [C(RESULT_MISS)]
1598 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1599 },
1600 [C(OP_PREFETCH)] = {
1601 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1602 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1603 },
1604 },
1605};
1606
1607/*
1608 * Perf Events counters
1609 */
1610enum armv7_counters {
1611 ARMV7_CYCLE_COUNTER = 1, /* Cycle counter */
1612 ARMV7_COUNTER0 = 2, /* First event counter */
1613};
1614
1615/*
1616 * The cycle counter is ARMV7_CYCLE_COUNTER.
1617 * The first event counter is ARMV7_COUNTER0.
1618 * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
1619 */
1620#define ARMV7_COUNTER_LAST (ARMV7_COUNTER0 + armpmu->num_events - 1)
1621
1622/*
1623 * ARMv7 low level PMNC access
1624 */
1625
1626/*
1627 * Per-CPU PMNC: config reg
1628 */
1629#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
1630#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
1631#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
1632#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
1633#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */
1634#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
1635#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */
1636#define ARMV7_PMNC_N_MASK 0x1f
1637#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
1638
1639/*
1640 * Available counters
1641 */
1642#define ARMV7_CNT0 0 /* First event counter */
1643#define ARMV7_CCNT 31 /* Cycle counter */
1644
1645/* Perf Event to low level counters mapping */
1646#define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
1647
1648/*
1649 * CNTENS: counters enable reg
1650 */
1651#define ARMV7_CNTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1652#define ARMV7_CNTENS_C (1 << ARMV7_CCNT)
1653
1654/*
1655 * CNTENC: counters disable reg
1656 */
1657#define ARMV7_CNTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1658#define ARMV7_CNTENC_C (1 << ARMV7_CCNT)
1659
1660/*
1661 * INTENS: counters overflow interrupt enable reg
1662 */
1663#define ARMV7_INTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1664#define ARMV7_INTENS_C (1 << ARMV7_CCNT)
1665
1666/*
1667 * INTENC: counters overflow interrupt disable reg
1668 */
1669#define ARMV7_INTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1670#define ARMV7_INTENC_C (1 << ARMV7_CCNT)
1671
1672/*
1673 * EVTSEL: Event selection reg
1674 */
d10fca9f 1675#define ARMV7_EVTSEL_MASK 0xff /* Mask for writable bits */
796d1295
JP		 1676
1677/*
1678 * SELECT: Counter selection reg
1679 */
1680#define ARMV7_SELECT_MASK 0x1f /* Mask for writable bits */
1681
1682/*
1683 * FLAG: counters overflow flag status reg
1684 */
1685#define ARMV7_FLAG_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1686#define ARMV7_FLAG_C (1 << ARMV7_CCNT)
1687#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
1688#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK
1689
1690static inline unsigned long armv7_pmnc_read(void)
1691{
1692 u32 val;
1693 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
1694 return val;
1695}
1696
1697static inline void armv7_pmnc_write(unsigned long val)
1698{
1699 val &= ARMV7_PMNC_MASK;
1700 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
1701}
1702
1703static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
1704{
1705 return pmnc & ARMV7_OVERFLOWED_MASK;
1706}
1707
1708static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
1709 enum armv7_counters counter)
1710{
1711 int ret;
1712
1713 if (counter == ARMV7_CYCLE_COUNTER)
1714 ret = pmnc & ARMV7_FLAG_C;
1715 else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
1716 ret = pmnc & ARMV7_FLAG_P(counter);
1717 else
1718 pr_err("CPU%u checking wrong counter %d overflow status\n",
1719 smp_processor_id(), counter);
1720
1721 return ret;
1722}
1723
1724static inline int armv7_pmnc_select_counter(unsigned int idx)
1725{
1726 u32 val;
1727
1728 if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
1729 pr_err("CPU%u selecting wrong PMNC counter"
1730 " %d\n", smp_processor_id(), idx);
1731 return -1;
1732 }
1733
1734 val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
1735 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
1736
1737 return idx;
1738}
1739
1740static inline u32 armv7pmu_read_counter(int idx)
1741{
1742 unsigned long value = 0;
1743
1744 if (idx == ARMV7_CYCLE_COUNTER)
1745 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
1746 else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
1747 if (armv7_pmnc_select_counter(idx) == idx)
1748 asm volatile("mrc p15, 0, %0, c9, c13, 2"
1749 : "=r" (value));
1750 } else
1751 pr_err("CPU%u reading wrong counter %d\n",
1752 smp_processor_id(), idx);
1753
1754 return value;
1755}
1756
1757static inline void armv7pmu_write_counter(int idx, u32 value)
1758{
1759 if (idx == ARMV7_CYCLE_COUNTER)
1760 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
1761 else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
1762 if (armv7_pmnc_select_counter(idx) == idx)
1763 asm volatile("mcr p15, 0, %0, c9, c13, 2"
1764 : : "r" (value));
1765 } else
1766 pr_err("CPU%u writing wrong counter %d\n",
1767 smp_processor_id(), idx);
1768}
1769
1770static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
1771{
1772 if (armv7_pmnc_select_counter(idx) == idx) {
1773 val &= ARMV7_EVTSEL_MASK;
1774 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
1775 }
1776}
1777
1778static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
1779{
1780 u32 val;
1781
1782 if ((idx != ARMV7_CYCLE_COUNTER) &&
1783 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1784 pr_err("CPU%u enabling wrong PMNC counter"
1785 " %d\n", smp_processor_id(), idx);
1786 return -1;
1787 }
1788
1789 if (idx == ARMV7_CYCLE_COUNTER)
1790 val = ARMV7_CNTENS_C;
1791 else
1792 val = ARMV7_CNTENS_P(idx);
1793
1794 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
1795
1796 return idx;
1797}
1798
1799static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
1800{
1801 u32 val;
1802
1803
1804 if ((idx != ARMV7_CYCLE_COUNTER) &&
1805 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1806 pr_err("CPU%u disabling wrong PMNC counter"
1807 " %d\n", smp_processor_id(), idx);
1808 return -1;
1809 }
1810
1811 if (idx == ARMV7_CYCLE_COUNTER)
1812 val = ARMV7_CNTENC_C;
1813 else
1814 val = ARMV7_CNTENC_P(idx);
1815
1816 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
1817
1818 return idx;
1819}
1820
1821static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
1822{
1823 u32 val;
1824
1825 if ((idx != ARMV7_CYCLE_COUNTER) &&
1826 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1827 pr_err("CPU%u enabling wrong PMNC counter"
1828 " interrupt enable %d\n", smp_processor_id(), idx);
1829 return -1;
1830 }
1831
1832 if (idx == ARMV7_CYCLE_COUNTER)
1833 val = ARMV7_INTENS_C;
1834 else
1835 val = ARMV7_INTENS_P(idx);
1836
1837 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
1838
1839 return idx;
1840}
1841
1842static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
1843{
1844 u32 val;
1845
1846 if ((idx != ARMV7_CYCLE_COUNTER) &&
1847 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1848 pr_err("CPU%u disabling wrong PMNC counter"
1849 " interrupt enable %d\n", smp_processor_id(), idx);
1850 return -1;
1851 }
1852
1853 if (idx == ARMV7_CYCLE_COUNTER)
1854 val = ARMV7_INTENC_C;
1855 else
1856 val = ARMV7_INTENC_P(idx);
1857
1858 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
1859
1860 return idx;
1861}
1862
1863static inline u32 armv7_pmnc_getreset_flags(void)
1864{
1865 u32 val;
1866
1867 /* Read */
1868 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
1869
1870 /* Write to clear flags */
1871 val &= ARMV7_FLAG_MASK;
1872 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
1873
1874 return val;
1875}
1876
1877#ifdef DEBUG
1878static void armv7_pmnc_dump_regs(void)
1879{
1880 u32 val;
1881 unsigned int cnt;
1882
1883 printk(KERN_INFO "PMNC registers dump:\n");
1884
1885 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
1886 printk(KERN_INFO "PMNC =0x%08x\n", val);
1887
1888 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
1889 printk(KERN_INFO "CNTENS=0x%08x\n", val);
1890
1891 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
1892 printk(KERN_INFO "INTENS=0x%08x\n", val);
1893
1894 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
1895 printk(KERN_INFO "FLAGS =0x%08x\n", val);
1896
1897 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
1898 printk(KERN_INFO "SELECT=0x%08x\n", val);
1899
1900 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
1901 printk(KERN_INFO "CCNT =0x%08x\n", val);
1902
1903 for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
1904 armv7_pmnc_select_counter(cnt);
1905 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
1906 printk(KERN_INFO "CNT[%d] count =0x%08x\n",
1907 cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
1908 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
1909 printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
1910 cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
1911 }
1912}
1913#endif
1914
1915void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
1916{
1917 unsigned long flags;
1918
1919 /*
1920 * Enable counter and interrupt, and set the counter to count
1921 * the event that we're interested in.
1922 */
1923 spin_lock_irqsave(&pmu_lock, flags);
1924
1925 /*
1926 * Disable counter
1927 */
1928 armv7_pmnc_disable_counter(idx);
1929
1930 /*
1931 * Set event (if destined for PMNx counters)
1932 * We don't need to set the event if it's a cycle count
1933 */
1934 if (idx != ARMV7_CYCLE_COUNTER)
1935 armv7_pmnc_write_evtsel(idx, hwc->config_base);
1936
1937 /*
1938 * Enable interrupt for this counter
1939 */
1940 armv7_pmnc_enable_intens(idx);
1941
1942 /*
1943 * Enable counter
1944 */
1945 armv7_pmnc_enable_counter(idx);
1946
1947 spin_unlock_irqrestore(&pmu_lock, flags);
1948}
1949
1950static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
1951{
1952 unsigned long flags;
1953
1954 /*
1955 * Disable counter and interrupt
1956 */
1957 spin_lock_irqsave(&pmu_lock, flags);
1958
1959 /*
1960 * Disable counter
1961 */
1962 armv7_pmnc_disable_counter(idx);
1963
1964 /*
1965 * Disable interrupt for this counter
1966 */
1967 armv7_pmnc_disable_intens(idx);
1968
1969 spin_unlock_irqrestore(&pmu_lock, flags);
1970}
1971
1972static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
1973{
1974 unsigned long pmnc;
1975 struct perf_sample_data data;
1976 struct cpu_hw_events *cpuc;
1977 struct pt_regs *regs;
1978 int idx;
1979
1980 /*
1981 * Get and reset the IRQ flags
1982 */
1983 pmnc = armv7_pmnc_getreset_flags();
1984
1985 /*
1986 * Did an overflow occur?
1987 */
1988 if (!armv7_pmnc_has_overflowed(pmnc))
1989 return IRQ_NONE;
1990
1991 /*
1992 * Handle the counter(s) overflow(s)
1993 */
1994 regs = get_irq_regs();
1995
dc1d628a 1996 perf_sample_data_init(&data, 0);
796d1295
JP		 1997
1998 cpuc = &__get_cpu_var(cpu_hw_events);
1999 for (idx = 0; idx <= armpmu->num_events; ++idx) {
2000 struct perf_event *event = cpuc->events[idx];
2001 struct hw_perf_event *hwc;
2002
2003 if (!test_bit(idx, cpuc->active_mask))
2004 continue;
2005
2006 /*
2007 * We have a single interrupt for all counters. Check that
2008 * each counter has overflowed before we process it.
2009 */
2010 if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
2011 continue;
2012
2013 hwc = &event->hw;
2014 armpmu_event_update(event, hwc, idx);
2015 data.period = event->hw.last_period;
2016 if (!armpmu_event_set_period(event, hwc, idx))
2017 continue;
2018
2019 if (perf_event_overflow(event, 0, &data, regs))
2020 armpmu->disable(hwc, idx);
2021 }
2022
2023 /*
2024 * Handle the pending perf events.
2025 *
2026 * Note: this call *must* be run with interrupts enabled. For
2027 * platforms that can have the PMU interrupts raised as a PMI, this
2028 * will not work.
2029 */
2030 perf_event_do_pending();
2031
2032 return IRQ_HANDLED;
2033}
2034
2035static void armv7pmu_start(void)
2036{
2037 unsigned long flags;
2038
2039 spin_lock_irqsave(&pmu_lock, flags);
2040 /* Enable all counters */
2041 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
2042 spin_unlock_irqrestore(&pmu_lock, flags);
2043}
2044
2045static void armv7pmu_stop(void)
2046{
2047 unsigned long flags;
2048
2049 spin_lock_irqsave(&pmu_lock, flags);
2050 /* Disable all counters */
2051 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
2052 spin_unlock_irqrestore(&pmu_lock, flags);
2053}
2054
2055static inline int armv7_a8_pmu_event_map(int config)
2056{
2057 int mapping = armv7_a8_perf_map[config];
2058 if (HW_OP_UNSUPPORTED == mapping)
2059 mapping = -EOPNOTSUPP;
2060 return mapping;
2061}
2062
2063static inline int armv7_a9_pmu_event_map(int config)
2064{
2065 int mapping = armv7_a9_perf_map[config];
2066 if (HW_OP_UNSUPPORTED == mapping)
2067 mapping = -EOPNOTSUPP;
2068 return mapping;
2069}
2070
2071static u64 armv7pmu_raw_event(u64 config)
2072{
2073 return config & 0xff;
2074}
2075
2076static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
2077 struct hw_perf_event *event)
2078{
2079 int idx;
2080
2081 /* Always place a cycle counter into the cycle counter. */
2082 if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
2083 if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
2084 return -EAGAIN;
2085
2086 return ARMV7_CYCLE_COUNTER;
2087 } else {
2088 /*
2089 * For anything other than a cycle counter, try and use
2090 * the events counters
2091 */
2092 for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
2093 if (!test_and_set_bit(idx, cpuc->used_mask))
2094 return idx;
2095 }
2096
2097 /* The counters are all in use. */
2098 return -EAGAIN;
2099 }
2100}
2101
2102static struct arm_pmu armv7pmu = {
2103 .handle_irq = armv7pmu_handle_irq,
2104 .enable = armv7pmu_enable_event,
2105 .disable = armv7pmu_disable_event,
2106 .raw_event = armv7pmu_raw_event,
2107 .read_counter = armv7pmu_read_counter,
2108 .write_counter = armv7pmu_write_counter,
2109 .get_event_idx = armv7pmu_get_event_idx,
2110 .start = armv7pmu_start,
2111 .stop = armv7pmu_stop,
2112 .max_period = (1LLU << 32) - 1,
2113};
2114
2115static u32 __init armv7_reset_read_pmnc(void)
2116{
2117 u32 nb_cnt;
2118
2119 /* Initialize & Reset PMNC: C and P bits */
2120 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
2121
2122 /* Read the nb of CNTx counters supported from PMNC */
2123 nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
2124
2125 /* Add the CPU cycles counter and return */
2126 return nb_cnt + 1;
2127}
2128
49e6a32f
WD		 2129/*
2130 * ARMv5 [xscale] Performance counter handling code.
2131 *
2132 * Based on xscale OProfile code.
2133 *
2134 * There are two variants of the xscale PMU that we support:
2135 * - xscale1pmu: 2 event counters and a cycle counter
2136 * - xscale2pmu: 4 event counters and a cycle counter
2137 * The two variants share event definitions, but have different
2138 * PMU structures.
2139 */
2140
2141enum xscale_perf_types {
2142 XSCALE_PERFCTR_ICACHE_MISS = 0x00,
2143 XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01,
2144 XSCALE_PERFCTR_DATA_STALL = 0x02,
2145 XSCALE_PERFCTR_ITLB_MISS = 0x03,
2146 XSCALE_PERFCTR_DTLB_MISS = 0x04,
2147 XSCALE_PERFCTR_BRANCH = 0x05,
2148 XSCALE_PERFCTR_BRANCH_MISS = 0x06,
2149 XSCALE_PERFCTR_INSTRUCTION = 0x07,
2150 XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08,
2151 XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
2152 XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A,
2153 XSCALE_PERFCTR_DCACHE_MISS = 0x0B,
2154 XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C,
2155 XSCALE_PERFCTR_PC_CHANGED = 0x0D,
2156 XSCALE_PERFCTR_BCU_REQUEST = 0x10,
2157 XSCALE_PERFCTR_BCU_FULL = 0x11,
2158 XSCALE_PERFCTR_BCU_DRAIN = 0x12,
2159 XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14,
2160 XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15,
2161 XSCALE_PERFCTR_RMW = 0x16,
2162 /* XSCALE_PERFCTR_CCNT is not hardware defined */
2163 XSCALE_PERFCTR_CCNT = 0xFE,
2164 XSCALE_PERFCTR_UNUSED = 0xFF,
2165};
2166
2167enum xscale_counters {
2168 XSCALE_CYCLE_COUNTER = 1,
2169 XSCALE_COUNTER0,
2170 XSCALE_COUNTER1,
2171 XSCALE_COUNTER2,
2172 XSCALE_COUNTER3,
2173};
2174
2175static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
2176 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
2177 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
2178 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
2179 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
2180 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
2181 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
2182 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
2183};
2184
2185static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
2186 [PERF_COUNT_HW_CACHE_OP_MAX]
2187 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2188 [C(L1D)] = {
2189 [C(OP_READ)] = {
2190 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
2191 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
2192 },
2193 [C(OP_WRITE)] = {
2194 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
2195 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
2196 },
2197 [C(OP_PREFETCH)] = {
2198 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2199 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2200 },
2201 },
2202 [C(L1I)] = {
2203 [C(OP_READ)] = {
2204 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2205 [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
2206 },
2207 [C(OP_WRITE)] = {
2208 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2209 [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
2210 },
2211 [C(OP_PREFETCH)] = {
2212 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2213 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2214 },
2215 },
2216 [C(LL)] = {
2217 [C(OP_READ)] = {
2218 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2219 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2220 },
2221 [C(OP_WRITE)] = {
2222 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2223 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2224 },
2225 [C(OP_PREFETCH)] = {
2226 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2227 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2228 },
2229 },
2230 [C(DTLB)] = {
2231 [C(OP_READ)] = {
2232 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2233 [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
2234 },
2235 [C(OP_WRITE)] = {
2236 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2237 [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
2238 },
2239 [C(OP_PREFETCH)] = {
2240 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2241 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2242 },
2243 },
2244 [C(ITLB)] = {
2245 [C(OP_READ)] = {
2246 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2247 [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
2248 },
2249 [C(OP_WRITE)] = {
2250 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2251 [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
2252 },
2253 [C(OP_PREFETCH)] = {
2254 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2255 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2256 },
2257 },
2258 [C(BPU)] = {
2259 [C(OP_READ)] = {
2260 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2261 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2262 },
2263 [C(OP_WRITE)] = {
2264 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2265 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2266 },
2267 [C(OP_PREFETCH)] = {
2268 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2269 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2270 },
2271 },
2272};
2273
2274#define XSCALE_PMU_ENABLE 0x001
2275#define XSCALE_PMN_RESET 0x002
2276#define XSCALE_CCNT_RESET 0x004
2277#define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET)
2278#define XSCALE_PMU_CNT64 0x008
2279
2280static inline int
2281xscalepmu_event_map(int config)
2282{
2283 int mapping = xscale_perf_map[config];
2284 if (HW_OP_UNSUPPORTED == mapping)
2285 mapping = -EOPNOTSUPP;
2286 return mapping;
2287}
2288
2289static u64
2290xscalepmu_raw_event(u64 config)
2291{
2292 return config & 0xff;
2293}
2294
2295#define XSCALE1_OVERFLOWED_MASK 0x700
2296#define XSCALE1_CCOUNT_OVERFLOW 0x400
2297#define XSCALE1_COUNT0_OVERFLOW 0x100
2298#define XSCALE1_COUNT1_OVERFLOW 0x200
2299#define XSCALE1_CCOUNT_INT_EN 0x040
2300#define XSCALE1_COUNT0_INT_EN 0x010
2301#define XSCALE1_COUNT1_INT_EN 0x020
2302#define XSCALE1_COUNT0_EVT_SHFT 12
2303#define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
2304#define XSCALE1_COUNT1_EVT_SHFT 20
2305#define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
2306
2307static inline u32
2308xscale1pmu_read_pmnc(void)
2309{
2310 u32 val;
2311 asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
2312 return val;
2313}
2314
2315static inline void
2316xscale1pmu_write_pmnc(u32 val)
2317{
2318 /* upper 4bits and 7, 11 are write-as-0 */
2319 val &= 0xffff77f;
2320 asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
2321}
2322
2323static inline int
2324xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
2325 enum xscale_counters counter)
2326{
2327 int ret = 0;
2328
2329 switch (counter) {
2330 case XSCALE_CYCLE_COUNTER:
2331 ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
2332 break;
2333 case XSCALE_COUNTER0:
2334 ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
2335 break;
2336 case XSCALE_COUNTER1:
2337 ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
2338 break;
2339 default:
2340 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
2341 }
2342
2343 return ret;
2344}
2345
2346static irqreturn_t
2347xscale1pmu_handle_irq(int irq_num, void *dev)
2348{
2349 unsigned long pmnc;
2350 struct perf_sample_data data;
2351 struct cpu_hw_events *cpuc;
2352 struct pt_regs *regs;
2353 int idx;
2354
2355 /*
2356 * NOTE: there's an A stepping erratum that states if an overflow
2357 * bit already exists and another occurs, the previous
2358 * Overflow bit gets cleared. There's no workaround.
2359 * Fixed in B stepping or later.
2360 */
2361 pmnc = xscale1pmu_read_pmnc();
2362
2363 /*
2364 * Write the value back to clear the overflow flags. Overflow
2365 * flags remain in pmnc for use below. We also disable the PMU
2366 * while we process the interrupt.
2367 */
2368 xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
2369
2370 if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
2371 return IRQ_NONE;
2372
2373 regs = get_irq_regs();
2374
2375 perf_sample_data_init(&data, 0);
2376
2377 cpuc = &__get_cpu_var(cpu_hw_events);
2378 for (idx = 0; idx <= armpmu->num_events; ++idx) {
2379 struct perf_event *event = cpuc->events[idx];
2380 struct hw_perf_event *hwc;
2381
2382 if (!test_bit(idx, cpuc->active_mask))
2383 continue;
2384
2385 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
2386 continue;
2387
2388 hwc = &event->hw;
2389 armpmu_event_update(event, hwc, idx);
2390 data.period = event->hw.last_period;
2391 if (!armpmu_event_set_period(event, hwc, idx))
2392 continue;
2393
2394 if (perf_event_overflow(event, 0, &data, regs))
2395 armpmu->disable(hwc, idx);
2396 }
2397
2398 perf_event_do_pending();
2399
2400 /*
2401 * Re-enable the PMU.
2402 */
2403 pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
2404 xscale1pmu_write_pmnc(pmnc);
2405
2406 return IRQ_HANDLED;
2407}
2408
2409static void
2410xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
2411{
2412 unsigned long val, mask, evt, flags;
2413
2414 switch (idx) {
2415 case XSCALE_CYCLE_COUNTER:
2416 mask = 0;
2417 evt = XSCALE1_CCOUNT_INT_EN;
2418 break;
2419 case XSCALE_COUNTER0:
2420 mask = XSCALE1_COUNT0_EVT_MASK;
2421 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
2422 XSCALE1_COUNT0_INT_EN;
2423 break;
2424 case XSCALE_COUNTER1:
2425 mask = XSCALE1_COUNT1_EVT_MASK;
2426 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
2427 XSCALE1_COUNT1_INT_EN;
2428 break;
2429 default:
2430 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2431 return;
2432 }
2433
2434 spin_lock_irqsave(&pmu_lock, flags);
2435 val = xscale1pmu_read_pmnc();
2436 val &= ~mask;
2437 val |= evt;
2438 xscale1pmu_write_pmnc(val);
2439 spin_unlock_irqrestore(&pmu_lock, flags);
2440}
2441
2442static void
2443xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
2444{
2445 unsigned long val, mask, evt, flags;
2446
2447 switch (idx) {
2448 case XSCALE_CYCLE_COUNTER:
2449 mask = XSCALE1_CCOUNT_INT_EN;
2450 evt = 0;
2451 break;
2452 case XSCALE_COUNTER0:
2453 mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
2454 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
2455 break;
2456 case XSCALE_COUNTER1:
2457 mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
2458 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
2459 break;
2460 default:
2461 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2462 return;
2463 }
2464
2465 spin_lock_irqsave(&pmu_lock, flags);
2466 val = xscale1pmu_read_pmnc();
2467 val &= ~mask;
2468 val |= evt;
2469 xscale1pmu_write_pmnc(val);
2470 spin_unlock_irqrestore(&pmu_lock, flags);
2471}
2472
2473static int
2474xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc,
2475 struct hw_perf_event *event)
2476{
2477 if (XSCALE_PERFCTR_CCNT == event->config_base) {
2478 if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
2479 return -EAGAIN;
2480
2481 return XSCALE_CYCLE_COUNTER;
2482 } else {
2483 if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) {
2484 return XSCALE_COUNTER1;
2485 }
2486
2487 if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) {
2488 return XSCALE_COUNTER0;
2489 }
2490
2491 return -EAGAIN;
2492 }
2493}
2494
2495static void
2496xscale1pmu_start(void)
2497{
2498 unsigned long flags, val;
2499
2500 spin_lock_irqsave(&pmu_lock, flags);
2501 val = xscale1pmu_read_pmnc();
2502 val |= XSCALE_PMU_ENABLE;
2503 xscale1pmu_write_pmnc(val);
2504 spin_unlock_irqrestore(&pmu_lock, flags);
2505}
2506
2507static void
2508xscale1pmu_stop(void)
2509{
2510 unsigned long flags, val;
2511
2512 spin_lock_irqsave(&pmu_lock, flags);
2513 val = xscale1pmu_read_pmnc();
2514 val &= ~XSCALE_PMU_ENABLE;
2515 xscale1pmu_write_pmnc(val);
2516 spin_unlock_irqrestore(&pmu_lock, flags);
2517}
2518
2519static inline u32
2520xscale1pmu_read_counter(int counter)
2521{
2522 u32 val = 0;
2523
2524 switch (counter) {
2525 case XSCALE_CYCLE_COUNTER:
2526 asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
2527 break;
2528 case XSCALE_COUNTER0:
2529 asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
2530 break;
2531 case XSCALE_COUNTER1:
2532 asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
2533 break;
2534 }
2535
2536 return val;
2537}
2538
2539static inline void
2540xscale1pmu_write_counter(int counter, u32 val)
2541{
2542 switch (counter) {
2543 case XSCALE_CYCLE_COUNTER:
2544 asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
2545 break;
2546 case XSCALE_COUNTER0:
2547 asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
2548 break;
2549 case XSCALE_COUNTER1:
2550 asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
2551 break;
2552 }
2553}
2554
2555static const struct arm_pmu xscale1pmu = {
2556 .id = ARM_PERF_PMU_ID_XSCALE1,
2557 .handle_irq = xscale1pmu_handle_irq,
2558 .enable = xscale1pmu_enable_event,
2559 .disable = xscale1pmu_disable_event,
2560 .event_map = xscalepmu_event_map,
2561 .raw_event = xscalepmu_raw_event,
2562 .read_counter = xscale1pmu_read_counter,
2563 .write_counter = xscale1pmu_write_counter,
2564 .get_event_idx = xscale1pmu_get_event_idx,
2565 .start = xscale1pmu_start,
2566 .stop = xscale1pmu_stop,
2567 .num_events = 3,
2568 .max_period = (1LLU << 32) - 1,
2569};
2570
2571#define XSCALE2_OVERFLOWED_MASK 0x01f
2572#define XSCALE2_CCOUNT_OVERFLOW 0x001
2573#define XSCALE2_COUNT0_OVERFLOW 0x002
2574#define XSCALE2_COUNT1_OVERFLOW 0x004
2575#define XSCALE2_COUNT2_OVERFLOW 0x008
2576#define XSCALE2_COUNT3_OVERFLOW 0x010
2577#define XSCALE2_CCOUNT_INT_EN 0x001
2578#define XSCALE2_COUNT0_INT_EN 0x002
2579#define XSCALE2_COUNT1_INT_EN 0x004
2580#define XSCALE2_COUNT2_INT_EN 0x008
2581#define XSCALE2_COUNT3_INT_EN 0x010
2582#define XSCALE2_COUNT0_EVT_SHFT 0
2583#define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
2584#define XSCALE2_COUNT1_EVT_SHFT 8
2585#define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
2586#define XSCALE2_COUNT2_EVT_SHFT 16
2587#define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
2588#define XSCALE2_COUNT3_EVT_SHFT 24
2589#define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
2590
2591static inline u32
2592xscale2pmu_read_pmnc(void)
2593{
2594 u32 val;
2595 asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
2596 /* bits 1-2 and 4-23 are read-unpredictable */
2597 return val & 0xff000009;
2598}
2599
2600static inline void
2601xscale2pmu_write_pmnc(u32 val)
2602{
2603 /* bits 4-23 are write-as-0, 24-31 are write ignored */
2604 val &= 0xf;
2605 asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
2606}
2607
2608static inline u32
2609xscale2pmu_read_overflow_flags(void)
2610{
2611 u32 val;
2612 asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
2613 return val;
2614}
2615
2616static inline void
2617xscale2pmu_write_overflow_flags(u32 val)
2618{
2619 asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
2620}
2621
2622static inline u32
2623xscale2pmu_read_event_select(void)
2624{
2625 u32 val;
2626 asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
2627 return val;
2628}
2629
2630static inline void
2631xscale2pmu_write_event_select(u32 val)
2632{
2633 asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
2634}
2635
2636static inline u32
2637xscale2pmu_read_int_enable(void)
2638{
2639 u32 val;
2640 asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
2641 return val;
2642}
2643
2644static void
2645xscale2pmu_write_int_enable(u32 val)
2646{
2647 asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
2648}
2649
2650static inline int
2651xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
2652 enum xscale_counters counter)
2653{
2654 int ret = 0;
2655
2656 switch (counter) {
2657 case XSCALE_CYCLE_COUNTER:
2658 ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
2659 break;
2660 case XSCALE_COUNTER0:
2661 ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
2662 break;
2663 case XSCALE_COUNTER1:
2664 ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
2665 break;
2666 case XSCALE_COUNTER2:
2667 ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
2668 break;
2669 case XSCALE_COUNTER3:
2670 ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
2671 break;
2672 default:
2673 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
2674 }
2675
2676 return ret;
2677}
2678
2679static irqreturn_t
2680xscale2pmu_handle_irq(int irq_num, void *dev)
2681{
2682 unsigned long pmnc, of_flags;
2683 struct perf_sample_data data;
2684 struct cpu_hw_events *cpuc;
2685 struct pt_regs *regs;
2686 int idx;
2687
2688 /* Disable the PMU. */
2689 pmnc = xscale2pmu_read_pmnc();
2690 xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
2691
2692 /* Check the overflow flag register. */
2693 of_flags = xscale2pmu_read_overflow_flags();
2694 if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
2695 return IRQ_NONE;
2696
2697 /* Clear the overflow bits. */
2698 xscale2pmu_write_overflow_flags(of_flags);
2699
2700 regs = get_irq_regs();
2701
2702 perf_sample_data_init(&data, 0);
2703
2704 cpuc = &__get_cpu_var(cpu_hw_events);
2705 for (idx = 0; idx <= armpmu->num_events; ++idx) {
2706 struct perf_event *event = cpuc->events[idx];
2707 struct hw_perf_event *hwc;
2708
2709 if (!test_bit(idx, cpuc->active_mask))
2710 continue;
2711
2712 if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
2713 continue;
2714
2715 hwc = &event->hw;
2716 armpmu_event_update(event, hwc, idx);
2717 data.period = event->hw.last_period;
2718 if (!armpmu_event_set_period(event, hwc, idx))
2719 continue;
2720
2721 if (perf_event_overflow(event, 0, &data, regs))
2722 armpmu->disable(hwc, idx);
2723 }
2724
2725 perf_event_do_pending();
2726
2727 /*
2728 * Re-enable the PMU.
2729 */
2730 pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
2731 xscale2pmu_write_pmnc(pmnc);
2732
2733 return IRQ_HANDLED;
2734}
2735
2736static void
2737xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
2738{
2739 unsigned long flags, ien, evtsel;
2740
2741 ien = xscale2pmu_read_int_enable();
2742 evtsel = xscale2pmu_read_event_select();
2743
2744 switch (idx) {
2745 case XSCALE_CYCLE_COUNTER:
2746 ien |= XSCALE2_CCOUNT_INT_EN;
2747 break;
2748 case XSCALE_COUNTER0:
2749 ien |= XSCALE2_COUNT0_INT_EN;
2750 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
2751 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
2752 break;
2753 case XSCALE_COUNTER1:
2754 ien |= XSCALE2_COUNT1_INT_EN;
2755 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
2756 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
2757 break;
2758 case XSCALE_COUNTER2:
2759 ien |= XSCALE2_COUNT2_INT_EN;
2760 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
2761 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
2762 break;
2763 case XSCALE_COUNTER3:
2764 ien |= XSCALE2_COUNT3_INT_EN;
2765 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
2766 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
2767 break;
2768 default:
2769 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2770 return;
2771 }
2772
2773 spin_lock_irqsave(&pmu_lock, flags);
2774 xscale2pmu_write_event_select(evtsel);
2775 xscale2pmu_write_int_enable(ien);
2776 spin_unlock_irqrestore(&pmu_lock, flags);
2777}
2778
2779static void
2780xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
2781{
2782 unsigned long flags, ien, evtsel;
2783
2784 ien = xscale2pmu_read_int_enable();
2785 evtsel = xscale2pmu_read_event_select();
2786
2787 switch (idx) {
2788 case XSCALE_CYCLE_COUNTER:
2789 ien &= ~XSCALE2_CCOUNT_INT_EN;
2790 break;
2791 case XSCALE_COUNTER0:
2792 ien &= ~XSCALE2_COUNT0_INT_EN;
2793 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
2794 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
2795 break;
2796 case XSCALE_COUNTER1:
2797 ien &= ~XSCALE2_COUNT1_INT_EN;
2798 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
2799 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
2800 break;
2801 case XSCALE_COUNTER2:
2802 ien &= ~XSCALE2_COUNT2_INT_EN;
2803 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
2804 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
2805 break;
2806 case XSCALE_COUNTER3:
2807 ien &= ~XSCALE2_COUNT3_INT_EN;
2808 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
2809 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
2810 break;
2811 default:
2812 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2813 return;
2814 }
2815
2816 spin_lock_irqsave(&pmu_lock, flags);
2817 xscale2pmu_write_event_select(evtsel);
2818 xscale2pmu_write_int_enable(ien);
2819 spin_unlock_irqrestore(&pmu_lock, flags);
2820}
2821
2822static int
2823xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc,
2824 struct hw_perf_event *event)
2825{
2826 int idx = xscale1pmu_get_event_idx(cpuc, event);
2827 if (idx >= 0)
2828 goto out;
2829
2830 if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
2831 idx = XSCALE_COUNTER3;
2832 else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
2833 idx = XSCALE_COUNTER2;
2834out:
2835 return idx;
2836}
2837
2838static void
2839xscale2pmu_start(void)
2840{
2841 unsigned long flags, val;
2842
2843 spin_lock_irqsave(&pmu_lock, flags);
2844 val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
2845 val |= XSCALE_PMU_ENABLE;
2846 xscale2pmu_write_pmnc(val);
2847 spin_unlock_irqrestore(&pmu_lock, flags);
2848}
2849
2850static void
2851xscale2pmu_stop(void)
2852{
2853 unsigned long flags, val;
2854
2855 spin_lock_irqsave(&pmu_lock, flags);
2856 val = xscale2pmu_read_pmnc();
2857 val &= ~XSCALE_PMU_ENABLE;
2858 xscale2pmu_write_pmnc(val);
2859 spin_unlock_irqrestore(&pmu_lock, flags);
2860}
2861
2862static inline u32
2863xscale2pmu_read_counter(int counter)
2864{
2865 u32 val = 0;
2866
2867 switch (counter) {
2868 case XSCALE_CYCLE_COUNTER:
2869 asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
2870 break;
2871 case XSCALE_COUNTER0:
2872 asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
2873 break;
2874 case XSCALE_COUNTER1:
2875 asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
2876 break;
2877 case XSCALE_COUNTER2:
2878 asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
2879 break;
2880 case XSCALE_COUNTER3:
2881 asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
2882 break;
2883 }
2884
2885 return val;
2886}
2887
2888static inline void
2889xscale2pmu_write_counter(int counter, u32 val)
2890{
2891 switch (counter) {
2892 case XSCALE_CYCLE_COUNTER:
2893 asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
2894 break;
2895 case XSCALE_COUNTER0:
2896 asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
2897 break;
2898 case XSCALE_COUNTER1:
2899 asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
2900 break;
2901 case XSCALE_COUNTER2:
2902 asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
2903 break;
2904 case XSCALE_COUNTER3:
2905 asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
2906 break;
2907 }
2908}
2909
2910static const struct arm_pmu xscale2pmu = {
2911 .id = ARM_PERF_PMU_ID_XSCALE2,
2912 .handle_irq = xscale2pmu_handle_irq,
2913 .enable = xscale2pmu_enable_event,
2914 .disable = xscale2pmu_disable_event,
2915 .event_map = xscalepmu_event_map,
2916 .raw_event = xscalepmu_raw_event,
2917 .read_counter = xscale2pmu_read_counter,
2918 .write_counter = xscale2pmu_write_counter,
2919 .get_event_idx = xscale2pmu_get_event_idx,
2920 .start = xscale2pmu_start,
2921 .stop = xscale2pmu_stop,
2922 .num_events = 5,
2923 .max_period = (1LLU << 32) - 1,
2924};
2925
1b8873a0
JI		 2926static int __init
2927init_hw_perf_events(void)
2928{
2929 unsigned long cpuid = read_cpuid_id();
2930 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
2931 unsigned long part_number = (cpuid & 0xFFF0);
2932
49e6a32f 2933 /* ARM Ltd CPUs. */
1b8873a0
JI		 2934 if (0x41 == implementor) {
2935 switch (part_number) {
2936 case 0xB360: /* ARM1136 */
2937 case 0xB560: /* ARM1156 */
2938 case 0xB760: /* ARM1176 */
2939 armpmu = &armv6pmu;
2940 memcpy(armpmu_perf_cache_map, armv6_perf_cache_map,
2941 sizeof(armv6_perf_cache_map));
2942 perf_max_events = armv6pmu.num_events;
2943 break;
2944 case 0xB020: /* ARM11mpcore */
2945 armpmu = &armv6mpcore_pmu;
2946 memcpy(armpmu_perf_cache_map,
2947 armv6mpcore_perf_cache_map,
2948 sizeof(armv6mpcore_perf_cache_map));
2949 perf_max_events = armv6mpcore_pmu.num_events;
2950 break;
796d1295 2951 case 0xC080: /* Cortex-A8 */
181193f3 2952 armv7pmu.id = ARM_PERF_PMU_ID_CA8;
796d1295
JP		 2953 memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map,
2954 sizeof(armv7_a8_perf_cache_map));
2955 armv7pmu.event_map = armv7_a8_pmu_event_map;
2956 armpmu = &armv7pmu;
2957
2958 /* Reset PMNC and read the nb of CNTx counters
2959 supported */
2960 armv7pmu.num_events = armv7_reset_read_pmnc();
2961 perf_max_events = armv7pmu.num_events;
2962 break;
2963 case 0xC090: /* Cortex-A9 */
181193f3 2964 armv7pmu.id = ARM_PERF_PMU_ID_CA9;
796d1295
JP		 2965 memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map,
2966 sizeof(armv7_a9_perf_cache_map));
2967 armv7pmu.event_map = armv7_a9_pmu_event_map;
2968 armpmu = &armv7pmu;
2969
2970 /* Reset PMNC and read the nb of CNTx counters
2971 supported */
2972 armv7pmu.num_events = armv7_reset_read_pmnc();
2973 perf_max_events = armv7pmu.num_events;
2974 break;
49e6a32f
WD		 2975 }
2976 /* Intel CPUs [xscale]. */
2977 } else if (0x69 == implementor) {
2978 part_number = (cpuid >> 13) & 0x7;
2979 switch (part_number) {
2980 case 1:
2981 armpmu = &xscale1pmu;
2982 memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
2983 sizeof(xscale_perf_cache_map));
2984 perf_max_events = xscale1pmu.num_events;
2985 break;
2986 case 2:
2987 armpmu = &xscale2pmu;
2988 memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
2989 sizeof(xscale_perf_cache_map));
2990 perf_max_events = xscale2pmu.num_events;
2991 break;
1b8873a0
JI		 2992 }
2993 }
2994
49e6a32f 2995 if (armpmu) {
796d1295 2996 pr_info("enabled with %s PMU driver, %d counters available\n",
49e6a32f
WD		 2997 arm_pmu_names[armpmu->id], armpmu->num_events);
2998 } else {
2999 pr_info("no hardware support available\n");
3000 perf_max_events = -1;
3001 }
1b8873a0
JI		 3002
3003 return 0;
3004}
3005arch_initcall(init_hw_perf_events);
3006
3007/*
3008 * Callchain handling code.
3009 */
3010static inline void
3011callchain_store(struct perf_callchain_entry *entry,
3012 u64 ip)
3013{
3014 if (entry->nr < PERF_MAX_STACK_DEPTH)
3015 entry->ip[entry->nr++] = ip;
3016}
3017
3018/*
3019 * The registers we're interested in are at the end of the variable
3020 * length saved register structure. The fp points at the end of this
3021 * structure so the address of this struct is:
3022 * (struct frame_tail *)(xxx->fp)-1
3023 *
3024 * This code has been adapted from the ARM OProfile support.
3025 */
3026struct frame_tail {
3027 struct frame_tail *fp;
3028 unsigned long sp;
3029 unsigned long lr;
3030} __attribute__((packed));
3031
3032/*
3033 * Get the return address for a single stackframe and return a pointer to the
3034 * next frame tail.
3035 */
3036static struct frame_tail *
3037user_backtrace(struct frame_tail *tail,
3038 struct perf_callchain_entry *entry)
3039{
3040 struct frame_tail buftail;
3041
3042 /* Also check accessibility of one struct frame_tail beyond */
3043 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
3044 return NULL;
3045 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
3046 return NULL;
3047
3048 callchain_store(entry, buftail.lr);
3049
3050 /*
3051 * Frame pointers should strictly progress back up the stack
3052 * (towards higher addresses).
3053 */
3054 if (tail >= buftail.fp)
3055 return NULL;
3056
3057 return buftail.fp - 1;
3058}
3059
3060static void
3061perf_callchain_user(struct pt_regs *regs,
3062 struct perf_callchain_entry *entry)
3063{
3064 struct frame_tail *tail;
3065
3066 callchain_store(entry, PERF_CONTEXT_USER);
3067
3068 if (!user_mode(regs))
3069 regs = task_pt_regs(current);
3070
3071 tail = (struct frame_tail *)regs->ARM_fp - 1;
3072
3073 while (tail && !((unsigned long)tail & 0x3))
3074 tail = user_backtrace(tail, entry);
3075}
3076
3077/*
3078 * Gets called by walk_stackframe() for every stackframe. This will be called
3079 * whist unwinding the stackframe and is like a subroutine return so we use
3080 * the PC.
3081 */
3082static int
3083callchain_trace(struct stackframe *fr,
3084 void *data)
3085{
3086 struct perf_callchain_entry *entry = data;
3087 callchain_store(entry, fr->pc);
3088 return 0;
3089}
3090
3091static void
3092perf_callchain_kernel(struct pt_regs *regs,
3093 struct perf_callchain_entry *entry)
3094{
3095 struct stackframe fr;
3096
3097 callchain_store(entry, PERF_CONTEXT_KERNEL);
3098 fr.fp = regs->ARM_fp;
3099 fr.sp = regs->ARM_sp;
3100 fr.lr = regs->ARM_lr;
3101 fr.pc = regs->ARM_pc;
3102 walk_stackframe(&fr, callchain_trace, entry);
3103}
3104
3105static void
3106perf_do_callchain(struct pt_regs *regs,
3107 struct perf_callchain_entry *entry)
3108{
3109 int is_user;
3110
3111 if (!regs)
3112 return;
3113
3114 is_user = user_mode(regs);
3115
3116 if (!current || !current->pid)
3117 return;
3118
3119 if (is_user && current->state != TASK_RUNNING)
3120 return;
3121
3122 if (!is_user)
3123 perf_callchain_kernel(regs, entry);
3124
3125 if (current->mm)
3126 perf_callchain_user(regs, entry);
3127}
3128
3129static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
3130
3131struct perf_callchain_entry *
3132perf_callchain(struct pt_regs *regs)
3133{
3134 struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry);
3135
3136 entry->nr = 0;
3137 perf_do_callchain(regs, entry);
3138 return entry;
3139}
Linux kernel - Deliverables
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