Commit | Line | Data |
---|---|---|
1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
1b8873a0 | 15 | #include <linux/kernel.h> |
49c006b9 | 16 | #include <linux/platform_device.h> |
7be2958e | 17 | #include <linux/pm_runtime.h> |
5505b206 | 18 | #include <linux/uaccess.h> |
1b8873a0 | 19 | |
1b8873a0 JI |
20 | #include <asm/irq_regs.h> |
21 | #include <asm/pmu.h> | |
22 | #include <asm/stacktrace.h> | |
23 | ||
1b8873a0 | 24 | static int |
e1f431b5 MR |
25 | armpmu_map_cache_event(const unsigned (*cache_map) |
26 | [PERF_COUNT_HW_CACHE_MAX] | |
27 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
28 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
29 | u64 config) | |
1b8873a0 JI |
30 | { |
31 | unsigned int cache_type, cache_op, cache_result, ret; | |
32 | ||
33 | cache_type = (config >> 0) & 0xff; | |
34 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
35 | return -EINVAL; | |
36 | ||
37 | cache_op = (config >> 8) & 0xff; | |
38 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
39 | return -EINVAL; | |
40 | ||
41 | cache_result = (config >> 16) & 0xff; | |
42 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
43 | return -EINVAL; | |
44 | ||
e1f431b5 | 45 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
46 | |
47 | if (ret == CACHE_OP_UNSUPPORTED) | |
48 | return -ENOENT; | |
49 | ||
50 | return ret; | |
51 | } | |
52 | ||
84fee97a | 53 | static int |
6dbc0029 | 54 | armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 55 | { |
d9f96635 SB |
56 | int mapping; |
57 | ||
58 | if (config >= PERF_COUNT_HW_MAX) | |
59 | return -EINVAL; | |
60 | ||
61 | mapping = (*event_map)[config]; | |
e1f431b5 | 62 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; |
84fee97a WD |
63 | } |
64 | ||
65 | static int | |
e1f431b5 | 66 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 67 | { |
e1f431b5 MR |
68 | return (int)(config & raw_event_mask); |
69 | } | |
70 | ||
6dbc0029 WD |
71 | int |
72 | armpmu_map_event(struct perf_event *event, | |
73 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
74 | const unsigned (*cache_map) | |
75 | [PERF_COUNT_HW_CACHE_MAX] | |
76 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
77 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
78 | u32 raw_event_mask) | |
e1f431b5 MR |
79 | { |
80 | u64 config = event->attr.config; | |
81 | ||
82 | switch (event->attr.type) { | |
83 | case PERF_TYPE_HARDWARE: | |
6dbc0029 | 84 | return armpmu_map_hw_event(event_map, config); |
e1f431b5 MR |
85 | case PERF_TYPE_HW_CACHE: |
86 | return armpmu_map_cache_event(cache_map, config); | |
87 | case PERF_TYPE_RAW: | |
88 | return armpmu_map_raw_event(raw_event_mask, config); | |
89 | } | |
90 | ||
91 | return -ENOENT; | |
84fee97a WD |
92 | } |
93 | ||
ed6f2a52 | 94 | int armpmu_event_set_period(struct perf_event *event) |
1b8873a0 | 95 | { |
8a16b34e | 96 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 97 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 98 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
99 | s64 period = hwc->sample_period; |
100 | int ret = 0; | |
101 | ||
3581fe0e WD |
102 | /* The period may have been changed by PERF_EVENT_IOC_PERIOD */ |
103 | if (unlikely(period != hwc->last_period)) | |
104 | left = period - (hwc->last_period - left); | |
105 | ||
1b8873a0 JI |
106 | if (unlikely(left <= -period)) { |
107 | left = period; | |
e7850595 | 108 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
109 | hwc->last_period = period; |
110 | ret = 1; | |
111 | } | |
112 | ||
113 | if (unlikely(left <= 0)) { | |
114 | left += period; | |
e7850595 | 115 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
116 | hwc->last_period = period; |
117 | ret = 1; | |
118 | } | |
119 | ||
120 | if (left > (s64)armpmu->max_period) | |
121 | left = armpmu->max_period; | |
122 | ||
e7850595 | 123 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 | 124 | |
ed6f2a52 | 125 | armpmu->write_counter(event, (u64)(-left) & 0xffffffff); |
1b8873a0 JI |
126 | |
127 | perf_event_update_userpage(event); | |
128 | ||
129 | return ret; | |
130 | } | |
131 | ||
ed6f2a52 | 132 | u64 armpmu_event_update(struct perf_event *event) |
1b8873a0 | 133 | { |
8a16b34e | 134 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 135 | struct hw_perf_event *hwc = &event->hw; |
a737823d | 136 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
137 | |
138 | again: | |
e7850595 | 139 | prev_raw_count = local64_read(&hwc->prev_count); |
ed6f2a52 | 140 | new_raw_count = armpmu->read_counter(event); |
1b8873a0 | 141 | |
e7850595 | 142 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
143 | new_raw_count) != prev_raw_count) |
144 | goto again; | |
145 | ||
57273471 | 146 | delta = (new_raw_count - prev_raw_count) & armpmu->max_period; |
1b8873a0 | 147 | |
e7850595 PZ |
148 | local64_add(delta, &event->count); |
149 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
150 | |
151 | return new_raw_count; | |
152 | } | |
153 | ||
154 | static void | |
a4eaf7f1 | 155 | armpmu_read(struct perf_event *event) |
1b8873a0 | 156 | { |
ed6f2a52 | 157 | armpmu_event_update(event); |
1b8873a0 JI |
158 | } |
159 | ||
160 | static void | |
a4eaf7f1 | 161 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 162 | { |
8a16b34e | 163 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
164 | struct hw_perf_event *hwc = &event->hw; |
165 | ||
a4eaf7f1 PZ |
166 | /* |
167 | * ARM pmu always has to update the counter, so ignore | |
168 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
169 | */ | |
170 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
ed6f2a52 SK |
171 | armpmu->disable(event); |
172 | armpmu_event_update(event); | |
a4eaf7f1 PZ |
173 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
174 | } | |
1b8873a0 JI |
175 | } |
176 | ||
ed6f2a52 | 177 | static void armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 178 | { |
8a16b34e | 179 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
180 | struct hw_perf_event *hwc = &event->hw; |
181 | ||
a4eaf7f1 PZ |
182 | /* |
183 | * ARM pmu always has to reprogram the period, so ignore | |
184 | * PERF_EF_RELOAD, see the comment below. | |
185 | */ | |
186 | if (flags & PERF_EF_RELOAD) | |
187 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
188 | ||
189 | hwc->state = 0; | |
1b8873a0 JI |
190 | /* |
191 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 192 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
193 | * may have been left counting. If we don't do this step then we may |
194 | * get an interrupt too soon or *way* too late if the overflow has | |
195 | * happened since disabling. | |
196 | */ | |
ed6f2a52 SK |
197 | armpmu_event_set_period(event); |
198 | armpmu->enable(event); | |
1b8873a0 JI |
199 | } |
200 | ||
a4eaf7f1 PZ |
201 | static void |
202 | armpmu_del(struct perf_event *event, int flags) | |
203 | { | |
8a16b34e | 204 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 205 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
a4eaf7f1 PZ |
206 | struct hw_perf_event *hwc = &event->hw; |
207 | int idx = hwc->idx; | |
208 | ||
a4eaf7f1 | 209 | armpmu_stop(event, PERF_EF_UPDATE); |
8be3f9a2 MR |
210 | hw_events->events[idx] = NULL; |
211 | clear_bit(idx, hw_events->used_mask); | |
a4eaf7f1 PZ |
212 | |
213 | perf_event_update_userpage(event); | |
214 | } | |
215 | ||
1b8873a0 | 216 | static int |
a4eaf7f1 | 217 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 218 | { |
8a16b34e | 219 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 220 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
1b8873a0 JI |
221 | struct hw_perf_event *hwc = &event->hw; |
222 | int idx; | |
223 | int err = 0; | |
224 | ||
33696fc0 | 225 | perf_pmu_disable(event->pmu); |
24cd7f54 | 226 | |
1b8873a0 | 227 | /* If we don't have a space for the counter then finish early. */ |
ed6f2a52 | 228 | idx = armpmu->get_event_idx(hw_events, event); |
1b8873a0 JI |
229 | if (idx < 0) { |
230 | err = idx; | |
231 | goto out; | |
232 | } | |
233 | ||
234 | /* | |
235 | * If there is an event in the counter we are going to use then make | |
236 | * sure it is disabled. | |
237 | */ | |
238 | event->hw.idx = idx; | |
ed6f2a52 | 239 | armpmu->disable(event); |
8be3f9a2 | 240 | hw_events->events[idx] = event; |
1b8873a0 | 241 | |
a4eaf7f1 PZ |
242 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
243 | if (flags & PERF_EF_START) | |
244 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
245 | |
246 | /* Propagate our changes to the userspace mapping. */ | |
247 | perf_event_update_userpage(event); | |
248 | ||
249 | out: | |
33696fc0 | 250 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
251 | return err; |
252 | } | |
253 | ||
1b8873a0 | 254 | static int |
8be3f9a2 | 255 | validate_event(struct pmu_hw_events *hw_events, |
1b8873a0 JI |
256 | struct perf_event *event) |
257 | { | |
8a16b34e | 258 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
7b9f72c6 | 259 | struct pmu *leader_pmu = event->group_leader->pmu; |
1b8873a0 | 260 | |
c95eb318 WD |
261 | if (is_software_event(event)) |
262 | return 1; | |
263 | ||
cb2d8b34 WD |
264 | if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF) |
265 | return 1; | |
266 | ||
267 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) | |
65b4711f | 268 | return 1; |
1b8873a0 | 269 | |
ed6f2a52 | 270 | return armpmu->get_event_idx(hw_events, event) >= 0; |
1b8873a0 JI |
271 | } |
272 | ||
273 | static int | |
274 | validate_group(struct perf_event *event) | |
275 | { | |
276 | struct perf_event *sibling, *leader = event->group_leader; | |
8be3f9a2 | 277 | struct pmu_hw_events fake_pmu; |
bce34d14 | 278 | DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS); |
1b8873a0 | 279 | |
bce34d14 WD |
280 | /* |
281 | * Initialise the fake PMU. We only need to populate the | |
282 | * used_mask for the purposes of validation. | |
283 | */ | |
284 | memset(fake_used_mask, 0, sizeof(fake_used_mask)); | |
285 | fake_pmu.used_mask = fake_used_mask; | |
1b8873a0 JI |
286 | |
287 | if (!validate_event(&fake_pmu, leader)) | |
aa2bc1ad | 288 | return -EINVAL; |
1b8873a0 JI |
289 | |
290 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
291 | if (!validate_event(&fake_pmu, sibling)) | |
aa2bc1ad | 292 | return -EINVAL; |
1b8873a0 JI |
293 | } |
294 | ||
295 | if (!validate_event(&fake_pmu, event)) | |
aa2bc1ad | 296 | return -EINVAL; |
1b8873a0 JI |
297 | |
298 | return 0; | |
299 | } | |
300 | ||
051f1b13 | 301 | static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) |
0e25a5c9 | 302 | { |
8a16b34e | 303 | struct arm_pmu *armpmu = (struct arm_pmu *) dev; |
a9356a04 MR |
304 | struct platform_device *plat_device = armpmu->plat_device; |
305 | struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); | |
0e25a5c9 | 306 | |
051f1b13 SK |
307 | if (plat && plat->handle_irq) |
308 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
309 | else | |
310 | return armpmu->handle_irq(irq, dev); | |
0e25a5c9 RV |
311 | } |
312 | ||
0b390e21 | 313 | static void |
8a16b34e | 314 | armpmu_release_hardware(struct arm_pmu *armpmu) |
0b390e21 | 315 | { |
ed6f2a52 | 316 | armpmu->free_irq(armpmu); |
051f1b13 | 317 | pm_runtime_put_sync(&armpmu->plat_device->dev); |
0b390e21 WD |
318 | } |
319 | ||
1b8873a0 | 320 | static int |
8a16b34e | 321 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
1b8873a0 | 322 | { |
051f1b13 | 323 | int err; |
a9356a04 | 324 | struct platform_device *pmu_device = armpmu->plat_device; |
1b8873a0 | 325 | |
e5a21327 WD |
326 | if (!pmu_device) |
327 | return -ENODEV; | |
328 | ||
7be2958e | 329 | pm_runtime_get_sync(&pmu_device->dev); |
ed6f2a52 | 330 | err = armpmu->request_irq(armpmu, armpmu_dispatch_irq); |
051f1b13 SK |
331 | if (err) { |
332 | armpmu_release_hardware(armpmu); | |
333 | return err; | |
49c006b9 | 334 | } |
1b8873a0 | 335 | |
0b390e21 | 336 | return 0; |
1b8873a0 JI |
337 | } |
338 | ||
1b8873a0 JI |
339 | static void |
340 | hw_perf_event_destroy(struct perf_event *event) | |
341 | { | |
8a16b34e | 342 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
03b7898d MR |
343 | atomic_t *active_events = &armpmu->active_events; |
344 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
345 | ||
346 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
8a16b34e | 347 | armpmu_release_hardware(armpmu); |
03b7898d | 348 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
349 | } |
350 | } | |
351 | ||
05d22fde WD |
352 | static int |
353 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
354 | { | |
355 | return attr->exclude_idle || attr->exclude_user || | |
356 | attr->exclude_kernel || attr->exclude_hv; | |
357 | } | |
358 | ||
1b8873a0 JI |
359 | static int |
360 | __hw_perf_event_init(struct perf_event *event) | |
361 | { | |
8a16b34e | 362 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 363 | struct hw_perf_event *hwc = &event->hw; |
9dcbf466 | 364 | int mapping; |
1b8873a0 | 365 | |
e1f431b5 | 366 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
367 | |
368 | if (mapping < 0) { | |
369 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
370 | event->attr.config); | |
371 | return mapping; | |
372 | } | |
373 | ||
05d22fde WD |
374 | /* |
375 | * We don't assign an index until we actually place the event onto | |
376 | * hardware. Use -1 to signify that we haven't decided where to put it | |
377 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
378 | * clever allocation or constraints checking at this point. | |
379 | */ | |
380 | hwc->idx = -1; | |
381 | hwc->config_base = 0; | |
382 | hwc->config = 0; | |
383 | hwc->event_base = 0; | |
384 | ||
1b8873a0 JI |
385 | /* |
386 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 387 | */ |
05d22fde WD |
388 | if ((!armpmu->set_event_filter || |
389 | armpmu->set_event_filter(hwc, &event->attr)) && | |
390 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
391 | pr_debug("ARM performance counters do not support " |
392 | "mode exclusion\n"); | |
fdeb8e35 | 393 | return -EOPNOTSUPP; |
1b8873a0 JI |
394 | } |
395 | ||
396 | /* | |
05d22fde | 397 | * Store the event encoding into the config_base field. |
1b8873a0 | 398 | */ |
05d22fde | 399 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
400 | |
401 | if (!hwc->sample_period) { | |
57273471 WD |
402 | /* |
403 | * For non-sampling runs, limit the sample_period to half | |
404 | * of the counter width. That way, the new counter value | |
405 | * is far less likely to overtake the previous one unless | |
406 | * you have some serious IRQ latency issues. | |
407 | */ | |
408 | hwc->sample_period = armpmu->max_period >> 1; | |
1b8873a0 | 409 | hwc->last_period = hwc->sample_period; |
e7850595 | 410 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
411 | } |
412 | ||
1b8873a0 | 413 | if (event->group_leader != event) { |
e595ede6 | 414 | if (validate_group(event) != 0) |
1b8873a0 JI |
415 | return -EINVAL; |
416 | } | |
417 | ||
9dcbf466 | 418 | return 0; |
1b8873a0 JI |
419 | } |
420 | ||
b0a873eb | 421 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 422 | { |
8a16b34e | 423 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 424 | int err = 0; |
03b7898d | 425 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 426 | |
2481c5fa SE |
427 | /* does not support taken branch sampling */ |
428 | if (has_branch_stack(event)) | |
429 | return -EOPNOTSUPP; | |
430 | ||
e1f431b5 | 431 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 432 | return -ENOENT; |
b0a873eb | 433 | |
1b8873a0 JI |
434 | event->destroy = hw_perf_event_destroy; |
435 | ||
03b7898d MR |
436 | if (!atomic_inc_not_zero(active_events)) { |
437 | mutex_lock(&armpmu->reserve_mutex); | |
438 | if (atomic_read(active_events) == 0) | |
8a16b34e | 439 | err = armpmu_reserve_hardware(armpmu); |
1b8873a0 JI |
440 | |
441 | if (!err) | |
03b7898d MR |
442 | atomic_inc(active_events); |
443 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
444 | } |
445 | ||
446 | if (err) | |
b0a873eb | 447 | return err; |
1b8873a0 JI |
448 | |
449 | err = __hw_perf_event_init(event); | |
450 | if (err) | |
451 | hw_perf_event_destroy(event); | |
452 | ||
b0a873eb | 453 | return err; |
1b8873a0 JI |
454 | } |
455 | ||
a4eaf7f1 | 456 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 457 | { |
8be3f9a2 | 458 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
8be3f9a2 | 459 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
7325eaec | 460 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
1b8873a0 | 461 | |
f4f38430 | 462 | if (enabled) |
ed6f2a52 | 463 | armpmu->start(armpmu); |
1b8873a0 JI |
464 | } |
465 | ||
a4eaf7f1 | 466 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 467 | { |
8a16b34e | 468 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
ed6f2a52 | 469 | armpmu->stop(armpmu); |
1b8873a0 JI |
470 | } |
471 | ||
7be2958e JH |
472 | #ifdef CONFIG_PM_RUNTIME |
473 | static int armpmu_runtime_resume(struct device *dev) | |
474 | { | |
475 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
476 | ||
477 | if (plat && plat->runtime_resume) | |
478 | return plat->runtime_resume(dev); | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | static int armpmu_runtime_suspend(struct device *dev) | |
484 | { | |
485 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
486 | ||
487 | if (plat && plat->runtime_suspend) | |
488 | return plat->runtime_suspend(dev); | |
489 | ||
490 | return 0; | |
491 | } | |
492 | #endif | |
493 | ||
6dbc0029 WD |
494 | const struct dev_pm_ops armpmu_dev_pm_ops = { |
495 | SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) | |
496 | }; | |
497 | ||
44d6b1fc | 498 | static void armpmu_init(struct arm_pmu *armpmu) |
03b7898d MR |
499 | { |
500 | atomic_set(&armpmu->active_events, 0); | |
501 | mutex_init(&armpmu->reserve_mutex); | |
8a16b34e MR |
502 | |
503 | armpmu->pmu = (struct pmu) { | |
504 | .pmu_enable = armpmu_enable, | |
505 | .pmu_disable = armpmu_disable, | |
506 | .event_init = armpmu_event_init, | |
507 | .add = armpmu_add, | |
508 | .del = armpmu_del, | |
509 | .start = armpmu_start, | |
510 | .stop = armpmu_stop, | |
511 | .read = armpmu_read, | |
512 | }; | |
513 | } | |
514 | ||
0305230a | 515 | int armpmu_register(struct arm_pmu *armpmu, int type) |
8a16b34e MR |
516 | { |
517 | armpmu_init(armpmu); | |
2ac29a14 | 518 | pm_runtime_enable(&armpmu->plat_device->dev); |
04236f9f WD |
519 | pr_info("enabled with %s PMU driver, %d counters available\n", |
520 | armpmu->name, armpmu->num_events); | |
0305230a | 521 | return perf_pmu_register(&armpmu->pmu, armpmu->name, type); |
03b7898d MR |
522 | } |
523 | ||
1b8873a0 JI |
524 | /* |
525 | * Callchain handling code. | |
526 | */ | |
1b8873a0 JI |
527 | |
528 | /* | |
529 | * The registers we're interested in are at the end of the variable | |
530 | * length saved register structure. The fp points at the end of this | |
531 | * structure so the address of this struct is: | |
532 | * (struct frame_tail *)(xxx->fp)-1 | |
533 | * | |
534 | * This code has been adapted from the ARM OProfile support. | |
535 | */ | |
536 | struct frame_tail { | |
4d6b7a77 WD |
537 | struct frame_tail __user *fp; |
538 | unsigned long sp; | |
539 | unsigned long lr; | |
1b8873a0 JI |
540 | } __attribute__((packed)); |
541 | ||
542 | /* | |
543 | * Get the return address for a single stackframe and return a pointer to the | |
544 | * next frame tail. | |
545 | */ | |
4d6b7a77 WD |
546 | static struct frame_tail __user * |
547 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
548 | struct perf_callchain_entry *entry) |
549 | { | |
550 | struct frame_tail buftail; | |
551 | ||
552 | /* Also check accessibility of one struct frame_tail beyond */ | |
553 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
554 | return NULL; | |
555 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
556 | return NULL; | |
557 | ||
70791ce9 | 558 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
559 | |
560 | /* | |
561 | * Frame pointers should strictly progress back up the stack | |
562 | * (towards higher addresses). | |
563 | */ | |
cb06199b | 564 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
565 | return NULL; |
566 | ||
567 | return buftail.fp - 1; | |
568 | } | |
569 | ||
56962b44 FW |
570 | void |
571 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 572 | { |
4d6b7a77 | 573 | struct frame_tail __user *tail; |
1b8873a0 | 574 | |
e50c5418 MZ |
575 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
576 | /* We don't support guest os callchain now */ | |
577 | return; | |
578 | } | |
1b8873a0 | 579 | |
c5f927a6 | 580 | perf_callchain_store(entry, regs->ARM_pc); |
4d6b7a77 | 581 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 582 | |
860ad782 SR |
583 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
584 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
585 | tail = user_backtrace(tail, entry); |
586 | } | |
587 | ||
588 | /* | |
589 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
590 | * whist unwinding the stackframe and is like a subroutine return so we use | |
591 | * the PC. | |
592 | */ | |
593 | static int | |
594 | callchain_trace(struct stackframe *fr, | |
595 | void *data) | |
596 | { | |
597 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 598 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
599 | return 0; |
600 | } | |
601 | ||
56962b44 FW |
602 | void |
603 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
604 | { |
605 | struct stackframe fr; | |
606 | ||
e50c5418 MZ |
607 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
608 | /* We don't support guest os callchain now */ | |
609 | return; | |
610 | } | |
611 | ||
1b8873a0 JI |
612 | fr.fp = regs->ARM_fp; |
613 | fr.sp = regs->ARM_sp; | |
614 | fr.lr = regs->ARM_lr; | |
615 | fr.pc = regs->ARM_pc; | |
616 | walk_stackframe(&fr, callchain_trace, entry); | |
617 | } | |
e50c5418 MZ |
618 | |
619 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
620 | { | |
621 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) | |
622 | return perf_guest_cbs->get_guest_ip(); | |
623 | ||
624 | return instruction_pointer(regs); | |
625 | } | |
626 | ||
627 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
628 | { | |
629 | int misc = 0; | |
630 | ||
631 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { | |
632 | if (perf_guest_cbs->is_user_mode()) | |
633 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
634 | else | |
635 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
636 | } else { | |
637 | if (user_mode(regs)) | |
638 | misc |= PERF_RECORD_MISC_USER; | |
639 | else | |
640 | misc |= PERF_RECORD_MISC_KERNEL; | |
641 | } | |
642 | ||
643 | return misc; | |
644 | } |