Commit | Line | Data |
---|---|---|
1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
7325eaec | 15 | #include <linux/bitmap.h> |
1b8873a0 JI |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kernel.h> | |
ecea4ab6 | 18 | #include <linux/export.h> |
1b8873a0 | 19 | #include <linux/perf_event.h> |
49c006b9 | 20 | #include <linux/platform_device.h> |
1b8873a0 JI |
21 | #include <linux/spinlock.h> |
22 | #include <linux/uaccess.h> | |
23 | ||
24 | #include <asm/cputype.h> | |
25 | #include <asm/irq.h> | |
26 | #include <asm/irq_regs.h> | |
27 | #include <asm/pmu.h> | |
28 | #include <asm/stacktrace.h> | |
29 | ||
1b8873a0 | 30 | /* |
ecf5a893 | 31 | * ARMv6 supports a maximum of 3 events, starting from index 0. If we add |
1b8873a0 JI |
32 | * another platform that supports more, we need to increase this to be the |
33 | * largest of all platforms. | |
796d1295 JP |
34 | * |
35 | * ARMv7 supports up to 32 events: | |
36 | * cycle counter CCNT + 31 events counters CNT0..30. | |
37 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. | |
1b8873a0 | 38 | */ |
ecf5a893 | 39 | #define ARMPMU_MAX_HWEVENTS 32 |
1b8873a0 | 40 | |
3fc2c830 MR |
41 | static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); |
42 | static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); | |
8be3f9a2 | 43 | static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); |
181193f3 | 44 | |
8a16b34e MR |
45 | #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) |
46 | ||
1b8873a0 | 47 | /* Set at runtime when we know what CPU type we are. */ |
8be3f9a2 | 48 | static struct arm_pmu *cpu_pmu; |
1b8873a0 | 49 | |
181193f3 WD |
50 | enum arm_perf_pmu_ids |
51 | armpmu_get_pmu_id(void) | |
52 | { | |
53 | int id = -ENODEV; | |
54 | ||
8be3f9a2 MR |
55 | if (cpu_pmu != NULL) |
56 | id = cpu_pmu->id; | |
181193f3 WD |
57 | |
58 | return id; | |
59 | } | |
60 | EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); | |
61 | ||
929f5199 WD |
62 | int |
63 | armpmu_get_max_events(void) | |
64 | { | |
65 | int max_events = 0; | |
66 | ||
8be3f9a2 MR |
67 | if (cpu_pmu != NULL) |
68 | max_events = cpu_pmu->num_events; | |
929f5199 WD |
69 | |
70 | return max_events; | |
71 | } | |
72 | EXPORT_SYMBOL_GPL(armpmu_get_max_events); | |
73 | ||
3bf101ba MF |
74 | int perf_num_counters(void) |
75 | { | |
76 | return armpmu_get_max_events(); | |
77 | } | |
78 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
79 | ||
1b8873a0 JI |
80 | #define HW_OP_UNSUPPORTED 0xFFFF |
81 | ||
82 | #define C(_x) \ | |
83 | PERF_COUNT_HW_CACHE_##_x | |
84 | ||
85 | #define CACHE_OP_UNSUPPORTED 0xFFFF | |
86 | ||
1b8873a0 | 87 | static int |
e1f431b5 MR |
88 | armpmu_map_cache_event(const unsigned (*cache_map) |
89 | [PERF_COUNT_HW_CACHE_MAX] | |
90 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
91 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
92 | u64 config) | |
1b8873a0 JI |
93 | { |
94 | unsigned int cache_type, cache_op, cache_result, ret; | |
95 | ||
96 | cache_type = (config >> 0) & 0xff; | |
97 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
98 | return -EINVAL; | |
99 | ||
100 | cache_op = (config >> 8) & 0xff; | |
101 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
102 | return -EINVAL; | |
103 | ||
104 | cache_result = (config >> 16) & 0xff; | |
105 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
106 | return -EINVAL; | |
107 | ||
e1f431b5 | 108 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
109 | |
110 | if (ret == CACHE_OP_UNSUPPORTED) | |
111 | return -ENOENT; | |
112 | ||
113 | return ret; | |
114 | } | |
115 | ||
84fee97a | 116 | static int |
e1f431b5 | 117 | armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 118 | { |
e1f431b5 MR |
119 | int mapping = (*event_map)[config]; |
120 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; | |
84fee97a WD |
121 | } |
122 | ||
123 | static int | |
e1f431b5 | 124 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 125 | { |
e1f431b5 MR |
126 | return (int)(config & raw_event_mask); |
127 | } | |
128 | ||
129 | static int map_cpu_event(struct perf_event *event, | |
130 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
131 | const unsigned (*cache_map) | |
132 | [PERF_COUNT_HW_CACHE_MAX] | |
133 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
134 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
135 | u32 raw_event_mask) | |
136 | { | |
137 | u64 config = event->attr.config; | |
138 | ||
139 | switch (event->attr.type) { | |
140 | case PERF_TYPE_HARDWARE: | |
141 | return armpmu_map_event(event_map, config); | |
142 | case PERF_TYPE_HW_CACHE: | |
143 | return armpmu_map_cache_event(cache_map, config); | |
144 | case PERF_TYPE_RAW: | |
145 | return armpmu_map_raw_event(raw_event_mask, config); | |
146 | } | |
147 | ||
148 | return -ENOENT; | |
84fee97a WD |
149 | } |
150 | ||
0ce47080 | 151 | int |
1b8873a0 JI |
152 | armpmu_event_set_period(struct perf_event *event, |
153 | struct hw_perf_event *hwc, | |
154 | int idx) | |
155 | { | |
8a16b34e | 156 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
e7850595 | 157 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
158 | s64 period = hwc->sample_period; |
159 | int ret = 0; | |
160 | ||
161 | if (unlikely(left <= -period)) { | |
162 | left = period; | |
e7850595 | 163 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
164 | hwc->last_period = period; |
165 | ret = 1; | |
166 | } | |
167 | ||
168 | if (unlikely(left <= 0)) { | |
169 | left += period; | |
e7850595 | 170 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
171 | hwc->last_period = period; |
172 | ret = 1; | |
173 | } | |
174 | ||
175 | if (left > (s64)armpmu->max_period) | |
176 | left = armpmu->max_period; | |
177 | ||
e7850595 | 178 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 JI |
179 | |
180 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); | |
181 | ||
182 | perf_event_update_userpage(event); | |
183 | ||
184 | return ret; | |
185 | } | |
186 | ||
0ce47080 | 187 | u64 |
1b8873a0 JI |
188 | armpmu_event_update(struct perf_event *event, |
189 | struct hw_perf_event *hwc, | |
a737823d | 190 | int idx, int overflow) |
1b8873a0 | 191 | { |
8a16b34e | 192 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
a737823d | 193 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
194 | |
195 | again: | |
e7850595 | 196 | prev_raw_count = local64_read(&hwc->prev_count); |
1b8873a0 JI |
197 | new_raw_count = armpmu->read_counter(idx); |
198 | ||
e7850595 | 199 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
200 | new_raw_count) != prev_raw_count) |
201 | goto again; | |
202 | ||
a737823d WD |
203 | new_raw_count &= armpmu->max_period; |
204 | prev_raw_count &= armpmu->max_period; | |
205 | ||
206 | if (overflow) | |
6759788b | 207 | delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; |
a737823d WD |
208 | else |
209 | delta = new_raw_count - prev_raw_count; | |
1b8873a0 | 210 | |
e7850595 PZ |
211 | local64_add(delta, &event->count); |
212 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
213 | |
214 | return new_raw_count; | |
215 | } | |
216 | ||
217 | static void | |
a4eaf7f1 | 218 | armpmu_read(struct perf_event *event) |
1b8873a0 | 219 | { |
1b8873a0 | 220 | struct hw_perf_event *hwc = &event->hw; |
1b8873a0 | 221 | |
a4eaf7f1 PZ |
222 | /* Don't read disabled counters! */ |
223 | if (hwc->idx < 0) | |
224 | return; | |
1b8873a0 | 225 | |
a737823d | 226 | armpmu_event_update(event, hwc, hwc->idx, 0); |
1b8873a0 JI |
227 | } |
228 | ||
229 | static void | |
a4eaf7f1 | 230 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 231 | { |
8a16b34e | 232 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
233 | struct hw_perf_event *hwc = &event->hw; |
234 | ||
a4eaf7f1 PZ |
235 | /* |
236 | * ARM pmu always has to update the counter, so ignore | |
237 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
238 | */ | |
239 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
240 | armpmu->disable(hwc, hwc->idx); | |
241 | barrier(); /* why? */ | |
a737823d | 242 | armpmu_event_update(event, hwc, hwc->idx, 0); |
a4eaf7f1 PZ |
243 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
244 | } | |
1b8873a0 JI |
245 | } |
246 | ||
247 | static void | |
a4eaf7f1 | 248 | armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 249 | { |
8a16b34e | 250 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
251 | struct hw_perf_event *hwc = &event->hw; |
252 | ||
a4eaf7f1 PZ |
253 | /* |
254 | * ARM pmu always has to reprogram the period, so ignore | |
255 | * PERF_EF_RELOAD, see the comment below. | |
256 | */ | |
257 | if (flags & PERF_EF_RELOAD) | |
258 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
259 | ||
260 | hwc->state = 0; | |
1b8873a0 JI |
261 | /* |
262 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 263 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
264 | * may have been left counting. If we don't do this step then we may |
265 | * get an interrupt too soon or *way* too late if the overflow has | |
266 | * happened since disabling. | |
267 | */ | |
268 | armpmu_event_set_period(event, hwc, hwc->idx); | |
269 | armpmu->enable(hwc, hwc->idx); | |
270 | } | |
271 | ||
a4eaf7f1 PZ |
272 | static void |
273 | armpmu_del(struct perf_event *event, int flags) | |
274 | { | |
8a16b34e | 275 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 276 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
a4eaf7f1 PZ |
277 | struct hw_perf_event *hwc = &event->hw; |
278 | int idx = hwc->idx; | |
279 | ||
280 | WARN_ON(idx < 0); | |
281 | ||
a4eaf7f1 | 282 | armpmu_stop(event, PERF_EF_UPDATE); |
8be3f9a2 MR |
283 | hw_events->events[idx] = NULL; |
284 | clear_bit(idx, hw_events->used_mask); | |
a4eaf7f1 PZ |
285 | |
286 | perf_event_update_userpage(event); | |
287 | } | |
288 | ||
1b8873a0 | 289 | static int |
a4eaf7f1 | 290 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 291 | { |
8a16b34e | 292 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 293 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
1b8873a0 JI |
294 | struct hw_perf_event *hwc = &event->hw; |
295 | int idx; | |
296 | int err = 0; | |
297 | ||
33696fc0 | 298 | perf_pmu_disable(event->pmu); |
24cd7f54 | 299 | |
1b8873a0 | 300 | /* If we don't have a space for the counter then finish early. */ |
8be3f9a2 | 301 | idx = armpmu->get_event_idx(hw_events, hwc); |
1b8873a0 JI |
302 | if (idx < 0) { |
303 | err = idx; | |
304 | goto out; | |
305 | } | |
306 | ||
307 | /* | |
308 | * If there is an event in the counter we are going to use then make | |
309 | * sure it is disabled. | |
310 | */ | |
311 | event->hw.idx = idx; | |
312 | armpmu->disable(hwc, idx); | |
8be3f9a2 | 313 | hw_events->events[idx] = event; |
1b8873a0 | 314 | |
a4eaf7f1 PZ |
315 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
316 | if (flags & PERF_EF_START) | |
317 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
318 | |
319 | /* Propagate our changes to the userspace mapping. */ | |
320 | perf_event_update_userpage(event); | |
321 | ||
322 | out: | |
33696fc0 | 323 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
324 | return err; |
325 | } | |
326 | ||
1b8873a0 | 327 | static int |
8be3f9a2 | 328 | validate_event(struct pmu_hw_events *hw_events, |
1b8873a0 JI |
329 | struct perf_event *event) |
330 | { | |
8a16b34e | 331 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 332 | struct hw_perf_event fake_event = event->hw; |
7b9f72c6 | 333 | struct pmu *leader_pmu = event->group_leader->pmu; |
1b8873a0 | 334 | |
7b9f72c6 | 335 | if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF) |
65b4711f | 336 | return 1; |
1b8873a0 | 337 | |
8be3f9a2 | 338 | return armpmu->get_event_idx(hw_events, &fake_event) >= 0; |
1b8873a0 JI |
339 | } |
340 | ||
341 | static int | |
342 | validate_group(struct perf_event *event) | |
343 | { | |
344 | struct perf_event *sibling, *leader = event->group_leader; | |
8be3f9a2 | 345 | struct pmu_hw_events fake_pmu; |
bce34d14 | 346 | DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS); |
1b8873a0 | 347 | |
bce34d14 WD |
348 | /* |
349 | * Initialise the fake PMU. We only need to populate the | |
350 | * used_mask for the purposes of validation. | |
351 | */ | |
352 | memset(fake_used_mask, 0, sizeof(fake_used_mask)); | |
353 | fake_pmu.used_mask = fake_used_mask; | |
1b8873a0 JI |
354 | |
355 | if (!validate_event(&fake_pmu, leader)) | |
aa2bc1ad | 356 | return -EINVAL; |
1b8873a0 JI |
357 | |
358 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
359 | if (!validate_event(&fake_pmu, sibling)) | |
aa2bc1ad | 360 | return -EINVAL; |
1b8873a0 JI |
361 | } |
362 | ||
363 | if (!validate_event(&fake_pmu, event)) | |
aa2bc1ad | 364 | return -EINVAL; |
1b8873a0 JI |
365 | |
366 | return 0; | |
367 | } | |
368 | ||
0e25a5c9 RV |
369 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
370 | { | |
8a16b34e | 371 | struct arm_pmu *armpmu = (struct arm_pmu *) dev; |
a9356a04 MR |
372 | struct platform_device *plat_device = armpmu->plat_device; |
373 | struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); | |
0e25a5c9 RV |
374 | |
375 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
376 | } | |
377 | ||
0b390e21 | 378 | static void |
8a16b34e | 379 | armpmu_release_hardware(struct arm_pmu *armpmu) |
0b390e21 WD |
380 | { |
381 | int i, irq, irqs; | |
a9356a04 | 382 | struct platform_device *pmu_device = armpmu->plat_device; |
0b390e21 WD |
383 | |
384 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
385 | ||
386 | for (i = 0; i < irqs; ++i) { | |
387 | if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) | |
388 | continue; | |
389 | irq = platform_get_irq(pmu_device, i); | |
390 | if (irq >= 0) | |
8a16b34e | 391 | free_irq(irq, armpmu); |
0b390e21 WD |
392 | } |
393 | ||
7ae18a57 | 394 | release_pmu(armpmu->type); |
0b390e21 WD |
395 | } |
396 | ||
1b8873a0 | 397 | static int |
8a16b34e | 398 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
1b8873a0 | 399 | { |
0e25a5c9 RV |
400 | struct arm_pmu_platdata *plat; |
401 | irq_handler_t handle_irq; | |
b0e89590 | 402 | int i, err, irq, irqs; |
a9356a04 | 403 | struct platform_device *pmu_device = armpmu->plat_device; |
1b8873a0 | 404 | |
e5a21327 WD |
405 | if (!pmu_device) |
406 | return -ENODEV; | |
407 | ||
7ae18a57 | 408 | err = reserve_pmu(armpmu->type); |
b0e89590 | 409 | if (err) { |
1b8873a0 | 410 | pr_warning("unable to reserve pmu\n"); |
b0e89590 | 411 | return err; |
1b8873a0 JI |
412 | } |
413 | ||
0e25a5c9 RV |
414 | plat = dev_get_platdata(&pmu_device->dev); |
415 | if (plat && plat->handle_irq) | |
416 | handle_irq = armpmu_platform_irq; | |
417 | else | |
418 | handle_irq = armpmu->handle_irq; | |
419 | ||
0b390e21 | 420 | irqs = min(pmu_device->num_resources, num_possible_cpus()); |
b0e89590 | 421 | if (irqs < 1) { |
1b8873a0 JI |
422 | pr_err("no irqs for PMUs defined\n"); |
423 | return -ENODEV; | |
424 | } | |
425 | ||
b0e89590 | 426 | for (i = 0; i < irqs; ++i) { |
0b390e21 | 427 | err = 0; |
49c006b9 WD |
428 | irq = platform_get_irq(pmu_device, i); |
429 | if (irq < 0) | |
430 | continue; | |
431 | ||
b0e89590 WD |
432 | /* |
433 | * If we have a single PMU interrupt that we can't shift, | |
434 | * assume that we're running on a uniprocessor machine and | |
0b390e21 | 435 | * continue. Otherwise, continue without this interrupt. |
b0e89590 | 436 | */ |
0b390e21 WD |
437 | if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { |
438 | pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
439 | irq, i); | |
440 | continue; | |
b0e89590 WD |
441 | } |
442 | ||
0e25a5c9 | 443 | err = request_irq(irq, handle_irq, |
ddee87f2 | 444 | IRQF_DISABLED | IRQF_NOBALANCING, |
8a16b34e | 445 | "arm-pmu", armpmu); |
1b8873a0 | 446 | if (err) { |
b0e89590 WD |
447 | pr_err("unable to request IRQ%d for ARM PMU counters\n", |
448 | irq); | |
8a16b34e | 449 | armpmu_release_hardware(armpmu); |
0b390e21 | 450 | return err; |
1b8873a0 | 451 | } |
1b8873a0 | 452 | |
0b390e21 | 453 | cpumask_set_cpu(i, &armpmu->active_irqs); |
49c006b9 | 454 | } |
1b8873a0 | 455 | |
0b390e21 | 456 | return 0; |
1b8873a0 JI |
457 | } |
458 | ||
1b8873a0 JI |
459 | static void |
460 | hw_perf_event_destroy(struct perf_event *event) | |
461 | { | |
8a16b34e | 462 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
03b7898d MR |
463 | atomic_t *active_events = &armpmu->active_events; |
464 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
465 | ||
466 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
8a16b34e | 467 | armpmu_release_hardware(armpmu); |
03b7898d | 468 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
469 | } |
470 | } | |
471 | ||
05d22fde WD |
472 | static int |
473 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
474 | { | |
475 | return attr->exclude_idle || attr->exclude_user || | |
476 | attr->exclude_kernel || attr->exclude_hv; | |
477 | } | |
478 | ||
1b8873a0 JI |
479 | static int |
480 | __hw_perf_event_init(struct perf_event *event) | |
481 | { | |
8a16b34e | 482 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
483 | struct hw_perf_event *hwc = &event->hw; |
484 | int mapping, err; | |
485 | ||
e1f431b5 | 486 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
487 | |
488 | if (mapping < 0) { | |
489 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
490 | event->attr.config); | |
491 | return mapping; | |
492 | } | |
493 | ||
05d22fde WD |
494 | /* |
495 | * We don't assign an index until we actually place the event onto | |
496 | * hardware. Use -1 to signify that we haven't decided where to put it | |
497 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
498 | * clever allocation or constraints checking at this point. | |
499 | */ | |
500 | hwc->idx = -1; | |
501 | hwc->config_base = 0; | |
502 | hwc->config = 0; | |
503 | hwc->event_base = 0; | |
504 | ||
1b8873a0 JI |
505 | /* |
506 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 507 | */ |
05d22fde WD |
508 | if ((!armpmu->set_event_filter || |
509 | armpmu->set_event_filter(hwc, &event->attr)) && | |
510 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
511 | pr_debug("ARM performance counters do not support " |
512 | "mode exclusion\n"); | |
513 | return -EPERM; | |
514 | } | |
515 | ||
516 | /* | |
05d22fde | 517 | * Store the event encoding into the config_base field. |
1b8873a0 | 518 | */ |
05d22fde | 519 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
520 | |
521 | if (!hwc->sample_period) { | |
522 | hwc->sample_period = armpmu->max_period; | |
523 | hwc->last_period = hwc->sample_period; | |
e7850595 | 524 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
525 | } |
526 | ||
527 | err = 0; | |
528 | if (event->group_leader != event) { | |
529 | err = validate_group(event); | |
530 | if (err) | |
531 | return -EINVAL; | |
532 | } | |
533 | ||
534 | return err; | |
535 | } | |
536 | ||
b0a873eb | 537 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 538 | { |
8a16b34e | 539 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 540 | int err = 0; |
03b7898d | 541 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 542 | |
e1f431b5 | 543 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 544 | return -ENOENT; |
b0a873eb | 545 | |
1b8873a0 JI |
546 | event->destroy = hw_perf_event_destroy; |
547 | ||
03b7898d MR |
548 | if (!atomic_inc_not_zero(active_events)) { |
549 | mutex_lock(&armpmu->reserve_mutex); | |
550 | if (atomic_read(active_events) == 0) | |
8a16b34e | 551 | err = armpmu_reserve_hardware(armpmu); |
1b8873a0 JI |
552 | |
553 | if (!err) | |
03b7898d MR |
554 | atomic_inc(active_events); |
555 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
556 | } |
557 | ||
558 | if (err) | |
b0a873eb | 559 | return err; |
1b8873a0 JI |
560 | |
561 | err = __hw_perf_event_init(event); | |
562 | if (err) | |
563 | hw_perf_event_destroy(event); | |
564 | ||
b0a873eb | 565 | return err; |
1b8873a0 JI |
566 | } |
567 | ||
a4eaf7f1 | 568 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 569 | { |
8be3f9a2 | 570 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
8be3f9a2 | 571 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
7325eaec | 572 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
1b8873a0 | 573 | |
f4f38430 WD |
574 | if (enabled) |
575 | armpmu->start(); | |
1b8873a0 JI |
576 | } |
577 | ||
a4eaf7f1 | 578 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 579 | { |
8a16b34e | 580 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
48957155 | 581 | armpmu->stop(); |
1b8873a0 JI |
582 | } |
583 | ||
03b7898d MR |
584 | static void __init armpmu_init(struct arm_pmu *armpmu) |
585 | { | |
586 | atomic_set(&armpmu->active_events, 0); | |
587 | mutex_init(&armpmu->reserve_mutex); | |
8a16b34e MR |
588 | |
589 | armpmu->pmu = (struct pmu) { | |
590 | .pmu_enable = armpmu_enable, | |
591 | .pmu_disable = armpmu_disable, | |
592 | .event_init = armpmu_event_init, | |
593 | .add = armpmu_add, | |
594 | .del = armpmu_del, | |
595 | .start = armpmu_start, | |
596 | .stop = armpmu_stop, | |
597 | .read = armpmu_read, | |
598 | }; | |
599 | } | |
600 | ||
0ce47080 | 601 | int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type) |
8a16b34e MR |
602 | { |
603 | armpmu_init(armpmu); | |
604 | return perf_pmu_register(&armpmu->pmu, name, type); | |
03b7898d MR |
605 | } |
606 | ||
43eab878 WD |
607 | /* Include the PMU-specific implementations. */ |
608 | #include "perf_event_xscale.c" | |
609 | #include "perf_event_v6.c" | |
610 | #include "perf_event_v7.c" | |
49e6a32f | 611 | |
574b69cb WD |
612 | /* |
613 | * Ensure the PMU has sane values out of reset. | |
614 | * This requires SMP to be available, so exists as a separate initcall. | |
615 | */ | |
616 | static int __init | |
8be3f9a2 | 617 | cpu_pmu_reset(void) |
574b69cb | 618 | { |
8be3f9a2 MR |
619 | if (cpu_pmu && cpu_pmu->reset) |
620 | return on_each_cpu(cpu_pmu->reset, NULL, 1); | |
574b69cb WD |
621 | return 0; |
622 | } | |
8be3f9a2 | 623 | arch_initcall(cpu_pmu_reset); |
574b69cb | 624 | |
b0e89590 WD |
625 | /* |
626 | * PMU platform driver and devicetree bindings. | |
627 | */ | |
628 | static struct of_device_id armpmu_of_device_ids[] = { | |
629 | {.compatible = "arm,cortex-a9-pmu"}, | |
630 | {.compatible = "arm,cortex-a8-pmu"}, | |
631 | {.compatible = "arm,arm1136-pmu"}, | |
632 | {.compatible = "arm,arm1176-pmu"}, | |
633 | {}, | |
634 | }; | |
635 | ||
636 | static struct platform_device_id armpmu_plat_device_ids[] = { | |
637 | {.name = "arm-pmu"}, | |
638 | {}, | |
639 | }; | |
640 | ||
641 | static int __devinit armpmu_device_probe(struct platform_device *pdev) | |
642 | { | |
6bd05409 WD |
643 | if (!cpu_pmu) |
644 | return -ENODEV; | |
645 | ||
8be3f9a2 | 646 | cpu_pmu->plat_device = pdev; |
b0e89590 WD |
647 | return 0; |
648 | } | |
649 | ||
650 | static struct platform_driver armpmu_driver = { | |
651 | .driver = { | |
652 | .name = "arm-pmu", | |
653 | .of_match_table = armpmu_of_device_ids, | |
654 | }, | |
655 | .probe = armpmu_device_probe, | |
656 | .id_table = armpmu_plat_device_ids, | |
657 | }; | |
658 | ||
659 | static int __init register_pmu_driver(void) | |
660 | { | |
661 | return platform_driver_register(&armpmu_driver); | |
662 | } | |
663 | device_initcall(register_pmu_driver); | |
664 | ||
8be3f9a2 | 665 | static struct pmu_hw_events *armpmu_get_cpu_events(void) |
92f701e1 MR |
666 | { |
667 | return &__get_cpu_var(cpu_hw_events); | |
668 | } | |
669 | ||
670 | static void __init cpu_pmu_init(struct arm_pmu *armpmu) | |
671 | { | |
0f78d2d5 MR |
672 | int cpu; |
673 | for_each_possible_cpu(cpu) { | |
8be3f9a2 | 674 | struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu); |
3fc2c830 MR |
675 | events->events = per_cpu(hw_events, cpu); |
676 | events->used_mask = per_cpu(used_mask, cpu); | |
0f78d2d5 MR |
677 | raw_spin_lock_init(&events->pmu_lock); |
678 | } | |
92f701e1 | 679 | armpmu->get_hw_events = armpmu_get_cpu_events; |
7ae18a57 | 680 | armpmu->type = ARM_PMU_DEVICE_CPU; |
92f701e1 MR |
681 | } |
682 | ||
b0e89590 WD |
683 | /* |
684 | * CPU PMU identification and registration. | |
685 | */ | |
1b8873a0 JI |
686 | static int __init |
687 | init_hw_perf_events(void) | |
688 | { | |
689 | unsigned long cpuid = read_cpuid_id(); | |
690 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; | |
691 | unsigned long part_number = (cpuid & 0xFFF0); | |
692 | ||
49e6a32f | 693 | /* ARM Ltd CPUs. */ |
1b8873a0 JI |
694 | if (0x41 == implementor) { |
695 | switch (part_number) { | |
696 | case 0xB360: /* ARM1136 */ | |
697 | case 0xB560: /* ARM1156 */ | |
698 | case 0xB760: /* ARM1176 */ | |
8be3f9a2 | 699 | cpu_pmu = armv6pmu_init(); |
1b8873a0 JI |
700 | break; |
701 | case 0xB020: /* ARM11mpcore */ | |
8be3f9a2 | 702 | cpu_pmu = armv6mpcore_pmu_init(); |
1b8873a0 | 703 | break; |
796d1295 | 704 | case 0xC080: /* Cortex-A8 */ |
8be3f9a2 | 705 | cpu_pmu = armv7_a8_pmu_init(); |
796d1295 JP |
706 | break; |
707 | case 0xC090: /* Cortex-A9 */ | |
8be3f9a2 | 708 | cpu_pmu = armv7_a9_pmu_init(); |
796d1295 | 709 | break; |
0c205cbe | 710 | case 0xC050: /* Cortex-A5 */ |
8be3f9a2 | 711 | cpu_pmu = armv7_a5_pmu_init(); |
0c205cbe | 712 | break; |
14abd038 | 713 | case 0xC0F0: /* Cortex-A15 */ |
8be3f9a2 | 714 | cpu_pmu = armv7_a15_pmu_init(); |
14abd038 | 715 | break; |
49e6a32f WD |
716 | } |
717 | /* Intel CPUs [xscale]. */ | |
718 | } else if (0x69 == implementor) { | |
719 | part_number = (cpuid >> 13) & 0x7; | |
720 | switch (part_number) { | |
721 | case 1: | |
8be3f9a2 | 722 | cpu_pmu = xscale1pmu_init(); |
49e6a32f WD |
723 | break; |
724 | case 2: | |
8be3f9a2 | 725 | cpu_pmu = xscale2pmu_init(); |
49e6a32f | 726 | break; |
1b8873a0 JI |
727 | } |
728 | } | |
729 | ||
8be3f9a2 | 730 | if (cpu_pmu) { |
796d1295 | 731 | pr_info("enabled with %s PMU driver, %d counters available\n", |
8be3f9a2 MR |
732 | cpu_pmu->name, cpu_pmu->num_events); |
733 | cpu_pmu_init(cpu_pmu); | |
734 | armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW); | |
49e6a32f WD |
735 | } else { |
736 | pr_info("no hardware support available\n"); | |
49e6a32f | 737 | } |
1b8873a0 JI |
738 | |
739 | return 0; | |
740 | } | |
004417a6 | 741 | early_initcall(init_hw_perf_events); |
1b8873a0 JI |
742 | |
743 | /* | |
744 | * Callchain handling code. | |
745 | */ | |
1b8873a0 JI |
746 | |
747 | /* | |
748 | * The registers we're interested in are at the end of the variable | |
749 | * length saved register structure. The fp points at the end of this | |
750 | * structure so the address of this struct is: | |
751 | * (struct frame_tail *)(xxx->fp)-1 | |
752 | * | |
753 | * This code has been adapted from the ARM OProfile support. | |
754 | */ | |
755 | struct frame_tail { | |
4d6b7a77 WD |
756 | struct frame_tail __user *fp; |
757 | unsigned long sp; | |
758 | unsigned long lr; | |
1b8873a0 JI |
759 | } __attribute__((packed)); |
760 | ||
761 | /* | |
762 | * Get the return address for a single stackframe and return a pointer to the | |
763 | * next frame tail. | |
764 | */ | |
4d6b7a77 WD |
765 | static struct frame_tail __user * |
766 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
767 | struct perf_callchain_entry *entry) |
768 | { | |
769 | struct frame_tail buftail; | |
770 | ||
771 | /* Also check accessibility of one struct frame_tail beyond */ | |
772 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
773 | return NULL; | |
774 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
775 | return NULL; | |
776 | ||
70791ce9 | 777 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
778 | |
779 | /* | |
780 | * Frame pointers should strictly progress back up the stack | |
781 | * (towards higher addresses). | |
782 | */ | |
cb06199b | 783 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
784 | return NULL; |
785 | ||
786 | return buftail.fp - 1; | |
787 | } | |
788 | ||
56962b44 FW |
789 | void |
790 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 791 | { |
4d6b7a77 | 792 | struct frame_tail __user *tail; |
1b8873a0 | 793 | |
1b8873a0 | 794 | |
4d6b7a77 | 795 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 796 | |
860ad782 SR |
797 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
798 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
799 | tail = user_backtrace(tail, entry); |
800 | } | |
801 | ||
802 | /* | |
803 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
804 | * whist unwinding the stackframe and is like a subroutine return so we use | |
805 | * the PC. | |
806 | */ | |
807 | static int | |
808 | callchain_trace(struct stackframe *fr, | |
809 | void *data) | |
810 | { | |
811 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 812 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
813 | return 0; |
814 | } | |
815 | ||
56962b44 FW |
816 | void |
817 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
818 | { |
819 | struct stackframe fr; | |
820 | ||
1b8873a0 JI |
821 | fr.fp = regs->ARM_fp; |
822 | fr.sp = regs->ARM_sp; | |
823 | fr.lr = regs->ARM_lr; | |
824 | fr.pc = regs->ARM_pc; | |
825 | walk_stackframe(&fr, callchain_trace, entry); | |
826 | } |