[deliverable/linux.git] / arch / arm / kernel / perf_event_cpu.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Copyright (C) 2012 ARM Limited
 *
 * Author: Will Deacon <will.deacon@arm.com>
 */
#define pr_fmt(fmt) "CPU PMU: " fmt

#include <linux/bitmap.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include <asm/cputype.h>
#include <asm/irq_regs.h>
#include <asm/pmu.h>

/* Set at runtime when we know what CPU type we are. */
static struct arm_pmu *cpu_pmu;

static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);

/*
 * Despite the names, these two functions are CPU-specific and are used
 * by the OProfile/perf code.
 */
const char *perf_pmu_name(void)
{
	if (!cpu_pmu)
		return NULL;

	return cpu_pmu->name;
}
EXPORT_SYMBOL_GPL(perf_pmu_name);

int perf_num_counters(void)
{
	int max_events = 0;

	if (cpu_pmu != NULL)
		max_events = cpu_pmu->num_events;

	return max_events;
}
EXPORT_SYMBOL_GPL(perf_num_counters);

/* Include the PMU-specific implementations. */
#include "perf_event_xscale.c"
#include "perf_event_v6.c"
#include "perf_event_v7.c"

static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
{
	return this_cpu_ptr(&cpu_hw_events);
}

static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
{
	int i, irq, irqs;
	struct platform_device *pmu_device = cpu_pmu->plat_device;

	irqs = min(pmu_device->num_resources, num_possible_cpus());

	for (i = 0; i < irqs; ++i) {
		if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
			continue;
		irq = platform_get_irq(pmu_device, i);
		if (irq >= 0)
			free_irq(irq, cpu_pmu);
	}
}

static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
{
	int i, err, irq, irqs;
	struct platform_device *pmu_device = cpu_pmu->plat_device;

	if (!pmu_device)
		return -ENODEV;

	irqs = min(pmu_device->num_resources, num_possible_cpus());
	if (irqs < 1) {
		pr_err("no irqs for PMUs defined\n");
		return -ENODEV;
	}

	for (i = 0; i < irqs; ++i) {
		err = 0;
		irq = platform_get_irq(pmu_device, i);
		if (irq < 0)
			continue;

		/*
		 * If we have a single PMU interrupt that we can't shift,
		 * assume that we're running on a uniprocessor machine and
		 * continue. Otherwise, continue without this interrupt.
		 */
		if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
			pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
				    irq, i);
			continue;
		}

		err = request_irq(irq, handler,
				  IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
				  cpu_pmu);
		if (err) {
			pr_err("unable to request IRQ%d for ARM PMU counters\n",
				irq);
			return err;
		}

		cpumask_set_cpu(i, &cpu_pmu->active_irqs);
	}

	return 0;
}

static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
{
	int cpu;
	for_each_possible_cpu(cpu) {
		struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
		events->events = per_cpu(hw_events, cpu);
		events->used_mask = per_cpu(used_mask, cpu);
		raw_spin_lock_init(&events->pmu_lock);
	}

	cpu_pmu->get_hw_events	= cpu_pmu_get_cpu_events;
	cpu_pmu->request_irq	= cpu_pmu_request_irq;
	cpu_pmu->free_irq	= cpu_pmu_free_irq;

	/* Ensure the PMU has sane values out of reset. */
	if (cpu_pmu->reset)
		on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
}

/*
 * PMU hardware loses all context when a CPU goes offline.
 * When a CPU is hotplugged back in, since some hardware registers are
 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
 * junk values out of them.
 */
static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
			  void *hcpu)
{
	if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
		return NOTIFY_DONE;

	if (cpu_pmu && cpu_pmu->reset)
		cpu_pmu->reset(cpu_pmu);
	else
		return NOTIFY_DONE;

	return NOTIFY_OK;
}

static struct notifier_block cpu_pmu_hotplug_notifier = {
	.notifier_call = cpu_pmu_notify,
};

/*
 * PMU platform driver and devicetree bindings.
 */
static struct of_device_id cpu_pmu_of_device_ids[] = {
	{.compatible = "arm,cortex-a15-pmu",	.data = armv7_a15_pmu_init},
	{.compatible = "arm,cortex-a9-pmu",	.data = armv7_a9_pmu_init},
	{.compatible = "arm,cortex-a8-pmu",	.data = armv7_a8_pmu_init},
	{.compatible = "arm,cortex-a7-pmu",	.data = armv7_a7_pmu_init},
	{.compatible = "arm,cortex-a5-pmu",	.data = armv7_a5_pmu_init},
	{.compatible = "arm,arm11mpcore-pmu",	.data = armv6mpcore_pmu_init},
	{.compatible = "arm,arm1176-pmu",	.data = armv6pmu_init},
	{.compatible = "arm,arm1136-pmu",	.data = armv6pmu_init},
	{},
};

static struct platform_device_id cpu_pmu_plat_device_ids[] = {
	{.name = "arm-pmu"},
	{},
};

/*
 * CPU PMU identification and probing.
 */
static int probe_current_pmu(struct arm_pmu *pmu)
{
	int cpu = get_cpu();
	unsigned long implementor = read_cpuid_implementor();
	unsigned long part_number = read_cpuid_part_number();
	int ret = -ENODEV;

	pr_info("probing PMU on CPU %d\n", cpu);

	/* ARM Ltd CPUs. */
	if (implementor == ARM_CPU_IMP_ARM) {
		switch (part_number) {
		case ARM_CPU_PART_ARM1136:
		case ARM_CPU_PART_ARM1156:
		case ARM_CPU_PART_ARM1176:
			ret = armv6pmu_init(pmu);
			break;
		case ARM_CPU_PART_ARM11MPCORE:
			ret = armv6mpcore_pmu_init(pmu);
			break;
		case ARM_CPU_PART_CORTEX_A8:
			ret = armv7_a8_pmu_init(pmu);
			break;
		case ARM_CPU_PART_CORTEX_A9:
			ret = armv7_a9_pmu_init(pmu);
			break;
		case ARM_CPU_PART_CORTEX_A5:
			ret = armv7_a5_pmu_init(pmu);
			break;
		case ARM_CPU_PART_CORTEX_A15:
			ret = armv7_a15_pmu_init(pmu);
			break;
		case ARM_CPU_PART_CORTEX_A7:
			ret = armv7_a7_pmu_init(pmu);
			break;
		}
	/* Intel CPUs [xscale]. */
	} else if (implementor == ARM_CPU_IMP_INTEL) {
		switch (xscale_cpu_arch_version()) {
		case ARM_CPU_XSCALE_ARCH_V1:
			ret = xscale1pmu_init(pmu);
			break;
		case ARM_CPU_XSCALE_ARCH_V2:
			ret = xscale2pmu_init(pmu);
			break;
		}
	}

	put_cpu();
	return ret;
}

static int cpu_pmu_device_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id;
	const int (*init_fn)(struct arm_pmu *);
	struct device_node *node = pdev->dev.of_node;
	struct arm_pmu *pmu;
	int ret = -ENODEV;

	if (cpu_pmu) {
		pr_info("attempt to register multiple PMU devices!");
		return -ENOSPC;
	}

	pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
	if (!pmu) {
		pr_info("failed to allocate PMU device!");
		return -ENOMEM;
	}

	if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
		init_fn = of_id->data;
		ret = init_fn(pmu);
	} else {
		ret = probe_current_pmu(pmu);
	}

	if (ret) {
		pr_info("failed to probe PMU!");
		goto out_free;
	}

	cpu_pmu = pmu;
	cpu_pmu->plat_device = pdev;
	cpu_pmu_init(cpu_pmu);
	ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW);

	if (!ret)
		return 0;

out_free:
	pr_info("failed to register PMU devices!");
	kfree(pmu);
	return ret;
}

static struct platform_driver cpu_pmu_driver = {
	.driver		= {
		.name	= "arm-pmu",
		.pm	= &armpmu_dev_pm_ops,
		.of_match_table = cpu_pmu_of_device_ids,
	},
	.probe		= cpu_pmu_device_probe,
	.id_table	= cpu_pmu_plat_device_ids,
};

static int __init register_pmu_driver(void)
{
	int err;

	err = register_cpu_notifier(&cpu_pmu_hotplug_notifier);
	if (err)
		return err;

	err = platform_driver_register(&cpu_pmu_driver);
	if (err)
		unregister_cpu_notifier(&cpu_pmu_hotplug_notifier);

	return err;
}
device_initcall(register_pmu_driver);
Commit	Line	Data
5505b206 WD	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License version 2 as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	14	*
	15	* Copyright (C) 2012 ARM Limited
	16	*
	17	* Author: Will Deacon <will.deacon@arm.com>
	18	*/
	19	#define pr_fmt(fmt) "CPU PMU: " fmt
	20
	21	#include <linux/bitmap.h>
	22	#include <linux/export.h>
	23	#include <linux/kernel.h>
	24	#include <linux/of.h>
	25	#include <linux/platform_device.h>
513c99ce	26	#include <linux/slab.h>
5505b206 WD	27	#include <linux/spinlock.h>
	28
	29	#include <asm/cputype.h>
	30	#include <asm/irq_regs.h>
	31	#include <asm/pmu.h>
	32
	33	/* Set at runtime when we know what CPU type we are. */
	34	static struct arm_pmu *cpu_pmu;
	35
	36	static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
	37	static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
	38	static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
	39
	40	/*
	41	* Despite the names, these two functions are CPU-specific and are used
	42	* by the OProfile/perf code.
	43	*/
	44	const char *perf_pmu_name(void)
	45	{
	46	if (!cpu_pmu)
	47	return NULL;
	48
0305230a	49	return cpu_pmu->name;
5505b206 WD	50	}
	51	EXPORT_SYMBOL_GPL(perf_pmu_name);
	52
	53	int perf_num_counters(void)
	54	{
	55	int max_events = 0;
	56
	57	if (cpu_pmu != NULL)
	58	max_events = cpu_pmu->num_events;
	59
	60	return max_events;
	61	}
	62	EXPORT_SYMBOL_GPL(perf_num_counters);
	63
	64	/* Include the PMU-specific implementations. */
	65	#include "perf_event_xscale.c"
	66	#include "perf_event_v6.c"
	67	#include "perf_event_v7.c"
	68
	69	static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
	70	{
1436c1aa	71	return this_cpu_ptr(&cpu_hw_events);
5505b206 WD	72	}
5505b206 WD	73
ed6f2a52	74	static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
051f1b13 SK	75	{
	76	int i, irq, irqs;
	77	struct platform_device *pmu_device = cpu_pmu->plat_device;
	78
	79	irqs = min(pmu_device->num_resources, num_possible_cpus());
	80
	81	for (i = 0; i < irqs; ++i) {
	82	if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
	83	continue;
	84	irq = platform_get_irq(pmu_device, i);
	85	if (irq >= 0)
	86	free_irq(irq, cpu_pmu);
	87	}
	88	}
	89
ed6f2a52	90	static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
051f1b13 SK	91	{
	92	int i, err, irq, irqs;
	93	struct platform_device *pmu_device = cpu_pmu->plat_device;
	94
	95	if (!pmu_device)
	96	return -ENODEV;
	97
	98	irqs = min(pmu_device->num_resources, num_possible_cpus());
	99	if (irqs < 1) {
	100	pr_err("no irqs for PMUs defined\n");
	101	return -ENODEV;
	102	}
	103
	104	for (i = 0; i < irqs; ++i) {
	105	err = 0;
	106	irq = platform_get_irq(pmu_device, i);
	107	if (irq < 0)
	108	continue;
	109
	110	/*
	111	* If we have a single PMU interrupt that we can't shift,
	112	* assume that we're running on a uniprocessor machine and
	113	* continue. Otherwise, continue without this interrupt.
	114	*/
	115	if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
	116	pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
	117	irq, i);
	118	continue;
	119	}
	120
d9c3365b TG	121	err = request_irq(irq, handler,
d9c3365b TG	122	IRQF_NOBALANCING \| IRQF_NO_THREAD, "arm-pmu",
051f1b13 SK	123	cpu_pmu);
	124	if (err) {
	125	pr_err("unable to request IRQ%d for ARM PMU counters\n",
	126	irq);
	127	return err;
	128	}
	129
	130	cpumask_set_cpu(i, &cpu_pmu->active_irqs);
	131	}
	132
	133	return 0;
	134	}
	135
351a102d	136	static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
5505b206 WD	137	{
	138	int cpu;
	139	for_each_possible_cpu(cpu) {
	140	struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
	141	events->events = per_cpu(hw_events, cpu);
	142	events->used_mask = per_cpu(used_mask, cpu);
	143	raw_spin_lock_init(&events->pmu_lock);
	144	}
051f1b13 SK	145
	146	cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
	147	cpu_pmu->request_irq = cpu_pmu_request_irq;
	148	cpu_pmu->free_irq = cpu_pmu_free_irq;
5505b206 WD	149
5505b206 WD	150	/* Ensure the PMU has sane values out of reset. */
1764c591	151	if (cpu_pmu->reset)
ed6f2a52	152	on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
5505b206 WD	153	}
	154
	155	/*
	156	* PMU hardware loses all context when a CPU goes offline.
	157	* When a CPU is hotplugged back in, since some hardware registers are
	158	* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
	159	* junk values out of them.
	160	*/
8bd26e3a PG	161	static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
8bd26e3a PG	162	void *hcpu)
5505b206 WD	163	{
	164	if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
	165	return NOTIFY_DONE;
	166
	167	if (cpu_pmu && cpu_pmu->reset)
ed6f2a52	168	cpu_pmu->reset(cpu_pmu);
288700d1 WD	169	else
288700d1 WD	170	return NOTIFY_DONE;
5505b206 WD	171
	172	return NOTIFY_OK;
	173	}
	174
8bd26e3a	175	static struct notifier_block cpu_pmu_hotplug_notifier = {
5505b206 WD	176	.notifier_call = cpu_pmu_notify,
	177	};
	178
	179	/*
	180	* PMU platform driver and devicetree bindings.
	181	*/
351a102d	182	static struct of_device_id cpu_pmu_of_device_ids[] = {
5505b206 WD	183	{.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
	184	{.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
	185	{.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
	186	{.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
	187	{.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
	188	{.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
	189	{.compatible = "arm,arm1176-pmu", .data = armv6pmu_init},
	190	{.compatible = "arm,arm1136-pmu", .data = armv6pmu_init},
	191	{},
	192	};
	193
351a102d	194	static struct platform_device_id cpu_pmu_plat_device_ids[] = {
5505b206 WD	195	{.name = "arm-pmu"},
	196	{},
	197	};
	198
	199	/*
	200	* CPU PMU identification and probing.
	201	*/
351a102d	202	static int probe_current_pmu(struct arm_pmu *pmu)
5505b206	203	{
5505b206	204	int cpu = get_cpu();
3b953c9c CD	205	unsigned long implementor = read_cpuid_implementor();
3b953c9c CD	206	unsigned long part_number = read_cpuid_part_number();
513c99ce	207	int ret = -ENODEV;
5505b206 WD	208
	209	pr_info("probing PMU on CPU %d\n", cpu);
	210
	211	/* ARM Ltd CPUs. */
3b953c9c	212	if (implementor == ARM_CPU_IMP_ARM) {
5505b206	213	switch (part_number) {
3b953c9c CD	214	case ARM_CPU_PART_ARM1136:
	215	case ARM_CPU_PART_ARM1156:
	216	case ARM_CPU_PART_ARM1176:
513c99ce	217	ret = armv6pmu_init(pmu);
5505b206	218	break;
3b953c9c	219	case ARM_CPU_PART_ARM11MPCORE:
513c99ce	220	ret = armv6mpcore_pmu_init(pmu);
5505b206	221	break;
3b953c9c	222	case ARM_CPU_PART_CORTEX_A8:
513c99ce	223	ret = armv7_a8_pmu_init(pmu);
5505b206	224	break;
3b953c9c	225	case ARM_CPU_PART_CORTEX_A9:
513c99ce	226	ret = armv7_a9_pmu_init(pmu);
5505b206	227	break;
3b953c9c	228	case ARM_CPU_PART_CORTEX_A5:
513c99ce	229	ret = armv7_a5_pmu_init(pmu);
5505b206	230	break;
3b953c9c	231	case ARM_CPU_PART_CORTEX_A15:
513c99ce	232	ret = armv7_a15_pmu_init(pmu);
5505b206	233	break;
3b953c9c	234	case ARM_CPU_PART_CORTEX_A7:
513c99ce	235	ret = armv7_a7_pmu_init(pmu);
5505b206 WD	236	break;
	237	}
	238	/* Intel CPUs [xscale]. */
3b953c9c CD	239	} else if (implementor == ARM_CPU_IMP_INTEL) {
	240	switch (xscale_cpu_arch_version()) {
	241	case ARM_CPU_XSCALE_ARCH_V1:
513c99ce	242	ret = xscale1pmu_init(pmu);
5505b206	243	break;
3b953c9c	244	case ARM_CPU_XSCALE_ARCH_V2:
513c99ce	245	ret = xscale2pmu_init(pmu);
5505b206 WD	246	break;
	247	}
	248	}
	249
	250	put_cpu();
513c99ce	251	return ret;
5505b206 WD	252	}
5505b206 WD	253
351a102d	254	static int cpu_pmu_device_probe(struct platform_device *pdev)
5505b206 WD	255	{
5505b206 WD	256	const struct of_device_id *of_id;
261521f1	257	const int (init_fn)(struct arm_pmu );
5505b206	258	struct device_node *node = pdev->dev.of_node;
513c99ce SK	259	struct arm_pmu *pmu;
513c99ce SK	260	int ret = -ENODEV;
5505b206 WD	261
	262	if (cpu_pmu) {
	263	pr_info("attempt to register multiple PMU devices!");
	264	return -ENOSPC;
	265	}
	266
513c99ce SK	267	pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
	268	if (!pmu) {
	269	pr_info("failed to allocate PMU device!");
	270	return -ENOMEM;
	271	}
	272
5505b206 WD	273	if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
5505b206 WD	274	init_fn = of_id->data;
513c99ce	275	ret = init_fn(pmu);
5505b206	276	} else {
513c99ce	277	ret = probe_current_pmu(pmu);
5505b206 WD	278	}
5505b206 WD	279
513c99ce	280	if (ret) {
76b8a0e4 MR	281	pr_info("failed to probe PMU!");
76b8a0e4 MR	282	goto out_free;
513c99ce	283	}
5505b206	284
513c99ce	285	cpu_pmu = pmu;
5505b206 WD	286	cpu_pmu->plat_device = pdev;
5505b206 WD	287	cpu_pmu_init(cpu_pmu);
76b8a0e4	288	ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW);
5505b206	289
76b8a0e4 MR	290	if (!ret)
	291	return 0;
	292
	293	out_free:
	294	pr_info("failed to register PMU devices!");
	295	kfree(pmu);
	296	return ret;
5505b206 WD	297	}
	298
	299	static struct platform_driver cpu_pmu_driver = {
	300	.driver = {
	301	.name = "arm-pmu",
	302	.pm = &armpmu_dev_pm_ops,
	303	.of_match_table = cpu_pmu_of_device_ids,
	304	},
	305	.probe = cpu_pmu_device_probe,
	306	.id_table = cpu_pmu_plat_device_ids,
	307	};
	308
	309	static int __init register_pmu_driver(void)
	310	{
2a4961ba MR	311	int err;
	312
	313	err = register_cpu_notifier(&cpu_pmu_hotplug_notifier);
	314	if (err)
	315	return err;
	316
	317	err = platform_driver_register(&cpu_pmu_driver);
	318	if (err)
	319	unregister_cpu_notifier(&cpu_pmu_hotplug_notifier);
	320
	321	return err;
5505b206 WD	322	}
5505b206 WD	323	device_initcall(register_pmu_driver);