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arm: perf: Convert event enums to #defines
[deliverable/linux.git] / arch / arm / kernel / perf_event_v7.c
CommitLineData
43eab878
WD		 1/*
2 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
3 *
4 * ARMv7 support: Jean Pihet <jpihet@mvista.com>
5 * 2010 (c) MontaVista Software, LLC.
6 *
7 * Copied from ARMv6 code, with the low level code inspired
8 * by the ARMv7 Oprofile code.
9 *
10 * Cortex-A8 has up to 4 configurable performance counters and
11 * a single cycle counter.
12 * Cortex-A9 has up to 31 configurable performance counters and
13 * a single cycle counter.
14 *
15 * All counters can be enabled/disabled and IRQ masked separately. The cycle
16 * counter and all 4 performance counters together can be reset separately.
17 */
18
19#ifdef CONFIG_CPU_V7
a505addc 20
b7aafe99 21#include <asm/cp15.h>
29ba0f37
MR		 22#include <asm/cputype.h>
23#include <asm/irq_regs.h>
b7aafe99
SB		 24#include <asm/vfp.h>
25#include "../vfp/vfpinstr.h"
26
29ba0f37 27#include <linux/of.h>
fa8ad788 28#include <linux/perf/arm_pmu.h>
29ba0f37
MR		 29#include <linux/platform_device.h>
30
6d4eaf99
WD		 31/*
32 * Common ARMv7 event types
33 *
34 * Note: An implementation may not be able to count all of these events
35 * but the encodings are considered to be `reserved' in the case that
36 * they are not available.
37 */
f4ab36cb
DR		 38#define ARMV7_PERFCTR_PMNC_SW_INCR 0x00
39#define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01
40#define ARMV7_PERFCTR_ITLB_REFILL 0x02
41#define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03
42#define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04
43#define ARMV7_PERFCTR_DTLB_REFILL 0x05
44#define ARMV7_PERFCTR_MEM_READ 0x06
45#define ARMV7_PERFCTR_MEM_WRITE 0x07
46#define ARMV7_PERFCTR_INSTR_EXECUTED 0x08
47#define ARMV7_PERFCTR_EXC_TAKEN 0x09
48#define ARMV7_PERFCTR_EXC_EXECUTED 0x0A
49#define ARMV7_PERFCTR_CID_WRITE 0x0B
50
51/*
52 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
53 * It counts:
54 * - all (taken) branch instructions,
55 * - instructions that explicitly write the PC,
56 * - exception generating instructions.
57 */
58#define ARMV7_PERFCTR_PC_WRITE 0x0C
59#define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D
60#define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E
61#define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
62#define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10
63#define ARMV7_PERFCTR_CLOCK_CYCLES 0x11
64#define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12
65
66/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
67#define ARMV7_PERFCTR_MEM_ACCESS 0x13
68#define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14
69#define ARMV7_PERFCTR_L1_DCACHE_WB 0x15
70#define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16
71#define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17
72#define ARMV7_PERFCTR_L2_CACHE_WB 0x18
73#define ARMV7_PERFCTR_BUS_ACCESS 0x19
74#define ARMV7_PERFCTR_MEM_ERROR 0x1A
75#define ARMV7_PERFCTR_INSTR_SPEC 0x1B
76#define ARMV7_PERFCTR_TTBR_WRITE 0x1C
77#define ARMV7_PERFCTR_BUS_CYCLES 0x1D
78
79#define ARMV7_PERFCTR_CPU_CYCLES 0xFF
43eab878
WD		 80
81/* ARMv7 Cortex-A8 specific event types */
f4ab36cb
DR		 82#define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43
83#define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44
84#define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50
85#define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56
43eab878
WD		 86
87/* ARMv7 Cortex-A9 specific event types */
f4ab36cb
DR		 88#define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68
89#define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60
90#define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66
43eab878 91
0c205cbe 92/* ARMv7 Cortex-A5 specific event types */
f4ab36cb
DR		 93#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2
94#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3
0c205cbe 95
14abd038 96/* ARMv7 Cortex-A15 specific event types */
f4ab36cb
DR		 97#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
98#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
99#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42
100#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43
14abd038 101
f4ab36cb
DR		 102#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C
103#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D
14abd038 104
f4ab36cb
DR		 105#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50
106#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
107#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52
108#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53
14abd038 109
f4ab36cb 110#define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76
14abd038 111
8e781f65 112/* ARMv7 Cortex-A12 specific event types */
f4ab36cb
DR		 113#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
114#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
8e781f65 115
f4ab36cb
DR		 116#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50
117#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
8e781f65 118
f4ab36cb 119#define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76
8e781f65 120
f4ab36cb 121#define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7
8e781f65 122
b7aafe99 123/* ARMv7 Krait specific event types */
f4ab36cb
DR		 124#define KRAIT_PMRESR0_GROUP0 0xcc
125#define KRAIT_PMRESR1_GROUP0 0xd0
126#define KRAIT_PMRESR2_GROUP0 0xd4
127#define KRAIT_VPMRESR0_GROUP0 0xd8
b7aafe99 128
f4ab36cb
DR		 129#define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011
130#define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010
b7aafe99 131
f4ab36cb
DR		 132#define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222
133#define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210
b7aafe99 134
341e42c4 135/* ARMv7 Scorpion specific event types */
f4ab36cb
DR		 136#define SCORPION_LPM0_GROUP0 0x4c
137#define SCORPION_LPM1_GROUP0 0x50
138#define SCORPION_LPM2_GROUP0 0x54
139#define SCORPION_L2LPM_GROUP0 0x58
140#define SCORPION_VLPM_GROUP0 0x5c
341e42c4 141
f4ab36cb
DR		 142#define SCORPION_ICACHE_ACCESS 0x10053
143#define SCORPION_ICACHE_MISS 0x10052
341e42c4 144
f4ab36cb
DR		 145#define SCORPION_DTLB_ACCESS 0x12013
146#define SCORPION_DTLB_MISS 0x12012
341e42c4 147
f4ab36cb 148#define SCORPION_ITLB_MISS 0x12021
341e42c4 149
43eab878
WD		 150/*
151 * Cortex-A8 HW events mapping
152 *
153 * The hardware events that we support. We do support cache operations but
154 * we have harvard caches and no way to combine instruction and data
155 * accesses/misses in hardware.
156 */
157static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
6b7658ec 158 PERF_MAP_ALL_UNSUPPORTED,
0445e7a5
WD		 159 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
160 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
161 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
162 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
163 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
164 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
0445e7a5 165 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE,
43eab878
WD		 166};
167
168static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
169 [PERF_COUNT_HW_CACHE_OP_MAX]
170 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
6b7658ec
MR		 171 PERF_CACHE_MAP_ALL_UNSUPPORTED,
172
173 /*
174 * The performance counters don't differentiate between read and write
175 * accesses/misses so this isn't strictly correct, but it's the best we
176 * can do. Writes and reads get combined.
177 */
178 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
179 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
180 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
181 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
182
183 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
184 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
185
186 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
187 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
188 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
189 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
190
191 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
192 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
193
194 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
195 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
196
197 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
198 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
199 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
200 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
43eab878
WD		 201};
202
203/*
204 * Cortex-A9 HW events mapping
205 */
206static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
6b7658ec 207 PERF_MAP_ALL_UNSUPPORTED,
0445e7a5
WD		 208 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
209 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
210 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
211 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
212 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
213 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
0445e7a5
WD		 214 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE,
215 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH,
43eab878
WD		 216};
217
218static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
219 [PERF_COUNT_HW_CACHE_OP_MAX]
220 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
6b7658ec
MR		 221 PERF_CACHE_MAP_ALL_UNSUPPORTED,
222
223 /*
224 * The performance counters don't differentiate between read and write
225 * accesses/misses so this isn't strictly correct, but it's the best we
226 * can do. Writes and reads get combined.
227 */
228 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
229 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
230 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
231 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
232
233 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
234
235 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
236 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
237
238 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
239 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
240
241 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
242 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
243 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
244 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
43eab878
WD		 245};
246
0c205cbe
WD		 247/*
248 * Cortex-A5 HW events mapping
249 */
250static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
6b7658ec 251 PERF_MAP_ALL_UNSUPPORTED,
0445e7a5
WD		 252 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
253 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
254 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
255 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
256 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
257 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
0c205cbe
WD		 258};
259
260static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
261 [PERF_COUNT_HW_CACHE_OP_MAX]
262 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
6b7658ec
MR		 263 PERF_CACHE_MAP_ALL_UNSUPPORTED,
264
265 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
266 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
267 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
268 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
269 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
270 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
271
272 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
273 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
274 /*
275 * The prefetch counters don't differentiate between the I side and the
276 * D side.
277 */
278 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
279 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
280
281 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
282 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
283
284 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
285 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
286
287 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
288 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
289 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
290 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
0c205cbe
WD		 291};
292
14abd038
WD		 293/*
294 * Cortex-A15 HW events mapping
295 */
296static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
6b7658ec 297 PERF_MAP_ALL_UNSUPPORTED,
0445e7a5
WD		 298 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
299 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
300 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
301 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
302 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC,
303 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
304 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
14abd038
WD		 305};
306
307static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
308 [PERF_COUNT_HW_CACHE_OP_MAX]
309 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
6b7658ec
MR		 310 PERF_CACHE_MAP_ALL_UNSUPPORTED,
311
312 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
313 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
314 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
315 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
316
317 /*
318 * Not all performance counters differentiate between read and write
319 * accesses/misses so we're not always strictly correct, but it's the
320 * best we can do. Writes and reads get combined in these cases.
321 */
322 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
323 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
324
325 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
326 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
327 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
328 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
329
330 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
331 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
332
333 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
334 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
335
336 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
337 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
338 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
339 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
14abd038
WD		 340};
341
d33c88c6
WD		 342/*
343 * Cortex-A7 HW events mapping
344 */
345static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = {
6b7658ec 346 PERF_MAP_ALL_UNSUPPORTED,
d33c88c6
WD		 347 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
348 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
349 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
350 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
351 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
352 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
353 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
d33c88c6
WD		 354};
355
356static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
357 [PERF_COUNT_HW_CACHE_OP_MAX]
358 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
6b7658ec
MR		 359 PERF_CACHE_MAP_ALL_UNSUPPORTED,
360
361 /*
362 * The performance counters don't differentiate between read and write
363 * accesses/misses so this isn't strictly correct, but it's the best we
364 * can do. Writes and reads get combined.
365 */
366 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
367 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
368 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
369 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
370
371 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
372 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
373
374 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
375 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
376 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
377 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
378
379 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
380 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
381
382 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
383 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
384
385 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
386 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
387 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
388 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
d33c88c6
WD		 389};
390
8e781f65
AT		 391/*
392 * Cortex-A12 HW events mapping
393 */
394static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = {
6b7658ec 395 PERF_MAP_ALL_UNSUPPORTED,
8e781f65
AT		 396 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
397 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
398 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
399 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
400 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC,
401 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
402 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
8e781f65
AT		 403};
404
405static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
406 [PERF_COUNT_HW_CACHE_OP_MAX]
407 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
6b7658ec
MR		 408 PERF_CACHE_MAP_ALL_UNSUPPORTED,
409
410 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ,
411 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
412 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE,
413 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
414
415 /*
416 * Not all performance counters differentiate between read and write
417 * accesses/misses so we're not always strictly correct, but it's the
418 * best we can do. Writes and reads get combined in these cases.
419 */
420 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
421 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
422
423 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ,
424 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
425 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE,
426 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
427
428 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
429 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
430 [C(DTLB)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL,
431
432 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
433 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
434
435 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
436 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
437 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
438 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
8e781f65
AT		 439};
440
2a3391cd
SB		 441/*
442 * Krait HW events mapping
443 */
444static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = {
6b7658ec 445 PERF_MAP_ALL_UNSUPPORTED,
2a3391cd
SB		 446 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
447 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
2a3391cd
SB		 448 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
449 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
450 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
451};
452
453static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = {
6b7658ec 454 PERF_MAP_ALL_UNSUPPORTED,
2a3391cd
SB		 455 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
456 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
2a3391cd
SB		 457 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
458 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
459};
460
461static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
462 [PERF_COUNT_HW_CACHE_OP_MAX]
463 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
6b7658ec
MR		 464 PERF_CACHE_MAP_ALL_UNSUPPORTED,
465
466 /*
467 * The performance counters don't differentiate between read and write
468 * accesses/misses so this isn't strictly correct, but it's the best we
469 * can do. Writes and reads get combined.
470 */
471 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
472 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
473 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
474 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
475
476 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS,
477 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS,
478
479 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS,
480 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS,
481
482 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS,
483 [C(ITLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS,
484
485 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
486 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
487 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
488 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
2a3391cd
SB		 489};
490
341e42c4
SB		 491/*
492 * Scorpion HW events mapping
493 */
494static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = {
495 PERF_MAP_ALL_UNSUPPORTED,
496 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
497 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
498 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
499 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
500 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
501};
502
503static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
504 [PERF_COUNT_HW_CACHE_OP_MAX]
505 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
506 PERF_CACHE_MAP_ALL_UNSUPPORTED,
507 /*
508 * The performance counters don't differentiate between read and write
509 * accesses/misses so this isn't strictly correct, but it's the best we
510 * can do. Writes and reads get combined.
511 */
512 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
513 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
514 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
515 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
516 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS,
517 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS,
518 /*
519 * Only ITLB misses and DTLB refills are supported. If users want the
520 * DTLB refills misses a raw counter must be used.
521 */
522 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS,
523 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
524 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS,
525 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS,
526 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
527 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ITLB_MISS,
528 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
529 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
530 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
531 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
532};
533
43eab878 534/*
c691bb62 535 * Perf Events' indices
43eab878 536 */
c691bb62
WD		 537#define ARMV7_IDX_CYCLE_COUNTER 0
538#define ARMV7_IDX_COUNTER0 1
7279adbd
SK		 539#define ARMV7_IDX_COUNTER_LAST(cpu_pmu) \
540 (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
c691bb62
WD		 541
542#define ARMV7_MAX_COUNTERS 32
543#define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1)
43eab878
WD		 544
545/*
c691bb62 546 * ARMv7 low level PMNC access
43eab878 547 */
43eab878
WD		 548
549/*
c691bb62 550 * Perf Event to low level counters mapping
43eab878 551 */
c691bb62
WD		 552#define ARMV7_IDX_TO_COUNTER(x) \
553 (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK)
43eab878
WD		 554
555/*
556 * Per-CPU PMNC: config reg
557 */
558#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
559#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
560#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
561#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
562#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */
563#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
564#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */
565#define ARMV7_PMNC_N_MASK 0x1f
566#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
567
568/*
43eab878 569 * FLAG: counters overflow flag status reg
43eab878 570 */
43eab878
WD		 571#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
572#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK
43eab878
WD		 573
574/*
a505addc 575 * PMXEVTYPER: Event selection reg
43eab878 576 */
f2fe09b0 577#define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */
a505addc 578#define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */
43eab878
WD		 579
580/*
a505addc 581 * Event filters for PMUv2
43eab878 582 */
a505addc
WD		 583#define ARMV7_EXCLUDE_PL1 (1 << 31)
584#define ARMV7_EXCLUDE_USER (1 << 30)
585#define ARMV7_INCLUDE_HYP (1 << 27)
43eab878 586
6330aae7 587static inline u32 armv7_pmnc_read(void)
43eab878
WD		 588{
589 u32 val;
590 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
591 return val;
592}
593
6330aae7 594static inline void armv7_pmnc_write(u32 val)
43eab878
WD		 595{
596 val &= ARMV7_PMNC_MASK;
d25d3b4c 597 isb();
43eab878
WD		 598 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
599}
600
6330aae7 601static inline int armv7_pmnc_has_overflowed(u32 pmnc)
43eab878
WD		 602{
603 return pmnc & ARMV7_OVERFLOWED_MASK;
604}
605
7279adbd 606static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int idx)
c691bb62 607{
7279adbd
SK		 608 return idx >= ARMV7_IDX_CYCLE_COUNTER &&
609 idx <= ARMV7_IDX_COUNTER_LAST(cpu_pmu);
c691bb62
WD		 610}
611
612static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx)
43eab878 613{
7279adbd 614 return pmnc & BIT(ARMV7_IDX_TO_COUNTER(idx));
43eab878
WD		 615}
616
cb6eb108 617static inline void armv7_pmnc_select_counter(int idx)
43eab878 618{
7279adbd 619 u32 counter = ARMV7_IDX_TO_COUNTER(idx);
c691bb62 620 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter));
d25d3b4c 621 isb();
43eab878
WD		 622}
623
ed6f2a52 624static inline u32 armv7pmu_read_counter(struct perf_event *event)
43eab878 625{
7279adbd 626 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
ed6f2a52
SK		 627 struct hw_perf_event *hwc = &event->hw;
628 int idx = hwc->idx;
6330aae7 629 u32 value = 0;
43eab878 630
cb6eb108 631 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
43eab878
WD		 632 pr_err("CPU%u reading wrong counter %d\n",
633 smp_processor_id(), idx);
cb6eb108 634 } else if (idx == ARMV7_IDX_CYCLE_COUNTER) {
c691bb62 635 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
cb6eb108 636 } else {
637 armv7_pmnc_select_counter(idx);
c691bb62 638 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value));
cb6eb108 639 }
43eab878
WD		 640
641 return value;
642}
643
ed6f2a52 644static inline void armv7pmu_write_counter(struct perf_event *event, u32 value)
43eab878 645{
7279adbd 646 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
ed6f2a52
SK		 647 struct hw_perf_event *hwc = &event->hw;
648 int idx = hwc->idx;
649
cb6eb108 650 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
43eab878
WD		 651 pr_err("CPU%u writing wrong counter %d\n",
652 smp_processor_id(), idx);
cb6eb108 653 } else if (idx == ARMV7_IDX_CYCLE_COUNTER) {
c691bb62 654 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
cb6eb108 655 } else {
656 armv7_pmnc_select_counter(idx);
c691bb62 657 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (value));
cb6eb108 658 }
43eab878
WD		 659}
660
25e29c7c 661static inline void armv7_pmnc_write_evtsel(int idx, u32 val)
43eab878 662{
cb6eb108 663 armv7_pmnc_select_counter(idx);
664 val &= ARMV7_EVTYPE_MASK;
665 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
43eab878
WD		 666}
667
cb6eb108 668static inline void armv7_pmnc_enable_counter(int idx)
43eab878 669{
7279adbd 670 u32 counter = ARMV7_IDX_TO_COUNTER(idx);
c691bb62 671 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter)));
43eab878
WD		 672}
673
cb6eb108 674static inline void armv7_pmnc_disable_counter(int idx)
43eab878 675{
7279adbd 676 u32 counter = ARMV7_IDX_TO_COUNTER(idx);
c691bb62 677 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter)));
43eab878
WD		 678}
679
cb6eb108 680static inline void armv7_pmnc_enable_intens(int idx)
43eab878 681{
7279adbd 682 u32 counter = ARMV7_IDX_TO_COUNTER(idx);
c691bb62 683 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter)));
43eab878
WD		 684}
685
cb6eb108 686static inline void armv7_pmnc_disable_intens(int idx)
43eab878 687{
7279adbd 688 u32 counter = ARMV7_IDX_TO_COUNTER(idx);
c691bb62 689 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
99c1745b
WD		 690 isb();
691 /* Clear the overflow flag in case an interrupt is pending. */
692 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter)));
693 isb();
43eab878
WD		 694}
695
696static inline u32 armv7_pmnc_getreset_flags(void)
697{
698 u32 val;
699
700 /* Read */
701 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
702
703 /* Write to clear flags */
704 val &= ARMV7_FLAG_MASK;
705 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
706
707 return val;
708}
709
710#ifdef DEBUG
7279adbd 711static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu)
43eab878
WD		 712{
713 u32 val;
714 unsigned int cnt;
715
52a5566e 716 pr_info("PMNC registers dump:\n");
43eab878
WD		 717
718 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
52a5566e 719 pr_info("PMNC =0x%08x\n", val);
43eab878
WD		 720
721 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
52a5566e 722 pr_info("CNTENS=0x%08x\n", val);
43eab878
WD		 723
724 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
52a5566e 725 pr_info("INTENS=0x%08x\n", val);
43eab878
WD		 726
727 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
52a5566e 728 pr_info("FLAGS =0x%08x\n", val);
43eab878
WD		 729
730 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
52a5566e 731 pr_info("SELECT=0x%08x\n", val);
43eab878
WD		 732
733 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
52a5566e 734 pr_info("CCNT =0x%08x\n", val);
43eab878 735
7279adbd
SK		 736 for (cnt = ARMV7_IDX_COUNTER0;
737 cnt <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) {
43eab878
WD		 738 armv7_pmnc_select_counter(cnt);
739 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
52a5566e 740 pr_info("CNT[%d] count =0x%08x\n",
c691bb62 741 ARMV7_IDX_TO_COUNTER(cnt), val);
43eab878 742 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
52a5566e 743 pr_info("CNT[%d] evtsel=0x%08x\n",
c691bb62 744 ARMV7_IDX_TO_COUNTER(cnt), val);
43eab878
WD		 745 }
746}
747#endif
748
ed6f2a52 749static void armv7pmu_enable_event(struct perf_event *event)
43eab878
WD		 750{
751 unsigned long flags;
ed6f2a52
SK		 752 struct hw_perf_event *hwc = &event->hw;
753 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
11679250 754 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
ed6f2a52 755 int idx = hwc->idx;
43eab878 756
7279adbd
SK		 757 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
758 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
759 smp_processor_id(), idx);
760 return;
761 }
762
43eab878
WD		 763 /*
764 * Enable counter and interrupt, and set the counter to count
765 * the event that we're interested in.
766 */
0f78d2d5 767 raw_spin_lock_irqsave(&events->pmu_lock, flags);
43eab878
WD		 768
769 /*
770 * Disable counter
771 */
772 armv7_pmnc_disable_counter(idx);
773
774 /*
775 * Set event (if destined for PMNx counters)
a505addc
WD		 776 * We only need to set the event for the cycle counter if we
777 * have the ability to perform event filtering.
43eab878 778 */
513c99ce 779 if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
43eab878
WD		 780 armv7_pmnc_write_evtsel(idx, hwc->config_base);
781
782 /*
783 * Enable interrupt for this counter
784 */
785 armv7_pmnc_enable_intens(idx);
786
787 /*
788 * Enable counter
789 */
790 armv7_pmnc_enable_counter(idx);
791
0f78d2d5 792 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
43eab878
WD		 793}
794
ed6f2a52 795static void armv7pmu_disable_event(struct perf_event *event)
43eab878
WD		 796{
797 unsigned long flags;
ed6f2a52
SK		 798 struct hw_perf_event *hwc = &event->hw;
799 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
11679250 800 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
ed6f2a52 801 int idx = hwc->idx;
43eab878 802
7279adbd
SK		 803 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
804 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
805 smp_processor_id(), idx);
806 return;
807 }
808
43eab878
WD		 809 /*
810 * Disable counter and interrupt
811 */
0f78d2d5 812 raw_spin_lock_irqsave(&events->pmu_lock, flags);
43eab878
WD		 813
814 /*
815 * Disable counter
816 */
817 armv7_pmnc_disable_counter(idx);
818
819 /*
820 * Disable interrupt for this counter
821 */
822 armv7_pmnc_disable_intens(idx);
823
0f78d2d5 824 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
43eab878
WD		 825}
826
827static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
828{
6330aae7 829 u32 pmnc;
43eab878 830 struct perf_sample_data data;
ed6f2a52 831 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
11679250 832 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
43eab878
WD		 833 struct pt_regs *regs;
834 int idx;
835
836 /*
837 * Get and reset the IRQ flags
838 */
839 pmnc = armv7_pmnc_getreset_flags();
840
841 /*
842 * Did an overflow occur?
843 */
844 if (!armv7_pmnc_has_overflowed(pmnc))
845 return IRQ_NONE;
846
847 /*
848 * Handle the counter(s) overflow(s)
849 */
850 regs = get_irq_regs();
851
8be3f9a2 852 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
43eab878
WD		 853 struct perf_event *event = cpuc->events[idx];
854 struct hw_perf_event *hwc;
855
f6f5a30c
WD		 856 /* Ignore if we don't have an event. */
857 if (!event)
858 continue;
859
43eab878
WD		 860 /*
861 * We have a single interrupt for all counters. Check that
862 * each counter has overflowed before we process it.
863 */
864 if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
865 continue;
866
867 hwc = &event->hw;
ed6f2a52 868 armpmu_event_update(event);
fd0d000b 869 perf_sample_data_init(&data, 0, hwc->last_period);
ed6f2a52 870 if (!armpmu_event_set_period(event))
43eab878
WD		 871 continue;
872
a8b0ca17 873 if (perf_event_overflow(event, &data, regs))
ed6f2a52 874 cpu_pmu->disable(event);
43eab878
WD		 875 }
876
877 /*
878 * Handle the pending perf events.
879 *
880 * Note: this call *must* be run with interrupts disabled. For
881 * platforms that can have the PMU interrupts raised as an NMI, this
882 * will not work.
883 */
884 irq_work_run();
885
886 return IRQ_HANDLED;
887}
888
ed6f2a52 889static void armv7pmu_start(struct arm_pmu *cpu_pmu)
43eab878
WD		 890{
891 unsigned long flags;
11679250 892 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
43eab878 893
0f78d2d5 894 raw_spin_lock_irqsave(&events->pmu_lock, flags);
43eab878
WD		 895 /* Enable all counters */
896 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
0f78d2d5 897 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
43eab878
WD		 898}
899
ed6f2a52 900static void armv7pmu_stop(struct arm_pmu *cpu_pmu)
43eab878
WD		 901{
902 unsigned long flags;
11679250 903 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
43eab878 904
0f78d2d5 905 raw_spin_lock_irqsave(&events->pmu_lock, flags);
43eab878
WD		 906 /* Disable all counters */
907 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
0f78d2d5 908 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
43eab878
WD		 909}
910
8be3f9a2 911static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc,
ed6f2a52 912 struct perf_event *event)
43eab878
WD		 913{
914 int idx;
ed6f2a52
SK		 915 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
916 struct hw_perf_event *hwc = &event->hw;
917 unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT;
43eab878
WD		 918
919 /* Always place a cycle counter into the cycle counter. */
a505addc 920 if (evtype == ARMV7_PERFCTR_CPU_CYCLES) {
c691bb62 921 if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask))
43eab878
WD		 922 return -EAGAIN;
923
c691bb62
WD		 924 return ARMV7_IDX_CYCLE_COUNTER;
925 }
43eab878 926
c691bb62
WD		 927 /*
928 * For anything other than a cycle counter, try and use
929 * the events counters
930 */
8be3f9a2 931 for (idx = ARMV7_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
c691bb62
WD		 932 if (!test_and_set_bit(idx, cpuc->used_mask))
933 return idx;
43eab878 934 }
c691bb62
WD		 935
936 /* The counters are all in use. */
937 return -EAGAIN;
43eab878
WD		 938}
939
a505addc
WD		 940/*
941 * Add an event filter to a given event. This will only work for PMUv2 PMUs.
942 */
943static int armv7pmu_set_event_filter(struct hw_perf_event *event,
944 struct perf_event_attr *attr)
945{
946 unsigned long config_base = 0;
947
948 if (attr->exclude_idle)
949 return -EPERM;
950 if (attr->exclude_user)
951 config_base |= ARMV7_EXCLUDE_USER;
952 if (attr->exclude_kernel)
953 config_base |= ARMV7_EXCLUDE_PL1;
954 if (!attr->exclude_hv)
955 config_base |= ARMV7_INCLUDE_HYP;
956
957 /*
958 * Install the filter into config_base as this is used to
959 * construct the event type.
960 */
961 event->config_base = config_base;
962
963 return 0;
43eab878
WD		 964}
965
574b69cb
WD		 966static void armv7pmu_reset(void *info)
967{
ed6f2a52 968 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
8be3f9a2 969 u32 idx, nb_cnt = cpu_pmu->num_events;
574b69cb
WD		 970
971 /* The counter and interrupt enable registers are unknown at reset. */
ed6f2a52
SK		 972 for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
973 armv7_pmnc_disable_counter(idx);
974 armv7_pmnc_disable_intens(idx);
975 }
574b69cb
WD		 976
977 /* Initialize & Reset PMNC: C and P bits */
978 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
979}
980
e1f431b5
MR		 981static int armv7_a8_map_event(struct perf_event *event)
982{
6dbc0029 983 return armpmu_map_event(event, &armv7_a8_perf_map,
e1f431b5
MR		 984 &armv7_a8_perf_cache_map, 0xFF);
985}
986
987static int armv7_a9_map_event(struct perf_event *event)
988{
6dbc0029 989 return armpmu_map_event(event, &armv7_a9_perf_map,
e1f431b5
MR		 990 &armv7_a9_perf_cache_map, 0xFF);
991}
992
993static int armv7_a5_map_event(struct perf_event *event)
994{
6dbc0029 995 return armpmu_map_event(event, &armv7_a5_perf_map,
e1f431b5
MR		 996 &armv7_a5_perf_cache_map, 0xFF);
997}
998
999static int armv7_a15_map_event(struct perf_event *event)
1000{
6dbc0029 1001 return armpmu_map_event(event, &armv7_a15_perf_map,
e1f431b5
MR		 1002 &armv7_a15_perf_cache_map, 0xFF);
1003}
1004
d33c88c6
WD		 1005static int armv7_a7_map_event(struct perf_event *event)
1006{
6dbc0029 1007 return armpmu_map_event(event, &armv7_a7_perf_map,
d33c88c6
WD		 1008 &armv7_a7_perf_cache_map, 0xFF);
1009}
1010
8e781f65
AT		 1011static int armv7_a12_map_event(struct perf_event *event)
1012{
1013 return armpmu_map_event(event, &armv7_a12_perf_map,
1014 &armv7_a12_perf_cache_map, 0xFF);
1015}
1016
2a3391cd
SB		 1017static int krait_map_event(struct perf_event *event)
1018{
1019 return armpmu_map_event(event, &krait_perf_map,
1020 &krait_perf_cache_map, 0xFFFFF);
1021}
1022
1023static int krait_map_event_no_branch(struct perf_event *event)
1024{
1025 return armpmu_map_event(event, &krait_perf_map_no_branch,
1026 &krait_perf_cache_map, 0xFFFFF);
1027}
1028
341e42c4
SB		 1029static int scorpion_map_event(struct perf_event *event)
1030{
1031 return armpmu_map_event(event, &scorpion_perf_map,
1032 &scorpion_perf_cache_map, 0xFFFFF);
1033}
1034
513c99ce
SK		 1035static void armv7pmu_init(struct arm_pmu *cpu_pmu)
1036{
1037 cpu_pmu->handle_irq = armv7pmu_handle_irq;
1038 cpu_pmu->enable = armv7pmu_enable_event;
1039 cpu_pmu->disable = armv7pmu_disable_event;
1040 cpu_pmu->read_counter = armv7pmu_read_counter;
1041 cpu_pmu->write_counter = armv7pmu_write_counter;
1042 cpu_pmu->get_event_idx = armv7pmu_get_event_idx;
1043 cpu_pmu->start = armv7pmu_start;
1044 cpu_pmu->stop = armv7pmu_stop;
1045 cpu_pmu->reset = armv7pmu_reset;
1046 cpu_pmu->max_period = (1LLU << 32) - 1;
43eab878
WD		 1047};
1048
0e3038d1 1049static void armv7_read_num_pmnc_events(void *info)
43eab878 1050{
0e3038d1 1051 int *nb_cnt = info;
43eab878 1052
43eab878 1053 /* Read the nb of CNTx counters supported from PMNC */
0e3038d1 1054 *nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
43eab878 1055
0e3038d1
MR		 1056 /* Add the CPU cycles counter */
1057 *nb_cnt += 1;
1058}
1059
1060static int armv7_probe_num_events(struct arm_pmu *arm_pmu)
1061{
1062 return smp_call_function_any(&arm_pmu->supported_cpus,
1063 armv7_read_num_pmnc_events,
1064 &arm_pmu->num_events, 1);
43eab878
WD		 1065}
1066
351a102d 1067static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
43eab878 1068{
513c99ce 1069 armv7pmu_init(cpu_pmu);
3d1ff755 1070 cpu_pmu->name = "armv7_cortex_a8";
513c99ce 1071 cpu_pmu->map_event = armv7_a8_map_event;
0e3038d1 1072 return armv7_probe_num_events(cpu_pmu);
43eab878
WD		 1073}
1074
351a102d 1075static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
43eab878 1076{
513c99ce 1077 armv7pmu_init(cpu_pmu);
3d1ff755 1078 cpu_pmu->name = "armv7_cortex_a9";
513c99ce 1079 cpu_pmu->map_event = armv7_a9_map_event;
0e3038d1 1080 return armv7_probe_num_events(cpu_pmu);
43eab878 1081}
0c205cbe 1082
351a102d 1083static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
0c205cbe 1084{
513c99ce 1085 armv7pmu_init(cpu_pmu);
3d1ff755 1086 cpu_pmu->name = "armv7_cortex_a5";
513c99ce 1087 cpu_pmu->map_event = armv7_a5_map_event;
0e3038d1 1088 return armv7_probe_num_events(cpu_pmu);
0c205cbe 1089}
14abd038 1090
351a102d 1091static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
14abd038 1092{
513c99ce 1093 armv7pmu_init(cpu_pmu);
3d1ff755 1094 cpu_pmu->name = "armv7_cortex_a15";
513c99ce 1095 cpu_pmu->map_event = armv7_a15_map_event;
513c99ce 1096 cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
0e3038d1 1097 return armv7_probe_num_events(cpu_pmu);
14abd038 1098}
d33c88c6 1099
351a102d 1100static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
d33c88c6 1101{
513c99ce 1102 armv7pmu_init(cpu_pmu);
3d1ff755 1103 cpu_pmu->name = "armv7_cortex_a7";
513c99ce 1104 cpu_pmu->map_event = armv7_a7_map_event;
513c99ce 1105 cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
0e3038d1 1106 return armv7_probe_num_events(cpu_pmu);
d33c88c6 1107}
2a3391cd 1108
8e781f65
AT		 1109static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)
1110{
1111 armv7pmu_init(cpu_pmu);
3d1ff755 1112 cpu_pmu->name = "armv7_cortex_a12";
8e781f65 1113 cpu_pmu->map_event = armv7_a12_map_event;
8e781f65 1114 cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
0e3038d1 1115 return armv7_probe_num_events(cpu_pmu);
8e781f65
AT		 1116}
1117
03eff46c
WD		 1118static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu)
1119{
0e3038d1 1120 int ret = armv7_a12_pmu_init(cpu_pmu);
3d1ff755 1121 cpu_pmu->name = "armv7_cortex_a17";
0e3038d1 1122 return ret;
03eff46c
WD		 1123}
1124
b7aafe99
SB		 1125/*
1126 * Krait Performance Monitor Region Event Selection Register (PMRESRn)
1127 *
1128 * 31 30 24 16 8 0
1129 * +--------------------------------+
1130 * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0
1131 * +--------------------------------+
1132 * PMRESR1 | EN | CC | CC | CC | CC | N = 1, R = 1
1133 * +--------------------------------+
1134 * PMRESR2 | EN | CC | CC | CC | CC | N = 1, R = 2
1135 * +--------------------------------+
1136 * VPMRESR0 | EN | CC | CC | CC | CC | N = 2, R = ?
1137 * +--------------------------------+
1138 * EN | G=3 | G=2 | G=1 | G=0
1139 *
1140 * Event Encoding:
1141 *
1142 * hwc->config_base = 0xNRCCG
1143 *
1144 * N = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR)
1145 * R = region register
1146 * CC = class of events the group G is choosing from
1147 * G = group or particular event
1148 *
1149 * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2
1150 *
1151 * A region (R) corresponds to a piece of the CPU (execution unit, instruction
1152 * unit, etc.) while the event code (CC) corresponds to a particular class of
1153 * events (interrupts for example). An event code is broken down into
1154 * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for
1155 * example).
1156 */
1157
1158#define KRAIT_EVENT (1 << 16)
1159#define VENUM_EVENT (2 << 16)
1160#define KRAIT_EVENT_MASK (KRAIT_EVENT | VENUM_EVENT)
1161#define PMRESRn_EN BIT(31)
1162
65bab451
SB		 1163#define EVENT_REGION(event) (((event) >> 12) & 0xf) /* R */
1164#define EVENT_GROUP(event) ((event) & 0xf) /* G */
1165#define EVENT_CODE(event) (((event) >> 4) & 0xff) /* CC */
1166#define EVENT_VENUM(event) (!!(event & VENUM_EVENT)) /* N=2 */
1167#define EVENT_CPU(event) (!!(event & KRAIT_EVENT)) /* N=1 */
1168
b7aafe99
SB		 1169static u32 krait_read_pmresrn(int n)
1170{
1171 u32 val;
1172
1173 switch (n) {
1174 case 0:
1175 asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val));
1176 break;
1177 case 1:
1178 asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val));
1179 break;
1180 case 2:
1181 asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val));
1182 break;
1183 default:
1184 BUG(); /* Should be validated in krait_pmu_get_event_idx() */
1185 }
1186
1187 return val;
1188}
1189
1190static void krait_write_pmresrn(int n, u32 val)
1191{
1192 switch (n) {
1193 case 0:
1194 asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val));
1195 break;
1196 case 1:
1197 asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val));
1198 break;
1199 case 2:
1200 asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val));
1201 break;
1202 default:
1203 BUG(); /* Should be validated in krait_pmu_get_event_idx() */
1204 }
1205}
1206
65bab451 1207static u32 venum_read_pmresr(void)
b7aafe99
SB		 1208{
1209 u32 val;
1210 asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val));
1211 return val;
1212}
1213
65bab451 1214static void venum_write_pmresr(u32 val)
b7aafe99
SB		 1215{
1216 asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val));
1217}
1218
65bab451 1219static void venum_pre_pmresr(u32 *venum_orig_val, u32 *fp_orig_val)
b7aafe99
SB		 1220{
1221 u32 venum_new_val;
1222 u32 fp_new_val;
1223
1224 BUG_ON(preemptible());
1225 /* CPACR Enable CP10 and CP11 access */
1226 *venum_orig_val = get_copro_access();
1227 venum_new_val = *venum_orig_val | CPACC_SVC(10) | CPACC_SVC(11);
1228 set_copro_access(venum_new_val);
1229
1230 /* Enable FPEXC */
1231 *fp_orig_val = fmrx(FPEXC);
1232 fp_new_val = *fp_orig_val | FPEXC_EN;
1233 fmxr(FPEXC, fp_new_val);
1234}
1235
65bab451 1236static void venum_post_pmresr(u32 venum_orig_val, u32 fp_orig_val)
b7aafe99
SB		 1237{
1238 BUG_ON(preemptible());
1239 /* Restore FPEXC */
1240 fmxr(FPEXC, fp_orig_val);
1241 isb();
1242 /* Restore CPACR */
1243 set_copro_access(venum_orig_val);
1244}
1245
1246static u32 krait_get_pmresrn_event(unsigned int region)
1247{
1248 static const u32 pmresrn_table[] = { KRAIT_PMRESR0_GROUP0,
1249 KRAIT_PMRESR1_GROUP0,
1250 KRAIT_PMRESR2_GROUP0 };
1251 return pmresrn_table[region];
1252}
1253
1254static void krait_evt_setup(int idx, u32 config_base)
1255{
1256 u32 val;
1257 u32 mask;
1258 u32 vval, fval;
65bab451
SB		 1259 unsigned int region = EVENT_REGION(config_base);
1260 unsigned int group = EVENT_GROUP(config_base);
1261 unsigned int code = EVENT_CODE(config_base);
b7aafe99 1262 unsigned int group_shift;
65bab451 1263 bool venum_event = EVENT_VENUM(config_base);
b7aafe99
SB		 1264
1265 group_shift = group * 8;
1266 mask = 0xff << group_shift;
1267
1268 /* Configure evtsel for the region and group */
1269 if (venum_event)
1270 val = KRAIT_VPMRESR0_GROUP0;
1271 else
1272 val = krait_get_pmresrn_event(region);
1273 val += group;
1274 /* Mix in mode-exclusion bits */
1275 val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1);
1276 armv7_pmnc_write_evtsel(idx, val);
1277
b7aafe99 1278 if (venum_event) {
65bab451
SB		 1279 venum_pre_pmresr(&vval, &fval);
1280 val = venum_read_pmresr();
b7aafe99
SB		 1281 val &= ~mask;
1282 val |= code << group_shift;
1283 val |= PMRESRn_EN;
65bab451
SB		 1284 venum_write_pmresr(val);
1285 venum_post_pmresr(vval, fval);
b7aafe99
SB		 1286 } else {
1287 val = krait_read_pmresrn(region);
1288 val &= ~mask;
1289 val |= code << group_shift;
1290 val |= PMRESRn_EN;
1291 krait_write_pmresrn(region, val);
1292 }
1293}
1294
65bab451 1295static u32 clear_pmresrn_group(u32 val, int group)
b7aafe99
SB		 1296{
1297 u32 mask;
1298 int group_shift;
1299
1300 group_shift = group * 8;
1301 mask = 0xff << group_shift;
1302 val &= ~mask;
1303
1304 /* Don't clear enable bit if entire region isn't disabled */
1305 if (val & ~PMRESRn_EN)
1306 return val |= PMRESRn_EN;
1307
1308 return 0;
1309}
1310
1311static void krait_clearpmu(u32 config_base)
1312{
1313 u32 val;
1314 u32 vval, fval;
65bab451
SB		 1315 unsigned int region = EVENT_REGION(config_base);
1316 unsigned int group = EVENT_GROUP(config_base);
1317 bool venum_event = EVENT_VENUM(config_base);
b7aafe99
SB		 1318
1319 if (venum_event) {
65bab451
SB		 1320 venum_pre_pmresr(&vval, &fval);
1321 val = venum_read_pmresr();
1322 val = clear_pmresrn_group(val, group);
1323 venum_write_pmresr(val);
1324 venum_post_pmresr(vval, fval);
b7aafe99
SB		 1325 } else {
1326 val = krait_read_pmresrn(region);
65bab451 1327 val = clear_pmresrn_group(val, group);
b7aafe99
SB		 1328 krait_write_pmresrn(region, val);
1329 }
1330}
1331
1332static void krait_pmu_disable_event(struct perf_event *event)
1333{
1334 unsigned long flags;
1335 struct hw_perf_event *hwc = &event->hw;
1336 int idx = hwc->idx;
037e79aa 1337 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
11679250 1338 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
b7aafe99
SB		 1339
1340 /* Disable counter and interrupt */
1341 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1342
1343 /* Disable counter */
1344 armv7_pmnc_disable_counter(idx);
1345
1346 /*
1347 * Clear pmresr code (if destined for PMNx counters)
1348 */
1349 if (hwc->config_base & KRAIT_EVENT_MASK)
1350 krait_clearpmu(hwc->config_base);
1351
1352 /* Disable interrupt for this counter */
1353 armv7_pmnc_disable_intens(idx);
1354
1355 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1356}
1357
1358static void krait_pmu_enable_event(struct perf_event *event)
1359{
1360 unsigned long flags;
1361 struct hw_perf_event *hwc = &event->hw;
1362 int idx = hwc->idx;
037e79aa 1363 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
11679250 1364 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
b7aafe99
SB		 1365
1366 /*
1367 * Enable counter and interrupt, and set the counter to count
1368 * the event that we're interested in.
1369 */
1370 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1371
1372 /* Disable counter */
1373 armv7_pmnc_disable_counter(idx);
1374
1375 /*
1376 * Set event (if destined for PMNx counters)
1377 * We set the event for the cycle counter because we
1378 * have the ability to perform event filtering.
1379 */
1380 if (hwc->config_base & KRAIT_EVENT_MASK)
1381 krait_evt_setup(idx, hwc->config_base);
1382 else
1383 armv7_pmnc_write_evtsel(idx, hwc->config_base);
1384
1385 /* Enable interrupt for this counter */
1386 armv7_pmnc_enable_intens(idx);
1387
1388 /* Enable counter */
1389 armv7_pmnc_enable_counter(idx);
1390
1391 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1392}
1393
1394static void krait_pmu_reset(void *info)
1395{
1396 u32 vval, fval;
93499918
SB		 1397 struct arm_pmu *cpu_pmu = info;
1398 u32 idx, nb_cnt = cpu_pmu->num_events;
b7aafe99
SB		 1399
1400 armv7pmu_reset(info);
1401
1402 /* Clear all pmresrs */
1403 krait_write_pmresrn(0, 0);
1404 krait_write_pmresrn(1, 0);
1405 krait_write_pmresrn(2, 0);
1406
65bab451
SB		 1407 venum_pre_pmresr(&vval, &fval);
1408 venum_write_pmresr(0);
1409 venum_post_pmresr(vval, fval);
93499918
SB		 1410
1411 /* Reset PMxEVNCTCR to sane default */
1412 for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
1413 armv7_pmnc_select_counter(idx);
1414 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0));
1415 }
1416
b7aafe99
SB		 1417}
1418
1419static int krait_event_to_bit(struct perf_event *event, unsigned int region,
1420 unsigned int group)
1421{
1422 int bit;
1423 struct hw_perf_event *hwc = &event->hw;
1424 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
1425
1426 if (hwc->config_base & VENUM_EVENT)
1427 bit = KRAIT_VPMRESR0_GROUP0;
1428 else
1429 bit = krait_get_pmresrn_event(region);
1430 bit -= krait_get_pmresrn_event(0);
1431 bit += group;
1432 /*
1433 * Lower bits are reserved for use by the counters (see
1434 * armv7pmu_get_event_idx() for more info)
1435 */
1436 bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1;
1437
1438 return bit;
1439}
1440
1441/*
1442 * We check for column exclusion constraints here.
1443 * Two events cant use the same group within a pmresr register.
1444 */
1445static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc,
1446 struct perf_event *event)
1447{
1448 int idx;
6a78371a 1449 int bit = -1;
b7aafe99 1450 struct hw_perf_event *hwc = &event->hw;
65bab451
SB		 1451 unsigned int region = EVENT_REGION(hwc->config_base);
1452 unsigned int code = EVENT_CODE(hwc->config_base);
1453 unsigned int group = EVENT_GROUP(hwc->config_base);
1454 bool venum_event = EVENT_VENUM(hwc->config_base);
1455 bool krait_event = EVENT_CPU(hwc->config_base);
b7aafe99 1456
65bab451 1457 if (venum_event || krait_event) {
b7aafe99
SB		 1458 /* Ignore invalid events */
1459 if (group > 3 || region > 2)
1460 return -EINVAL;
65bab451 1461 if (venum_event && (code & 0xe0))
b7aafe99
SB		 1462 return -EINVAL;
1463
1464 bit = krait_event_to_bit(event, region, group);
1465 if (test_and_set_bit(bit, cpuc->used_mask))
1466 return -EAGAIN;
1467 }
1468
1469 idx = armv7pmu_get_event_idx(cpuc, event);
6a78371a 1470 if (idx < 0 && bit >= 0)
b7aafe99
SB		 1471 clear_bit(bit, cpuc->used_mask);
1472
1473 return idx;
1474}
1475
1476static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc,
1477 struct perf_event *event)
1478{
1479 int bit;
1480 struct hw_perf_event *hwc = &event->hw;
65bab451
SB		 1481 unsigned int region = EVENT_REGION(hwc->config_base);
1482 unsigned int group = EVENT_GROUP(hwc->config_base);
1483 bool venum_event = EVENT_VENUM(hwc->config_base);
1484 bool krait_event = EVENT_CPU(hwc->config_base);
b7aafe99 1485
65bab451 1486 if (venum_event || krait_event) {
b7aafe99
SB		 1487 bit = krait_event_to_bit(event, region, group);
1488 clear_bit(bit, cpuc->used_mask);
1489 }
1490}
1491
2a3391cd
SB		 1492static int krait_pmu_init(struct arm_pmu *cpu_pmu)
1493{
1494 armv7pmu_init(cpu_pmu);
3d1ff755 1495 cpu_pmu->name = "armv7_krait";
2a3391cd
SB		 1496 /* Some early versions of Krait don't support PC write events */
1497 if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node,
1498 "qcom,no-pc-write"))
1499 cpu_pmu->map_event = krait_map_event_no_branch;
1500 else
1501 cpu_pmu->map_event = krait_map_event;
2a3391cd 1502 cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
b7aafe99
SB		 1503 cpu_pmu->reset = krait_pmu_reset;
1504 cpu_pmu->enable = krait_pmu_enable_event;
1505 cpu_pmu->disable = krait_pmu_disable_event;
1506 cpu_pmu->get_event_idx = krait_pmu_get_event_idx;
1507 cpu_pmu->clear_event_idx = krait_pmu_clear_event_idx;
0e3038d1 1508 return armv7_probe_num_events(cpu_pmu);
2a3391cd 1509}
341e42c4
SB		 1510
1511/*
1512 * Scorpion Local Performance Monitor Register (LPMn)
1513 *
1514 * 31 30 24 16 8 0
1515 * +--------------------------------+
1516 * LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0
1517 * +--------------------------------+
1518 * LPM1 | EN | CC | CC | CC | CC | N = 1, R = 1
1519 * +--------------------------------+
1520 * LPM2 | EN | CC | CC | CC | CC | N = 1, R = 2
1521 * +--------------------------------+
1522 * L2LPM | EN | CC | CC | CC | CC | N = 1, R = 3
1523 * +--------------------------------+
1524 * VLPM | EN | CC | CC | CC | CC | N = 2, R = ?
1525 * +--------------------------------+
1526 * EN | G=3 | G=2 | G=1 | G=0
1527 *
1528 *
1529 * Event Encoding:
1530 *
1531 * hwc->config_base = 0xNRCCG
1532 *
1533 * N = prefix, 1 for Scorpion CPU (LPMn/L2LPM), 2 for Venum VFP (VLPM)
1534 * R = region register
1535 * CC = class of events the group G is choosing from
1536 * G = group or particular event
1537 *
1538 * Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2
1539 *
1540 * A region (R) corresponds to a piece of the CPU (execution unit, instruction
1541 * unit, etc.) while the event code (CC) corresponds to a particular class of
1542 * events (interrupts for example). An event code is broken down into
1543 * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for
1544 * example).
1545 */
1546
1547static u32 scorpion_read_pmresrn(int n)
1548{
1549 u32 val;
1550
1551 switch (n) {
1552 case 0:
1553 asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val));
1554 break;
1555 case 1:
1556 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
1557 break;
1558 case 2:
1559 asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val));
1560 break;
1561 case 3:
1562 asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val));
1563 break;
1564 default:
1565 BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */
1566 }
1567
1568 return val;
1569}
1570
1571static void scorpion_write_pmresrn(int n, u32 val)
1572{
1573 switch (n) {
1574 case 0:
1575 asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val));
1576 break;
1577 case 1:
1578 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val));
1579 break;
1580 case 2:
1581 asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val));
1582 break;
1583 case 3:
1584 asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val));
1585 break;
1586 default:
1587 BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */
1588 }
1589}
1590
1591static u32 scorpion_get_pmresrn_event(unsigned int region)
1592{
1593 static const u32 pmresrn_table[] = { SCORPION_LPM0_GROUP0,
1594 SCORPION_LPM1_GROUP0,
1595 SCORPION_LPM2_GROUP0,
1596 SCORPION_L2LPM_GROUP0 };
1597 return pmresrn_table[region];
1598}
1599
1600static void scorpion_evt_setup(int idx, u32 config_base)
1601{
1602 u32 val;
1603 u32 mask;
1604 u32 vval, fval;
1605 unsigned int region = EVENT_REGION(config_base);
1606 unsigned int group = EVENT_GROUP(config_base);
1607 unsigned int code = EVENT_CODE(config_base);
1608 unsigned int group_shift;
1609 bool venum_event = EVENT_VENUM(config_base);
1610
1611 group_shift = group * 8;
1612 mask = 0xff << group_shift;
1613
1614 /* Configure evtsel for the region and group */
1615 if (venum_event)
1616 val = SCORPION_VLPM_GROUP0;
1617 else
1618 val = scorpion_get_pmresrn_event(region);
1619 val += group;
1620 /* Mix in mode-exclusion bits */
1621 val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1);
1622 armv7_pmnc_write_evtsel(idx, val);
1623
1624 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0));
1625
1626 if (venum_event) {
1627 venum_pre_pmresr(&vval, &fval);
1628 val = venum_read_pmresr();
1629 val &= ~mask;
1630 val |= code << group_shift;
1631 val |= PMRESRn_EN;
1632 venum_write_pmresr(val);
1633 venum_post_pmresr(vval, fval);
1634 } else {
1635 val = scorpion_read_pmresrn(region);
1636 val &= ~mask;
1637 val |= code << group_shift;
1638 val |= PMRESRn_EN;
1639 scorpion_write_pmresrn(region, val);
1640 }
1641}
1642
1643static void scorpion_clearpmu(u32 config_base)
1644{
1645 u32 val;
1646 u32 vval, fval;
1647 unsigned int region = EVENT_REGION(config_base);
1648 unsigned int group = EVENT_GROUP(config_base);
1649 bool venum_event = EVENT_VENUM(config_base);
1650
1651 if (venum_event) {
1652 venum_pre_pmresr(&vval, &fval);
1653 val = venum_read_pmresr();
1654 val = clear_pmresrn_group(val, group);
1655 venum_write_pmresr(val);
1656 venum_post_pmresr(vval, fval);
1657 } else {
1658 val = scorpion_read_pmresrn(region);
1659 val = clear_pmresrn_group(val, group);
1660 scorpion_write_pmresrn(region, val);
1661 }
1662}
1663
1664static void scorpion_pmu_disable_event(struct perf_event *event)
1665{
1666 unsigned long flags;
1667 struct hw_perf_event *hwc = &event->hw;
1668 int idx = hwc->idx;
1669 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
1670 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
1671
1672 /* Disable counter and interrupt */
1673 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1674
1675 /* Disable counter */
1676 armv7_pmnc_disable_counter(idx);
1677
1678 /*
1679 * Clear pmresr code (if destined for PMNx counters)
1680 */
1681 if (hwc->config_base & KRAIT_EVENT_MASK)
1682 scorpion_clearpmu(hwc->config_base);
1683
1684 /* Disable interrupt for this counter */
1685 armv7_pmnc_disable_intens(idx);
1686
1687 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1688}
1689
1690static void scorpion_pmu_enable_event(struct perf_event *event)
1691{
1692 unsigned long flags;
1693 struct hw_perf_event *hwc = &event->hw;
1694 int idx = hwc->idx;
1695 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
1696 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
1697
1698 /*
1699 * Enable counter and interrupt, and set the counter to count
1700 * the event that we're interested in.
1701 */
1702 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1703
1704 /* Disable counter */
1705 armv7_pmnc_disable_counter(idx);
1706
1707 /*
1708 * Set event (if destined for PMNx counters)
1709 * We don't set the event for the cycle counter because we
1710 * don't have the ability to perform event filtering.
1711 */
1712 if (hwc->config_base & KRAIT_EVENT_MASK)
1713 scorpion_evt_setup(idx, hwc->config_base);
1714 else if (idx != ARMV7_IDX_CYCLE_COUNTER)
1715 armv7_pmnc_write_evtsel(idx, hwc->config_base);
1716
1717 /* Enable interrupt for this counter */
1718 armv7_pmnc_enable_intens(idx);
1719
1720 /* Enable counter */
1721 armv7_pmnc_enable_counter(idx);
1722
1723 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1724}
1725
1726static void scorpion_pmu_reset(void *info)
1727{
1728 u32 vval, fval;
1729 struct arm_pmu *cpu_pmu = info;
1730 u32 idx, nb_cnt = cpu_pmu->num_events;
1731
1732 armv7pmu_reset(info);
1733
1734 /* Clear all pmresrs */
1735 scorpion_write_pmresrn(0, 0);
1736 scorpion_write_pmresrn(1, 0);
1737 scorpion_write_pmresrn(2, 0);
1738 scorpion_write_pmresrn(3, 0);
1739
1740 venum_pre_pmresr(&vval, &fval);
1741 venum_write_pmresr(0);
1742 venum_post_pmresr(vval, fval);
1743
1744 /* Reset PMxEVNCTCR to sane default */
1745 for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
1746 armv7_pmnc_select_counter(idx);
1747 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0));
1748 }
1749}
1750
1751static int scorpion_event_to_bit(struct perf_event *event, unsigned int region,
1752 unsigned int group)
1753{
1754 int bit;
1755 struct hw_perf_event *hwc = &event->hw;
1756 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
1757
1758 if (hwc->config_base & VENUM_EVENT)
1759 bit = SCORPION_VLPM_GROUP0;
1760 else
1761 bit = scorpion_get_pmresrn_event(region);
1762 bit -= scorpion_get_pmresrn_event(0);
1763 bit += group;
1764 /*
1765 * Lower bits are reserved for use by the counters (see
1766 * armv7pmu_get_event_idx() for more info)
1767 */
1768 bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1;
1769
1770 return bit;
1771}
1772
1773/*
1774 * We check for column exclusion constraints here.
1775 * Two events cant use the same group within a pmresr register.
1776 */
1777static int scorpion_pmu_get_event_idx(struct pmu_hw_events *cpuc,
1778 struct perf_event *event)
1779{
1780 int idx;
1781 int bit = -1;
1782 struct hw_perf_event *hwc = &event->hw;
1783 unsigned int region = EVENT_REGION(hwc->config_base);
1784 unsigned int group = EVENT_GROUP(hwc->config_base);
1785 bool venum_event = EVENT_VENUM(hwc->config_base);
1786 bool scorpion_event = EVENT_CPU(hwc->config_base);
1787
1788 if (venum_event || scorpion_event) {
1789 /* Ignore invalid events */
1790 if (group > 3 || region > 3)
1791 return -EINVAL;
1792
1793 bit = scorpion_event_to_bit(event, region, group);
1794 if (test_and_set_bit(bit, cpuc->used_mask))
1795 return -EAGAIN;
1796 }
1797
1798 idx = armv7pmu_get_event_idx(cpuc, event);
1799 if (idx < 0 && bit >= 0)
1800 clear_bit(bit, cpuc->used_mask);
1801
1802 return idx;
1803}
1804
1805static void scorpion_pmu_clear_event_idx(struct pmu_hw_events *cpuc,
1806 struct perf_event *event)
1807{
1808 int bit;
1809 struct hw_perf_event *hwc = &event->hw;
1810 unsigned int region = EVENT_REGION(hwc->config_base);
1811 unsigned int group = EVENT_GROUP(hwc->config_base);
1812 bool venum_event = EVENT_VENUM(hwc->config_base);
1813 bool scorpion_event = EVENT_CPU(hwc->config_base);
1814
1815 if (venum_event || scorpion_event) {
1816 bit = scorpion_event_to_bit(event, region, group);
1817 clear_bit(bit, cpuc->used_mask);
1818 }
1819}
1820
1821static int scorpion_pmu_init(struct arm_pmu *cpu_pmu)
1822{
1823 armv7pmu_init(cpu_pmu);
1824 cpu_pmu->name = "armv7_scorpion";
1825 cpu_pmu->map_event = scorpion_map_event;
341e42c4
SB		 1826 cpu_pmu->reset = scorpion_pmu_reset;
1827 cpu_pmu->enable = scorpion_pmu_enable_event;
1828 cpu_pmu->disable = scorpion_pmu_disable_event;
1829 cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx;
1830 cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx;
0e3038d1 1831 return armv7_probe_num_events(cpu_pmu);
341e42c4
SB		 1832}
1833
1834static int scorpion_mp_pmu_init(struct arm_pmu *cpu_pmu)
1835{
1836 armv7pmu_init(cpu_pmu);
1837 cpu_pmu->name = "armv7_scorpion_mp";
1838 cpu_pmu->map_event = scorpion_map_event;
341e42c4
SB		 1839 cpu_pmu->reset = scorpion_pmu_reset;
1840 cpu_pmu->enable = scorpion_pmu_enable_event;
1841 cpu_pmu->disable = scorpion_pmu_disable_event;
1842 cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx;
1843 cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx;
0e3038d1 1844 return armv7_probe_num_events(cpu_pmu);
341e42c4 1845}
d33c88c6 1846
29ba0f37
MR		 1847static const struct of_device_id armv7_pmu_of_device_ids[] = {
1848 {.compatible = "arm,cortex-a17-pmu", .data = armv7_a17_pmu_init},
1849 {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
1850 {.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init},
1851 {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
1852 {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
1853 {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
1854 {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
1855 {.compatible = "qcom,krait-pmu", .data = krait_pmu_init},
1856 {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init},
1857 {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_mp_pmu_init},
1858 {},
1859};
2a3391cd 1860
29ba0f37
MR		 1861static const struct pmu_probe_info armv7_pmu_probe_table[] = {
1862 ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A8, armv7_a8_pmu_init),
1863 ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A9, armv7_a9_pmu_init),
1864 { /* sentinel value */ }
1865};
8e781f65 1866
03eff46c 1867
29ba0f37 1868static int armv7_pmu_device_probe(struct platform_device *pdev)
2a3391cd 1869{
29ba0f37
MR		 1870 return arm_pmu_device_probe(pdev, armv7_pmu_of_device_ids,
1871 armv7_pmu_probe_table);
2a3391cd 1872}
341e42c4 1873
29ba0f37
MR		 1874static struct platform_driver armv7_pmu_driver = {
1875 .driver = {
1876 .name = "armv7-pmu",
1877 .of_match_table = armv7_pmu_of_device_ids,
1878 },
1879 .probe = armv7_pmu_device_probe,
1880};
341e42c4 1881
29ba0f37 1882static int __init register_armv7_pmu_driver(void)
341e42c4 1883{
29ba0f37 1884 return platform_driver_register(&armv7_pmu_driver);
341e42c4 1885}
29ba0f37 1886device_initcall(register_armv7_pmu_driver);
43eab878 1887#endif /* CONFIG_CPU_V7 */
Linux kernel - Deliverables
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