Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/setup.c | |
3 | * | |
4 | * Copyright (C) 1995-2001 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ecea4ab6 | 10 | #include <linux/export.h> |
1da177e4 LT |
11 | #include <linux/kernel.h> |
12 | #include <linux/stddef.h> | |
13 | #include <linux/ioport.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/utsname.h> | |
16 | #include <linux/initrd.h> | |
17 | #include <linux/console.h> | |
18 | #include <linux/bootmem.h> | |
19 | #include <linux/seq_file.h> | |
894673ee | 20 | #include <linux/screen_info.h> |
883a106b | 21 | #include <linux/of_platform.h> |
1da177e4 | 22 | #include <linux/init.h> |
3c57fb43 | 23 | #include <linux/kexec.h> |
93c02ab4 | 24 | #include <linux/of_fdt.h> |
1da177e4 LT |
25 | #include <linux/cpu.h> |
26 | #include <linux/interrupt.h> | |
7bbb7940 | 27 | #include <linux/smp.h> |
e119bfff | 28 | #include <linux/proc_fs.h> |
2778f620 | 29 | #include <linux/memblock.h> |
2ecccf90 DM |
30 | #include <linux/bug.h> |
31 | #include <linux/compiler.h> | |
27a3f0e9 | 32 | #include <linux/sort.h> |
1da177e4 | 33 | |
b86040a5 | 34 | #include <asm/unified.h> |
15d07dc9 | 35 | #include <asm/cp15.h> |
1da177e4 | 36 | #include <asm/cpu.h> |
0ba8b9b2 | 37 | #include <asm/cputype.h> |
1da177e4 | 38 | #include <asm/elf.h> |
1da177e4 | 39 | #include <asm/procinfo.h> |
05774088 | 40 | #include <asm/psci.h> |
37efe642 | 41 | #include <asm/sections.h> |
1da177e4 | 42 | #include <asm/setup.h> |
f00ec48f | 43 | #include <asm/smp_plat.h> |
1da177e4 LT |
44 | #include <asm/mach-types.h> |
45 | #include <asm/cacheflush.h> | |
46097c7d | 46 | #include <asm/cachetype.h> |
1da177e4 LT |
47 | #include <asm/tlbflush.h> |
48 | ||
93c02ab4 | 49 | #include <asm/prom.h> |
1da177e4 LT |
50 | #include <asm/mach/arch.h> |
51 | #include <asm/mach/irq.h> | |
52 | #include <asm/mach/time.h> | |
9f97da78 DH |
53 | #include <asm/system_info.h> |
54 | #include <asm/system_misc.h> | |
5cbad0eb | 55 | #include <asm/traps.h> |
bff595c1 | 56 | #include <asm/unwind.h> |
1c16d242 | 57 | #include <asm/memblock.h> |
4588c34d | 58 | #include <asm/virt.h> |
1da177e4 | 59 | |
4cd9d6f7 | 60 | #include "atags.h" |
0fc1c832 | 61 | |
1da177e4 LT |
62 | |
63 | #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE) | |
64 | char fpe_type[8]; | |
65 | ||
66 | static int __init fpe_setup(char *line) | |
67 | { | |
68 | memcpy(fpe_type, line, 8); | |
69 | return 1; | |
70 | } | |
71 | ||
72 | __setup("fpe=", fpe_setup); | |
73 | #endif | |
74 | ||
4b5f32ce | 75 | extern void paging_init(struct machine_desc *desc); |
0371d3f7 | 76 | extern void sanity_check_meminfo(void); |
1da177e4 | 77 | extern void reboot_setup(char *str); |
c7909509 | 78 | extern void setup_dma_zone(struct machine_desc *desc); |
1da177e4 LT |
79 | |
80 | unsigned int processor_id; | |
c18f6581 | 81 | EXPORT_SYMBOL(processor_id); |
0385ebc0 | 82 | unsigned int __machine_arch_type __read_mostly; |
1da177e4 | 83 | EXPORT_SYMBOL(__machine_arch_type); |
0385ebc0 | 84 | unsigned int cacheid __read_mostly; |
c0e95878 | 85 | EXPORT_SYMBOL(cacheid); |
1da177e4 | 86 | |
9d20fdd5 BG |
87 | unsigned int __atags_pointer __initdata; |
88 | ||
1da177e4 LT |
89 | unsigned int system_rev; |
90 | EXPORT_SYMBOL(system_rev); | |
91 | ||
92 | unsigned int system_serial_low; | |
93 | EXPORT_SYMBOL(system_serial_low); | |
94 | ||
95 | unsigned int system_serial_high; | |
96 | EXPORT_SYMBOL(system_serial_high); | |
97 | ||
0385ebc0 | 98 | unsigned int elf_hwcap __read_mostly; |
1da177e4 LT |
99 | EXPORT_SYMBOL(elf_hwcap); |
100 | ||
101 | ||
102 | #ifdef MULTI_CPU | |
0385ebc0 | 103 | struct processor processor __read_mostly; |
1da177e4 LT |
104 | #endif |
105 | #ifdef MULTI_TLB | |
0385ebc0 | 106 | struct cpu_tlb_fns cpu_tlb __read_mostly; |
1da177e4 LT |
107 | #endif |
108 | #ifdef MULTI_USER | |
0385ebc0 | 109 | struct cpu_user_fns cpu_user __read_mostly; |
1da177e4 LT |
110 | #endif |
111 | #ifdef MULTI_CACHE | |
0385ebc0 | 112 | struct cpu_cache_fns cpu_cache __read_mostly; |
1da177e4 | 113 | #endif |
953233dc | 114 | #ifdef CONFIG_OUTER_CACHE |
0385ebc0 | 115 | struct outer_cache_fns outer_cache __read_mostly; |
6c09f09d | 116 | EXPORT_SYMBOL(outer_cache); |
953233dc | 117 | #endif |
1da177e4 | 118 | |
2ecccf90 DM |
119 | /* |
120 | * Cached cpu_architecture() result for use by assembler code. | |
121 | * C code should use the cpu_architecture() function instead of accessing this | |
122 | * variable directly. | |
123 | */ | |
124 | int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN; | |
125 | ||
ccea7a19 RK |
126 | struct stack { |
127 | u32 irq[3]; | |
128 | u32 abt[3]; | |
129 | u32 und[3]; | |
130 | } ____cacheline_aligned; | |
131 | ||
55bdd694 | 132 | #ifndef CONFIG_CPU_V7M |
ccea7a19 | 133 | static struct stack stacks[NR_CPUS]; |
55bdd694 | 134 | #endif |
ccea7a19 | 135 | |
1da177e4 LT |
136 | char elf_platform[ELF_PLATFORM_SIZE]; |
137 | EXPORT_SYMBOL(elf_platform); | |
138 | ||
1da177e4 LT |
139 | static const char *cpu_name; |
140 | static const char *machine_name; | |
48ab7e09 | 141 | static char __initdata cmd_line[COMMAND_LINE_SIZE]; |
8ff1443c | 142 | struct machine_desc *machine_desc __initdata; |
1da177e4 | 143 | |
1da177e4 LT |
144 | static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } }; |
145 | #define ENDIANNESS ((char)endian_test.l) | |
146 | ||
147 | DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data); | |
148 | ||
149 | /* | |
150 | * Standard memory resources | |
151 | */ | |
152 | static struct resource mem_res[] = { | |
740e518e GKH |
153 | { |
154 | .name = "Video RAM", | |
155 | .start = 0, | |
156 | .end = 0, | |
157 | .flags = IORESOURCE_MEM | |
158 | }, | |
159 | { | |
a36d8e5b | 160 | .name = "Kernel code", |
740e518e GKH |
161 | .start = 0, |
162 | .end = 0, | |
163 | .flags = IORESOURCE_MEM | |
164 | }, | |
165 | { | |
166 | .name = "Kernel data", | |
167 | .start = 0, | |
168 | .end = 0, | |
169 | .flags = IORESOURCE_MEM | |
170 | } | |
1da177e4 LT |
171 | }; |
172 | ||
173 | #define video_ram mem_res[0] | |
174 | #define kernel_code mem_res[1] | |
175 | #define kernel_data mem_res[2] | |
176 | ||
177 | static struct resource io_res[] = { | |
740e518e GKH |
178 | { |
179 | .name = "reserved", | |
180 | .start = 0x3bc, | |
181 | .end = 0x3be, | |
182 | .flags = IORESOURCE_IO | IORESOURCE_BUSY | |
183 | }, | |
184 | { | |
185 | .name = "reserved", | |
186 | .start = 0x378, | |
187 | .end = 0x37f, | |
188 | .flags = IORESOURCE_IO | IORESOURCE_BUSY | |
189 | }, | |
190 | { | |
191 | .name = "reserved", | |
192 | .start = 0x278, | |
193 | .end = 0x27f, | |
194 | .flags = IORESOURCE_IO | IORESOURCE_BUSY | |
195 | } | |
1da177e4 LT |
196 | }; |
197 | ||
198 | #define lp0 io_res[0] | |
199 | #define lp1 io_res[1] | |
200 | #define lp2 io_res[2] | |
201 | ||
1da177e4 LT |
202 | static const char *proc_arch[] = { |
203 | "undefined/unknown", | |
204 | "3", | |
205 | "4", | |
206 | "4T", | |
207 | "5", | |
208 | "5T", | |
209 | "5TE", | |
210 | "5TEJ", | |
211 | "6TEJ", | |
6b090a25 | 212 | "7", |
55bdd694 | 213 | "7M", |
1da177e4 LT |
214 | "?(12)", |
215 | "?(13)", | |
216 | "?(14)", | |
217 | "?(15)", | |
218 | "?(16)", | |
219 | "?(17)", | |
220 | }; | |
221 | ||
55bdd694 CM |
222 | #ifdef CONFIG_CPU_V7M |
223 | static int __get_cpu_architecture(void) | |
224 | { | |
225 | return CPU_ARCH_ARMv7M; | |
226 | } | |
227 | #else | |
2ecccf90 | 228 | static int __get_cpu_architecture(void) |
1da177e4 LT |
229 | { |
230 | int cpu_arch; | |
231 | ||
0ba8b9b2 | 232 | if ((read_cpuid_id() & 0x0008f000) == 0) { |
1da177e4 | 233 | cpu_arch = CPU_ARCH_UNKNOWN; |
0ba8b9b2 RK |
234 | } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) { |
235 | cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3; | |
236 | } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) { | |
237 | cpu_arch = (read_cpuid_id() >> 16) & 7; | |
1da177e4 LT |
238 | if (cpu_arch) |
239 | cpu_arch += CPU_ARCH_ARMv3; | |
0ba8b9b2 | 240 | } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) { |
180005c4 CM |
241 | unsigned int mmfr0; |
242 | ||
243 | /* Revised CPUID format. Read the Memory Model Feature | |
244 | * Register 0 and check for VMSAv7 or PMSAv7 */ | |
245 | asm("mrc p15, 0, %0, c0, c1, 4" | |
246 | : "=r" (mmfr0)); | |
315cfe78 CM |
247 | if ((mmfr0 & 0x0000000f) >= 0x00000003 || |
248 | (mmfr0 & 0x000000f0) >= 0x00000030) | |
180005c4 CM |
249 | cpu_arch = CPU_ARCH_ARMv7; |
250 | else if ((mmfr0 & 0x0000000f) == 0x00000002 || | |
251 | (mmfr0 & 0x000000f0) == 0x00000020) | |
252 | cpu_arch = CPU_ARCH_ARMv6; | |
253 | else | |
254 | cpu_arch = CPU_ARCH_UNKNOWN; | |
255 | } else | |
256 | cpu_arch = CPU_ARCH_UNKNOWN; | |
1da177e4 LT |
257 | |
258 | return cpu_arch; | |
259 | } | |
55bdd694 | 260 | #endif |
1da177e4 | 261 | |
2ecccf90 DM |
262 | int __pure cpu_architecture(void) |
263 | { | |
264 | BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN); | |
265 | ||
266 | return __cpu_architecture; | |
267 | } | |
268 | ||
8925ec4c WD |
269 | static int cpu_has_aliasing_icache(unsigned int arch) |
270 | { | |
271 | int aliasing_icache; | |
272 | unsigned int id_reg, num_sets, line_size; | |
273 | ||
7f94e9cc WD |
274 | /* PIPT caches never alias. */ |
275 | if (icache_is_pipt()) | |
276 | return 0; | |
277 | ||
8925ec4c WD |
278 | /* arch specifies the register format */ |
279 | switch (arch) { | |
280 | case CPU_ARCH_ARMv7: | |
5fb31a96 LW |
281 | asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR" |
282 | : /* No output operands */ | |
8925ec4c | 283 | : "r" (1)); |
5fb31a96 LW |
284 | isb(); |
285 | asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR" | |
286 | : "=r" (id_reg)); | |
8925ec4c WD |
287 | line_size = 4 << ((id_reg & 0x7) + 2); |
288 | num_sets = ((id_reg >> 13) & 0x7fff) + 1; | |
289 | aliasing_icache = (line_size * num_sets) > PAGE_SIZE; | |
290 | break; | |
291 | case CPU_ARCH_ARMv6: | |
292 | aliasing_icache = read_cpuid_cachetype() & (1 << 11); | |
293 | break; | |
294 | default: | |
295 | /* I-cache aliases will be handled by D-cache aliasing code */ | |
296 | aliasing_icache = 0; | |
297 | } | |
298 | ||
299 | return aliasing_icache; | |
300 | } | |
301 | ||
c0e95878 RK |
302 | static void __init cacheid_init(void) |
303 | { | |
c0e95878 RK |
304 | unsigned int arch = cpu_architecture(); |
305 | ||
55bdd694 CM |
306 | if (arch == CPU_ARCH_ARMv7M) { |
307 | cacheid = 0; | |
308 | } else if (arch >= CPU_ARCH_ARMv6) { | |
ac52e83f | 309 | unsigned int cachetype = read_cpuid_cachetype(); |
b57ee99f CM |
310 | if ((cachetype & (7 << 29)) == 4 << 29) { |
311 | /* ARMv7 register format */ | |
72dc53ac | 312 | arch = CPU_ARCH_ARMv7; |
b57ee99f | 313 | cacheid = CACHEID_VIPT_NONALIASING; |
7f94e9cc WD |
314 | switch (cachetype & (3 << 14)) { |
315 | case (1 << 14): | |
b57ee99f | 316 | cacheid |= CACHEID_ASID_TAGGED; |
7f94e9cc WD |
317 | break; |
318 | case (3 << 14): | |
319 | cacheid |= CACHEID_PIPT; | |
320 | break; | |
321 | } | |
8925ec4c | 322 | } else { |
72dc53ac WD |
323 | arch = CPU_ARCH_ARMv6; |
324 | if (cachetype & (1 << 23)) | |
325 | cacheid = CACHEID_VIPT_ALIASING; | |
326 | else | |
327 | cacheid = CACHEID_VIPT_NONALIASING; | |
8925ec4c | 328 | } |
72dc53ac WD |
329 | if (cpu_has_aliasing_icache(arch)) |
330 | cacheid |= CACHEID_VIPT_I_ALIASING; | |
c0e95878 RK |
331 | } else { |
332 | cacheid = CACHEID_VIVT; | |
333 | } | |
2b4ae1f1 RK |
334 | |
335 | printk("CPU: %s data cache, %s instruction cache\n", | |
336 | cache_is_vivt() ? "VIVT" : | |
337 | cache_is_vipt_aliasing() ? "VIPT aliasing" : | |
7f94e9cc | 338 | cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown", |
2b4ae1f1 RK |
339 | cache_is_vivt() ? "VIVT" : |
340 | icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" : | |
8925ec4c | 341 | icache_is_vipt_aliasing() ? "VIPT aliasing" : |
7f94e9cc | 342 | icache_is_pipt() ? "PIPT" : |
2b4ae1f1 | 343 | cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown"); |
c0e95878 RK |
344 | } |
345 | ||
1da177e4 LT |
346 | /* |
347 | * These functions re-use the assembly code in head.S, which | |
348 | * already provide the required functionality. | |
349 | */ | |
0f44ba1d | 350 | extern struct proc_info_list *lookup_processor_type(unsigned int); |
6fc31d54 | 351 | |
93c02ab4 | 352 | void __init early_print(const char *str, ...) |
6fc31d54 RK |
353 | { |
354 | extern void printascii(const char *); | |
355 | char buf[256]; | |
356 | va_list ap; | |
357 | ||
358 | va_start(ap, str); | |
359 | vsnprintf(buf, sizeof(buf), str, ap); | |
360 | va_end(ap); | |
361 | ||
362 | #ifdef CONFIG_DEBUG_LL | |
363 | printascii(buf); | |
364 | #endif | |
365 | printk("%s", buf); | |
366 | } | |
367 | ||
8164f7af SB |
368 | static void __init cpuid_init_hwcaps(void) |
369 | { | |
a469abd0 | 370 | unsigned int divide_instrs, vmsa; |
8164f7af SB |
371 | |
372 | if (cpu_architecture() < CPU_ARCH_ARMv7) | |
373 | return; | |
374 | ||
375 | divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24; | |
376 | ||
377 | switch (divide_instrs) { | |
378 | case 2: | |
379 | elf_hwcap |= HWCAP_IDIVA; | |
380 | case 1: | |
381 | elf_hwcap |= HWCAP_IDIVT; | |
382 | } | |
a469abd0 WD |
383 | |
384 | /* LPAE implies atomic ldrd/strd instructions */ | |
385 | vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0; | |
386 | if (vmsa >= 5) | |
387 | elf_hwcap |= HWCAP_LPAE; | |
8164f7af SB |
388 | } |
389 | ||
f159f4ed TL |
390 | static void __init feat_v6_fixup(void) |
391 | { | |
392 | int id = read_cpuid_id(); | |
393 | ||
394 | if ((id & 0xff0f0000) != 0x41070000) | |
395 | return; | |
396 | ||
397 | /* | |
398 | * HWCAP_TLS is available only on 1136 r1p0 and later, | |
399 | * see also kuser_get_tls_init. | |
400 | */ | |
401 | if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0)) | |
402 | elf_hwcap &= ~HWCAP_TLS; | |
403 | } | |
404 | ||
ccea7a19 RK |
405 | /* |
406 | * cpu_init - initialise one CPU. | |
407 | * | |
90f1e084 | 408 | * cpu_init sets up the per-CPU stacks. |
ccea7a19 | 409 | */ |
1783d457 | 410 | void notrace cpu_init(void) |
ccea7a19 | 411 | { |
55bdd694 | 412 | #ifndef CONFIG_CPU_V7M |
ccea7a19 RK |
413 | unsigned int cpu = smp_processor_id(); |
414 | struct stack *stk = &stacks[cpu]; | |
415 | ||
416 | if (cpu >= NR_CPUS) { | |
417 | printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu); | |
418 | BUG(); | |
419 | } | |
420 | ||
14318efb RH |
421 | /* |
422 | * This only works on resume and secondary cores. For booting on the | |
423 | * boot cpu, smp_prepare_boot_cpu is called after percpu area setup. | |
424 | */ | |
425 | set_my_cpu_offset(per_cpu_offset(cpu)); | |
426 | ||
b69874e4 RK |
427 | cpu_proc_init(); |
428 | ||
b86040a5 CM |
429 | /* |
430 | * Define the placement constraint for the inline asm directive below. | |
431 | * In Thumb-2, msr with an immediate value is not allowed. | |
432 | */ | |
433 | #ifdef CONFIG_THUMB2_KERNEL | |
434 | #define PLC "r" | |
435 | #else | |
436 | #define PLC "I" | |
437 | #endif | |
438 | ||
ccea7a19 RK |
439 | /* |
440 | * setup stacks for re-entrant exception handlers | |
441 | */ | |
442 | __asm__ ( | |
443 | "msr cpsr_c, %1\n\t" | |
b86040a5 CM |
444 | "add r14, %0, %2\n\t" |
445 | "mov sp, r14\n\t" | |
ccea7a19 | 446 | "msr cpsr_c, %3\n\t" |
b86040a5 CM |
447 | "add r14, %0, %4\n\t" |
448 | "mov sp, r14\n\t" | |
ccea7a19 | 449 | "msr cpsr_c, %5\n\t" |
b86040a5 CM |
450 | "add r14, %0, %6\n\t" |
451 | "mov sp, r14\n\t" | |
ccea7a19 RK |
452 | "msr cpsr_c, %7" |
453 | : | |
454 | : "r" (stk), | |
b86040a5 | 455 | PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), |
ccea7a19 | 456 | "I" (offsetof(struct stack, irq[0])), |
b86040a5 | 457 | PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE), |
ccea7a19 | 458 | "I" (offsetof(struct stack, abt[0])), |
b86040a5 | 459 | PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE), |
ccea7a19 | 460 | "I" (offsetof(struct stack, und[0])), |
b86040a5 | 461 | PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) |
aaaa3f9e | 462 | : "r14"); |
55bdd694 | 463 | #endif |
ccea7a19 RK |
464 | } |
465 | ||
eb50439b WD |
466 | int __cpu_logical_map[NR_CPUS]; |
467 | ||
468 | void __init smp_setup_processor_id(void) | |
469 | { | |
470 | int i; | |
cb8cf4f8 LP |
471 | u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; |
472 | u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
eb50439b WD |
473 | |
474 | cpu_logical_map(0) = cpu; | |
cb8cf4f8 | 475 | for (i = 1; i < nr_cpu_ids; ++i) |
eb50439b WD |
476 | cpu_logical_map(i) = i == cpu ? 0 : i; |
477 | ||
cb8cf4f8 | 478 | printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr); |
eb50439b WD |
479 | } |
480 | ||
8cf72172 LP |
481 | struct mpidr_hash mpidr_hash; |
482 | #ifdef CONFIG_SMP | |
483 | /** | |
484 | * smp_build_mpidr_hash - Pre-compute shifts required at each affinity | |
485 | * level in order to build a linear index from an | |
486 | * MPIDR value. Resulting algorithm is a collision | |
487 | * free hash carried out through shifting and ORing | |
488 | */ | |
489 | static void __init smp_build_mpidr_hash(void) | |
490 | { | |
491 | u32 i, affinity; | |
492 | u32 fs[3], bits[3], ls, mask = 0; | |
493 | /* | |
494 | * Pre-scan the list of MPIDRS and filter out bits that do | |
495 | * not contribute to affinity levels, ie they never toggle. | |
496 | */ | |
497 | for_each_possible_cpu(i) | |
498 | mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); | |
499 | pr_debug("mask of set bits 0x%x\n", mask); | |
500 | /* | |
501 | * Find and stash the last and first bit set at all affinity levels to | |
502 | * check how many bits are required to represent them. | |
503 | */ | |
504 | for (i = 0; i < 3; i++) { | |
505 | affinity = MPIDR_AFFINITY_LEVEL(mask, i); | |
506 | /* | |
507 | * Find the MSB bit and LSB bits position | |
508 | * to determine how many bits are required | |
509 | * to express the affinity level. | |
510 | */ | |
511 | ls = fls(affinity); | |
512 | fs[i] = affinity ? ffs(affinity) - 1 : 0; | |
513 | bits[i] = ls - fs[i]; | |
514 | } | |
515 | /* | |
516 | * An index can be created from the MPIDR by isolating the | |
517 | * significant bits at each affinity level and by shifting | |
518 | * them in order to compress the 24 bits values space to a | |
519 | * compressed set of values. This is equivalent to hashing | |
520 | * the MPIDR through shifting and ORing. It is a collision free | |
521 | * hash though not minimal since some levels might contain a number | |
522 | * of CPUs that is not an exact power of 2 and their bit | |
523 | * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}. | |
524 | */ | |
525 | mpidr_hash.shift_aff[0] = fs[0]; | |
526 | mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0]; | |
527 | mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] - | |
528 | (bits[1] + bits[0]); | |
529 | mpidr_hash.mask = mask; | |
530 | mpidr_hash.bits = bits[2] + bits[1] + bits[0]; | |
531 | pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n", | |
532 | mpidr_hash.shift_aff[0], | |
533 | mpidr_hash.shift_aff[1], | |
534 | mpidr_hash.shift_aff[2], | |
535 | mpidr_hash.mask, | |
536 | mpidr_hash.bits); | |
537 | /* | |
538 | * 4x is an arbitrary value used to warn on a hash table much bigger | |
539 | * than expected on most systems. | |
540 | */ | |
541 | if (mpidr_hash_size() > 4 * num_possible_cpus()) | |
542 | pr_warn("Large number of MPIDR hash buckets detected\n"); | |
543 | sync_cache_w(&mpidr_hash); | |
544 | } | |
545 | #endif | |
546 | ||
b69874e4 RK |
547 | static void __init setup_processor(void) |
548 | { | |
549 | struct proc_info_list *list; | |
550 | ||
551 | /* | |
552 | * locate processor in the list of supported processor | |
553 | * types. The linker builds this table for us from the | |
554 | * entries in arch/arm/mm/proc-*.S | |
555 | */ | |
556 | list = lookup_processor_type(read_cpuid_id()); | |
557 | if (!list) { | |
558 | printk("CPU configuration botched (ID %08x), unable " | |
559 | "to continue.\n", read_cpuid_id()); | |
560 | while (1); | |
561 | } | |
562 | ||
563 | cpu_name = list->cpu_name; | |
2ecccf90 | 564 | __cpu_architecture = __get_cpu_architecture(); |
b69874e4 RK |
565 | |
566 | #ifdef MULTI_CPU | |
567 | processor = *list->proc; | |
568 | #endif | |
569 | #ifdef MULTI_TLB | |
570 | cpu_tlb = *list->tlb; | |
571 | #endif | |
572 | #ifdef MULTI_USER | |
573 | cpu_user = *list->user; | |
574 | #endif | |
575 | #ifdef MULTI_CACHE | |
576 | cpu_cache = *list->cache; | |
577 | #endif | |
578 | ||
579 | printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n", | |
580 | cpu_name, read_cpuid_id(), read_cpuid_id() & 15, | |
581 | proc_arch[cpu_architecture()], cr_alignment); | |
582 | ||
a34dbfb0 WD |
583 | snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c", |
584 | list->arch_name, ENDIANNESS); | |
585 | snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c", | |
586 | list->elf_name, ENDIANNESS); | |
b69874e4 | 587 | elf_hwcap = list->elf_hwcap; |
8164f7af SB |
588 | |
589 | cpuid_init_hwcaps(); | |
590 | ||
b69874e4 | 591 | #ifndef CONFIG_ARM_THUMB |
c40e3641 | 592 | elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT); |
b69874e4 RK |
593 | #endif |
594 | ||
595 | feat_v6_fixup(); | |
596 | ||
597 | cacheid_init(); | |
598 | cpu_init(); | |
599 | } | |
600 | ||
93c02ab4 | 601 | void __init dump_machine_table(void) |
1da177e4 | 602 | { |
dce72dd0 | 603 | struct machine_desc *p; |
1da177e4 | 604 | |
6291319d GL |
605 | early_print("Available machine support:\n\nID (hex)\tNAME\n"); |
606 | for_each_machine_desc(p) | |
dce72dd0 | 607 | early_print("%08x\t%s\n", p->nr, p->name); |
1da177e4 | 608 | |
dce72dd0 | 609 | early_print("\nPlease check your kernel config and/or bootloader.\n"); |
1da177e4 | 610 | |
dce72dd0 NP |
611 | while (true) |
612 | /* can't use cpu_relax() here as it may require MMU setup */; | |
1da177e4 LT |
613 | } |
614 | ||
a5d5f7da | 615 | int __init arm_add_memory(phys_addr_t start, phys_addr_t size) |
3a669411 | 616 | { |
4b5f32ce NP |
617 | struct membank *bank = &meminfo.bank[meminfo.nr_banks]; |
618 | ||
619 | if (meminfo.nr_banks >= NR_BANKS) { | |
620 | printk(KERN_CRIT "NR_BANKS too low, " | |
29a38193 | 621 | "ignoring memory at 0x%08llx\n", (long long)start); |
4b5f32ce NP |
622 | return -EINVAL; |
623 | } | |
05f96ef1 | 624 | |
3a669411 RK |
625 | /* |
626 | * Ensure that start/size are aligned to a page boundary. | |
627 | * Size is appropriately rounded down, start is rounded up. | |
628 | */ | |
629 | size -= start & ~PAGE_MASK; | |
05f96ef1 | 630 | bank->start = PAGE_ALIGN(start); |
e5ab8580 | 631 | |
4e1db26a | 632 | #ifndef CONFIG_ARM_LPAE |
e5ab8580 WD |
633 | if (bank->start + size < bank->start) { |
634 | printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " | |
635 | "32-bit physical address space\n", (long long)start); | |
636 | /* | |
637 | * To ensure bank->start + bank->size is representable in | |
638 | * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB. | |
639 | * This means we lose a page after masking. | |
640 | */ | |
641 | size = ULONG_MAX - bank->start; | |
642 | } | |
643 | #endif | |
644 | ||
a5d5f7da | 645 | bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1); |
4b5f32ce NP |
646 | |
647 | /* | |
648 | * Check whether this memory region has non-zero size or | |
649 | * invalid node number. | |
650 | */ | |
be370302 | 651 | if (bank->size == 0) |
4b5f32ce NP |
652 | return -EINVAL; |
653 | ||
654 | meminfo.nr_banks++; | |
655 | return 0; | |
3a669411 RK |
656 | } |
657 | ||
1da177e4 LT |
658 | /* |
659 | * Pick out the memory size. We look for mem=size@start, | |
660 | * where start and size are "size[KkMm]" | |
661 | */ | |
2b0d8c25 | 662 | static int __init early_mem(char *p) |
1da177e4 LT |
663 | { |
664 | static int usermem __initdata = 0; | |
a5d5f7da | 665 | phys_addr_t size; |
f60892d3 | 666 | phys_addr_t start; |
2b0d8c25 | 667 | char *endp; |
1da177e4 LT |
668 | |
669 | /* | |
670 | * If the user specifies memory size, we | |
671 | * blow away any automatically generated | |
672 | * size. | |
673 | */ | |
674 | if (usermem == 0) { | |
675 | usermem = 1; | |
676 | meminfo.nr_banks = 0; | |
677 | } | |
678 | ||
679 | start = PHYS_OFFSET; | |
2b0d8c25 JK |
680 | size = memparse(p, &endp); |
681 | if (*endp == '@') | |
682 | start = memparse(endp + 1, NULL); | |
1da177e4 | 683 | |
1c97b73e | 684 | arm_add_memory(start, size); |
1da177e4 | 685 | |
2b0d8c25 | 686 | return 0; |
1da177e4 | 687 | } |
2b0d8c25 | 688 | early_param("mem", early_mem); |
1da177e4 | 689 | |
11b9369c | 690 | static void __init request_standard_resources(struct machine_desc *mdesc) |
1da177e4 | 691 | { |
11b9369c | 692 | struct memblock_region *region; |
1da177e4 | 693 | struct resource *res; |
1da177e4 | 694 | |
37efe642 RK |
695 | kernel_code.start = virt_to_phys(_text); |
696 | kernel_code.end = virt_to_phys(_etext - 1); | |
842eab40 | 697 | kernel_data.start = virt_to_phys(_sdata); |
37efe642 | 698 | kernel_data.end = virt_to_phys(_end - 1); |
1da177e4 | 699 | |
11b9369c | 700 | for_each_memblock(memory, region) { |
1da177e4 LT |
701 | res = alloc_bootmem_low(sizeof(*res)); |
702 | res->name = "System RAM"; | |
11b9369c DZ |
703 | res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); |
704 | res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; | |
1da177e4 LT |
705 | res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; |
706 | ||
707 | request_resource(&iomem_resource, res); | |
708 | ||
709 | if (kernel_code.start >= res->start && | |
710 | kernel_code.end <= res->end) | |
711 | request_resource(res, &kernel_code); | |
712 | if (kernel_data.start >= res->start && | |
713 | kernel_data.end <= res->end) | |
714 | request_resource(res, &kernel_data); | |
715 | } | |
716 | ||
717 | if (mdesc->video_start) { | |
718 | video_ram.start = mdesc->video_start; | |
719 | video_ram.end = mdesc->video_end; | |
720 | request_resource(&iomem_resource, &video_ram); | |
721 | } | |
722 | ||
723 | /* | |
724 | * Some machines don't have the possibility of ever | |
725 | * possessing lp0, lp1 or lp2 | |
726 | */ | |
727 | if (mdesc->reserve_lp0) | |
728 | request_resource(&ioport_resource, &lp0); | |
729 | if (mdesc->reserve_lp1) | |
730 | request_resource(&ioport_resource, &lp1); | |
731 | if (mdesc->reserve_lp2) | |
732 | request_resource(&ioport_resource, &lp2); | |
733 | } | |
734 | ||
1da177e4 LT |
735 | #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) |
736 | struct screen_info screen_info = { | |
737 | .orig_video_lines = 30, | |
738 | .orig_video_cols = 80, | |
739 | .orig_video_mode = 0, | |
740 | .orig_video_ega_bx = 0, | |
741 | .orig_video_isVGA = 1, | |
742 | .orig_video_points = 8 | |
743 | }; | |
4394c124 | 744 | #endif |
1da177e4 | 745 | |
1da177e4 LT |
746 | static int __init customize_machine(void) |
747 | { | |
883a106b AB |
748 | /* |
749 | * customizes platform devices, or adds new ones | |
750 | * On DT based machines, we fall back to populating the | |
751 | * machine from the device tree, if no callback is provided, | |
752 | * otherwise we would always need an init_machine callback. | |
753 | */ | |
8ff1443c RK |
754 | if (machine_desc->init_machine) |
755 | machine_desc->init_machine(); | |
883a106b AB |
756 | #ifdef CONFIG_OF |
757 | else | |
758 | of_platform_populate(NULL, of_default_bus_match_table, | |
759 | NULL, NULL); | |
760 | #endif | |
1da177e4 LT |
761 | return 0; |
762 | } | |
763 | arch_initcall(customize_machine); | |
764 | ||
90de4137 SG |
765 | static int __init init_machine_late(void) |
766 | { | |
767 | if (machine_desc->init_late) | |
768 | machine_desc->init_late(); | |
769 | return 0; | |
770 | } | |
771 | late_initcall(init_machine_late); | |
772 | ||
3c57fb43 MW |
773 | #ifdef CONFIG_KEXEC |
774 | static inline unsigned long long get_total_mem(void) | |
775 | { | |
776 | unsigned long total; | |
777 | ||
778 | total = max_low_pfn - min_low_pfn; | |
779 | return total << PAGE_SHIFT; | |
780 | } | |
781 | ||
782 | /** | |
783 | * reserve_crashkernel() - reserves memory are for crash kernel | |
784 | * | |
785 | * This function reserves memory area given in "crashkernel=" kernel command | |
786 | * line parameter. The memory reserved is used by a dump capture kernel when | |
787 | * primary kernel is crashing. | |
788 | */ | |
789 | static void __init reserve_crashkernel(void) | |
790 | { | |
791 | unsigned long long crash_size, crash_base; | |
792 | unsigned long long total_mem; | |
793 | int ret; | |
794 | ||
795 | total_mem = get_total_mem(); | |
796 | ret = parse_crashkernel(boot_command_line, total_mem, | |
797 | &crash_size, &crash_base); | |
798 | if (ret) | |
799 | return; | |
800 | ||
801 | ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE); | |
802 | if (ret < 0) { | |
803 | printk(KERN_WARNING "crashkernel reservation failed - " | |
804 | "memory is in use (0x%lx)\n", (unsigned long)crash_base); | |
805 | return; | |
806 | } | |
807 | ||
808 | printk(KERN_INFO "Reserving %ldMB of memory at %ldMB " | |
809 | "for crashkernel (System RAM: %ldMB)\n", | |
810 | (unsigned long)(crash_size >> 20), | |
811 | (unsigned long)(crash_base >> 20), | |
812 | (unsigned long)(total_mem >> 20)); | |
813 | ||
814 | crashk_res.start = crash_base; | |
815 | crashk_res.end = crash_base + crash_size - 1; | |
816 | insert_resource(&iomem_resource, &crashk_res); | |
817 | } | |
818 | #else | |
819 | static inline void reserve_crashkernel(void) {} | |
820 | #endif /* CONFIG_KEXEC */ | |
821 | ||
27a3f0e9 NP |
822 | static int __init meminfo_cmp(const void *_a, const void *_b) |
823 | { | |
824 | const struct membank *a = _a, *b = _b; | |
825 | long cmp = bank_pfn_start(a) - bank_pfn_start(b); | |
826 | return cmp < 0 ? -1 : cmp > 0 ? 1 : 0; | |
827 | } | |
6291319d | 828 | |
4588c34d DM |
829 | void __init hyp_mode_check(void) |
830 | { | |
831 | #ifdef CONFIG_ARM_VIRT_EXT | |
832 | if (is_hyp_mode_available()) { | |
833 | pr_info("CPU: All CPU(s) started in HYP mode.\n"); | |
834 | pr_info("CPU: Virtualization extensions available.\n"); | |
835 | } else if (is_hyp_mode_mismatched()) { | |
836 | pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n", | |
837 | __boot_cpu_mode & MODE_MASK); | |
838 | pr_warn("CPU: This may indicate a broken bootloader or firmware.\n"); | |
839 | } else | |
840 | pr_info("CPU: All CPU(s) started in SVC mode.\n"); | |
841 | #endif | |
842 | } | |
843 | ||
6291319d GL |
844 | void __init setup_arch(char **cmdline_p) |
845 | { | |
846 | struct machine_desc *mdesc; | |
847 | ||
6291319d | 848 | setup_processor(); |
93c02ab4 GL |
849 | mdesc = setup_machine_fdt(__atags_pointer); |
850 | if (!mdesc) | |
b8b499c8 | 851 | mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type); |
6291319d GL |
852 | machine_desc = mdesc; |
853 | machine_name = mdesc->name; | |
854 | ||
c7909509 MS |
855 | setup_dma_zone(mdesc); |
856 | ||
b44c350d RK |
857 | if (mdesc->restart_mode) |
858 | reboot_setup(&mdesc->restart_mode); | |
6291319d | 859 | |
37efe642 RK |
860 | init_mm.start_code = (unsigned long) _text; |
861 | init_mm.end_code = (unsigned long) _etext; | |
862 | init_mm.end_data = (unsigned long) _edata; | |
863 | init_mm.brk = (unsigned long) _end; | |
1da177e4 | 864 | |
48ab7e09 JK |
865 | /* populate cmd_line too for later use, preserving boot_command_line */ |
866 | strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE); | |
867 | *cmdline_p = cmd_line; | |
2b0d8c25 JK |
868 | |
869 | parse_early_param(); | |
870 | ||
27a3f0e9 | 871 | sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL); |
0371d3f7 | 872 | sanity_check_meminfo(); |
8d717a52 | 873 | arm_memblock_init(&meminfo, mdesc); |
2778f620 | 874 | |
4b5f32ce | 875 | paging_init(mdesc); |
11b9369c | 876 | request_standard_resources(mdesc); |
1da177e4 | 877 | |
a528721d RK |
878 | if (mdesc->restart) |
879 | arm_pm_restart = mdesc->restart; | |
880 | ||
93c02ab4 GL |
881 | unflatten_device_tree(); |
882 | ||
5587164e | 883 | arm_dt_init_cpu_maps(); |
05774088 | 884 | psci_init(); |
7bbb7940 | 885 | #ifdef CONFIG_SMP |
abcee5fb | 886 | if (is_smp()) { |
b382b940 JM |
887 | if (!mdesc->smp_init || !mdesc->smp_init()) { |
888 | if (psci_smp_available()) | |
889 | smp_set_ops(&psci_smp_ops); | |
890 | else if (mdesc->smp) | |
891 | smp_set_ops(mdesc->smp); | |
892 | } | |
f00ec48f | 893 | smp_init_cpus(); |
8cf72172 | 894 | smp_build_mpidr_hash(); |
abcee5fb | 895 | } |
7bbb7940 | 896 | #endif |
4588c34d DM |
897 | |
898 | if (!is_smp()) | |
899 | hyp_mode_check(); | |
900 | ||
3c57fb43 | 901 | reserve_crashkernel(); |
7bbb7940 | 902 | |
52108641 | 903 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
904 | handle_arch_irq = mdesc->handle_irq; | |
905 | #endif | |
1da177e4 LT |
906 | |
907 | #ifdef CONFIG_VT | |
908 | #if defined(CONFIG_VGA_CONSOLE) | |
909 | conswitchp = &vga_con; | |
910 | #elif defined(CONFIG_DUMMY_CONSOLE) | |
911 | conswitchp = &dummy_con; | |
912 | #endif | |
913 | #endif | |
dec12e62 RK |
914 | |
915 | if (mdesc->init_early) | |
916 | mdesc->init_early(); | |
1da177e4 LT |
917 | } |
918 | ||
919 | ||
920 | static int __init topology_init(void) | |
921 | { | |
922 | int cpu; | |
923 | ||
66fb8bd2 RK |
924 | for_each_possible_cpu(cpu) { |
925 | struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu); | |
926 | cpuinfo->cpu.hotpluggable = 1; | |
927 | register_cpu(&cpuinfo->cpu, cpu); | |
928 | } | |
1da177e4 LT |
929 | |
930 | return 0; | |
931 | } | |
1da177e4 LT |
932 | subsys_initcall(topology_init); |
933 | ||
e119bfff RK |
934 | #ifdef CONFIG_HAVE_PROC_CPU |
935 | static int __init proc_cpu_init(void) | |
936 | { | |
937 | struct proc_dir_entry *res; | |
938 | ||
939 | res = proc_mkdir("cpu", NULL); | |
940 | if (!res) | |
941 | return -ENOMEM; | |
942 | return 0; | |
943 | } | |
944 | fs_initcall(proc_cpu_init); | |
945 | #endif | |
946 | ||
1da177e4 LT |
947 | static const char *hwcap_str[] = { |
948 | "swp", | |
949 | "half", | |
950 | "thumb", | |
951 | "26bit", | |
952 | "fastmult", | |
953 | "fpa", | |
954 | "vfp", | |
955 | "edsp", | |
956 | "java", | |
8f7f9435 | 957 | "iwmmxt", |
99e4a6dd | 958 | "crunch", |
4369ae16 | 959 | "thumbee", |
2bedbdf4 | 960 | "neon", |
7279dc3e CM |
961 | "vfpv3", |
962 | "vfpv3d16", | |
254cdf8e WD |
963 | "tls", |
964 | "vfpv4", | |
965 | "idiva", | |
966 | "idivt", | |
a469abd0 | 967 | "lpae", |
1da177e4 LT |
968 | NULL |
969 | }; | |
970 | ||
1da177e4 LT |
971 | static int c_show(struct seq_file *m, void *v) |
972 | { | |
b4b8f770 LP |
973 | int i, j; |
974 | u32 cpuid; | |
1da177e4 | 975 | |
1da177e4 | 976 | for_each_online_cpu(i) { |
15559722 RK |
977 | /* |
978 | * glibc reads /proc/cpuinfo to determine the number of | |
979 | * online processors, looking for lines beginning with | |
980 | * "processor". Give glibc what it expects. | |
981 | */ | |
982 | seq_printf(m, "processor\t: %d\n", i); | |
b4b8f770 LP |
983 | cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id(); |
984 | seq_printf(m, "model name\t: %s rev %d (%s)\n", | |
985 | cpu_name, cpuid & 15, elf_platform); | |
986 | ||
987 | #if defined(CONFIG_SMP) | |
988 | seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", | |
1da177e4 LT |
989 | per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ), |
990 | (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100); | |
b4b8f770 LP |
991 | #else |
992 | seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", | |
993 | loops_per_jiffy / (500000/HZ), | |
994 | (loops_per_jiffy / (5000/HZ)) % 100); | |
1da177e4 | 995 | #endif |
b4b8f770 LP |
996 | /* dump out the processor features */ |
997 | seq_puts(m, "Features\t: "); | |
1da177e4 | 998 | |
b4b8f770 LP |
999 | for (j = 0; hwcap_str[j]; j++) |
1000 | if (elf_hwcap & (1 << j)) | |
1001 | seq_printf(m, "%s ", hwcap_str[j]); | |
1da177e4 | 1002 | |
b4b8f770 LP |
1003 | seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24); |
1004 | seq_printf(m, "CPU architecture: %s\n", | |
1005 | proc_arch[cpu_architecture()]); | |
1da177e4 | 1006 | |
b4b8f770 LP |
1007 | if ((cpuid & 0x0008f000) == 0x00000000) { |
1008 | /* pre-ARM7 */ | |
1009 | seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4); | |
1da177e4 | 1010 | } else { |
b4b8f770 LP |
1011 | if ((cpuid & 0x0008f000) == 0x00007000) { |
1012 | /* ARM7 */ | |
1013 | seq_printf(m, "CPU variant\t: 0x%02x\n", | |
1014 | (cpuid >> 16) & 127); | |
1015 | } else { | |
1016 | /* post-ARM7 */ | |
1017 | seq_printf(m, "CPU variant\t: 0x%x\n", | |
1018 | (cpuid >> 20) & 15); | |
1019 | } | |
1020 | seq_printf(m, "CPU part\t: 0x%03x\n", | |
1021 | (cpuid >> 4) & 0xfff); | |
1da177e4 | 1022 | } |
b4b8f770 | 1023 | seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15); |
1da177e4 | 1024 | } |
1da177e4 LT |
1025 | |
1026 | seq_printf(m, "Hardware\t: %s\n", machine_name); | |
1027 | seq_printf(m, "Revision\t: %04x\n", system_rev); | |
1028 | seq_printf(m, "Serial\t\t: %08x%08x\n", | |
1029 | system_serial_high, system_serial_low); | |
1030 | ||
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | static void *c_start(struct seq_file *m, loff_t *pos) | |
1035 | { | |
1036 | return *pos < 1 ? (void *)1 : NULL; | |
1037 | } | |
1038 | ||
1039 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
1040 | { | |
1041 | ++*pos; | |
1042 | return NULL; | |
1043 | } | |
1044 | ||
1045 | static void c_stop(struct seq_file *m, void *v) | |
1046 | { | |
1047 | } | |
1048 | ||
2ffd6e18 | 1049 | const struct seq_operations cpuinfo_op = { |
1da177e4 LT |
1050 | .start = c_start, |
1051 | .next = c_next, | |
1052 | .stop = c_stop, | |
1053 | .show = c_show | |
1054 | }; |