Commit | Line | Data |
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f6b0fa02 | 1 | #include <linux/linkage.h> |
941aefac | 2 | #include <linux/threads.h> |
f6b0fa02 RK |
3 | #include <asm/asm-offsets.h> |
4 | #include <asm/assembler.h> | |
5 | #include <asm/glue-cache.h> | |
6 | #include <asm/glue-proc.h> | |
7 | #include <asm/system.h> | |
8 | .text | |
9 | ||
10 | /* | |
11 | * Save CPU state for a suspend | |
12 | * r1 = v:p offset | |
3799bbe5 | 13 | * r2 = suspend function arg0 |
e8856a87 | 14 | * r3 = suspend function |
f6b0fa02 | 15 | */ |
2c74a0ce | 16 | ENTRY(__cpu_suspend) |
e8856a87 | 17 | stmfd sp!, {r4 - r11, lr} |
f6b0fa02 RK |
18 | #ifdef MULTI_CPU |
19 | ldr r10, =processor | |
8111eaa6 | 20 | ldr r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state |
f6b0fa02 | 21 | ldr ip, [r10, #CPU_DO_RESUME] @ virtual resume function |
941aefac | 22 | #else |
8111eaa6 | 23 | ldr r5, =cpu_suspend_size |
6b5f6ab0 | 24 | ldr ip, =cpu_do_resume |
3fd431bd | 25 | #endif |
8111eaa6 RK |
26 | mov r6, sp @ current virtual SP |
27 | sub sp, sp, r5 @ allocate CPU state on stack | |
29cb3cd2 | 28 | mov r0, sp @ save pointer to CPU save block |
6b5f6ab0 | 29 | add ip, ip, r1 @ convert resume fn to phys |
8111eaa6 RK |
30 | stmfd sp!, {r1, r6, ip} @ save v:p, virt SP, phys resume fn |
31 | ldr r5, =sleep_save_sp | |
32 | add r6, sp, r1 @ convert SP to phys | |
e8856a87 | 33 | stmfd sp!, {r2, r3} @ save suspend func arg and pointer |
941aefac RK |
34 | #ifdef CONFIG_SMP |
35 | ALT_SMP(mrc p15, 0, lr, c0, c0, 5) | |
36 | ALT_UP(mov lr, #0) | |
37 | and lr, lr, #15 | |
8111eaa6 | 38 | str r6, [r5, lr, lsl #2] @ save phys SP |
941aefac | 39 | #else |
8111eaa6 | 40 | str r6, [r5] @ save phys SP |
941aefac | 41 | #endif |
3fd431bd RK |
42 | #ifdef MULTI_CPU |
43 | mov lr, pc | |
44 | ldr pc, [r10, #CPU_DO_SUSPEND] @ save CPU state | |
45 | #else | |
f6b0fa02 RK |
46 | bl cpu_do_suspend |
47 | #endif | |
48 | ||
49 | @ flush data cache | |
50 | #ifdef MULTI_CACHE | |
51 | ldr r10, =cpu_cache | |
3799bbe5 | 52 | mov lr, pc |
f6b0fa02 RK |
53 | ldr pc, [r10, #CACHE_FLUSH_KERN_ALL] |
54 | #else | |
3799bbe5 | 55 | bl __cpuc_flush_kern_all |
f6b0fa02 | 56 | #endif |
29cb3cd2 | 57 | adr lr, BSYM(cpu_suspend_abort) |
3799bbe5 | 58 | ldmfd sp!, {r0, pc} @ call suspend fn |
2c74a0ce | 59 | ENDPROC(__cpu_suspend) |
f6b0fa02 RK |
60 | .ltorg |
61 | ||
29cb3cd2 RK |
62 | cpu_suspend_abort: |
63 | ldmia sp!, {r1 - r3} @ pop v:p, virt SP, phys resume fn | |
f5fa68d9 RK |
64 | teq r0, #0 |
65 | moveq r0, #1 @ force non-zero value | |
29cb3cd2 RK |
66 | mov sp, r2 |
67 | ldmfd sp!, {r4 - r11, pc} | |
68 | ENDPROC(cpu_suspend_abort) | |
69 | ||
f6b0fa02 RK |
70 | /* |
71 | * r0 = control register value | |
72 | * r1 = v:p offset (preserved by cpu_do_resume) | |
73 | * r2 = phys page table base | |
74 | * r3 = L1 section flags | |
75 | */ | |
76 | ENTRY(cpu_resume_mmu) | |
77 | adr r4, cpu_resume_turn_mmu_on | |
78 | mov r4, r4, lsr #20 | |
79 | orr r3, r3, r4, lsl #20 | |
80 | ldr r5, [r2, r4, lsl #2] @ save old mapping | |
81 | str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code | |
82 | sub r2, r2, r1 | |
83 | ldr r3, =cpu_resume_after_mmu | |
84 | bic r1, r0, #CR_C @ ensure D-cache is disabled | |
85 | b cpu_resume_turn_mmu_on | |
86 | ENDPROC(cpu_resume_mmu) | |
87 | .ltorg | |
88 | .align 5 | |
89 | cpu_resume_turn_mmu_on: | |
90 | mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc | |
91 | mrc p15, 0, r1, c0, c0, 0 @ read id reg | |
92 | mov r1, r1 | |
93 | mov r1, r1 | |
94 | mov pc, r3 @ jump to virtual address | |
95 | ENDPROC(cpu_resume_turn_mmu_on) | |
96 | cpu_resume_after_mmu: | |
97 | str r5, [r2, r4, lsl #2] @ restore old mapping | |
98 | mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache | |
14cd8fd5 | 99 | bl cpu_init @ restore the und/abt/irq banked regs |
29cb3cd2 | 100 | mov r0, #0 @ return zero on success |
5fa94c81 | 101 | ldmfd sp!, {r4 - r11, pc} |
f6b0fa02 RK |
102 | ENDPROC(cpu_resume_after_mmu) |
103 | ||
104 | /* | |
105 | * Note: Yes, part of the following code is located into the .data section. | |
106 | * This is to allow sleep_save_sp to be accessed with a relative load | |
107 | * while we can't rely on any MMU translation. We could have put | |
108 | * sleep_save_sp in the .text section as well, but some setups might | |
109 | * insist on it to be truly read-only. | |
110 | */ | |
111 | .data | |
112 | .align | |
113 | ENTRY(cpu_resume) | |
941aefac RK |
114 | #ifdef CONFIG_SMP |
115 | adr r0, sleep_save_sp | |
116 | ALT_SMP(mrc p15, 0, r1, c0, c0, 5) | |
117 | ALT_UP(mov r1, #0) | |
118 | and r1, r1, #15 | |
119 | ldr r0, [r0, r1, lsl #2] @ stack phys addr | |
120 | #else | |
f6b0fa02 | 121 | ldr r0, sleep_save_sp @ stack phys addr |
941aefac | 122 | #endif |
fb4fe87d | 123 | setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off |
2fefbcd5 RK |
124 | @ load v:p, stack, resume fn |
125 | ARM( ldmia r0!, {r1, sp, pc} ) | |
126 | THUMB( ldmia r0!, {r1, r2, r3} ) | |
fb4fe87d | 127 | THUMB( mov sp, r2 ) |
2fefbcd5 | 128 | THUMB( bx r3 ) |
f6b0fa02 RK |
129 | ENDPROC(cpu_resume) |
130 | ||
131 | sleep_save_sp: | |
941aefac RK |
132 | .rept CONFIG_NR_CPUS |
133 | .long 0 @ preserve stack phys ptr here | |
134 | .endr |