Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/smp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
c97d4869 | 10 | #include <linux/module.h> |
1da177e4 LT |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/cache.h> | |
17 | #include <linux/profile.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/mm.h> | |
4e950f6f | 20 | #include <linux/err.h> |
1da177e4 | 21 | #include <linux/cpu.h> |
1da177e4 | 22 | #include <linux/seq_file.h> |
c97d4869 | 23 | #include <linux/irq.h> |
bc28248e RK |
24 | #include <linux/percpu.h> |
25 | #include <linux/clockchips.h> | |
3c030bea | 26 | #include <linux/completion.h> |
ec971ea5 | 27 | #include <linux/cpufreq.h> |
bf18525f | 28 | #include <linux/irq_work.h> |
1da177e4 | 29 | |
60063497 | 30 | #include <linux/atomic.h> |
abcee5fb | 31 | #include <asm/smp.h> |
1da177e4 LT |
32 | #include <asm/cacheflush.h> |
33 | #include <asm/cpu.h> | |
42578c82 | 34 | #include <asm/cputype.h> |
5a567d78 | 35 | #include <asm/exception.h> |
8903826d | 36 | #include <asm/idmap.h> |
c9018aab | 37 | #include <asm/topology.h> |
e65f38ed RK |
38 | #include <asm/mmu_context.h> |
39 | #include <asm/pgtable.h> | |
40 | #include <asm/pgalloc.h> | |
1da177e4 | 41 | #include <asm/processor.h> |
37b05b63 | 42 | #include <asm/sections.h> |
1da177e4 LT |
43 | #include <asm/tlbflush.h> |
44 | #include <asm/ptrace.h> | |
d6257288 | 45 | #include <asm/smp_plat.h> |
4588c34d | 46 | #include <asm/virt.h> |
abcee5fb | 47 | #include <asm/mach/arch.h> |
eb08375e | 48 | #include <asm/mpu.h> |
1da177e4 | 49 | |
365ec7b1 NP |
50 | #define CREATE_TRACE_POINTS |
51 | #include <trace/events/ipi.h> | |
52 | ||
e65f38ed RK |
53 | /* |
54 | * as from 2.5, kernels no longer have an init_tasks structure | |
55 | * so we need some other way of telling a new secondary core | |
56 | * where to place its SVC stack | |
57 | */ | |
58 | struct secondary_data secondary_data; | |
59 | ||
28e8e29c MZ |
60 | /* |
61 | * control for which core is the next to come out of the secondary | |
62 | * boot "holding pen" | |
63 | */ | |
8bd26e3a | 64 | volatile int pen_release = -1; |
28e8e29c | 65 | |
1da177e4 | 66 | enum ipi_msg_type { |
559a5939 SB |
67 | IPI_WAKEUP, |
68 | IPI_TIMER, | |
1da177e4 LT |
69 | IPI_RESCHEDULE, |
70 | IPI_CALL_FUNC, | |
f6dd9fa5 | 71 | IPI_CALL_FUNC_SINGLE, |
1da177e4 | 72 | IPI_CPU_STOP, |
bf18525f | 73 | IPI_IRQ_WORK, |
5135d875 | 74 | IPI_COMPLETION, |
1da177e4 LT |
75 | }; |
76 | ||
149c2415 RK |
77 | static DECLARE_COMPLETION(cpu_running); |
78 | ||
abcee5fb MZ |
79 | static struct smp_operations smp_ops; |
80 | ||
81 | void __init smp_set_ops(struct smp_operations *ops) | |
82 | { | |
83 | if (ops) | |
84 | smp_ops = *ops; | |
85 | }; | |
86 | ||
4756dcbf CC |
87 | static unsigned long get_arch_pgd(pgd_t *pgd) |
88 | { | |
4dc9a817 | 89 | phys_addr_t pgdir = virt_to_idmap(pgd); |
4756dcbf CC |
90 | BUG_ON(pgdir & ARCH_PGD_MASK); |
91 | return pgdir >> ARCH_PGD_SHIFT; | |
92 | } | |
93 | ||
8bd26e3a | 94 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
1da177e4 | 95 | { |
1da177e4 LT |
96 | int ret; |
97 | ||
084bb5bc GU |
98 | if (!smp_ops.smp_boot_secondary) |
99 | return -ENOSYS; | |
100 | ||
e65f38ed RK |
101 | /* |
102 | * We need to tell the secondary core where to find | |
103 | * its stack and the page tables. | |
104 | */ | |
32d39a93 | 105 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; |
eb08375e JA |
106 | #ifdef CONFIG_ARM_MPU |
107 | secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr; | |
108 | #endif | |
109 | ||
c4a1f032 | 110 | #ifdef CONFIG_MMU |
4756dcbf CC |
111 | secondary_data.pgdir = get_arch_pgd(idmap_pgd); |
112 | secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir); | |
c4a1f032 | 113 | #endif |
efcfc46e | 114 | sync_cache_w(&secondary_data); |
e65f38ed | 115 | |
1da177e4 LT |
116 | /* |
117 | * Now bring the CPU into our world. | |
118 | */ | |
084bb5bc | 119 | ret = smp_ops.smp_boot_secondary(cpu, idle); |
e65f38ed | 120 | if (ret == 0) { |
e65f38ed RK |
121 | /* |
122 | * CPU was successfully started, wait for it | |
123 | * to come online or time out. | |
124 | */ | |
149c2415 RK |
125 | wait_for_completion_timeout(&cpu_running, |
126 | msecs_to_jiffies(1000)); | |
e65f38ed | 127 | |
58613cd1 RK |
128 | if (!cpu_online(cpu)) { |
129 | pr_crit("CPU%u: failed to come online\n", cpu); | |
e65f38ed | 130 | ret = -EIO; |
58613cd1 RK |
131 | } |
132 | } else { | |
133 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
e65f38ed RK |
134 | } |
135 | ||
e65f38ed | 136 | |
eb08375e | 137 | memset(&secondary_data, 0, sizeof(secondary_data)); |
1da177e4 LT |
138 | return ret; |
139 | } | |
140 | ||
abcee5fb | 141 | /* platform specific SMP operations */ |
ac6c7998 | 142 | void __init smp_init_cpus(void) |
abcee5fb MZ |
143 | { |
144 | if (smp_ops.smp_init_cpus) | |
145 | smp_ops.smp_init_cpus(); | |
146 | } | |
147 | ||
2103f6cb SW |
148 | int platform_can_cpu_hotplug(void) |
149 | { | |
150 | #ifdef CONFIG_HOTPLUG_CPU | |
151 | if (smp_ops.cpu_kill) | |
152 | return 1; | |
153 | #endif | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
a054a811 | 158 | #ifdef CONFIG_HOTPLUG_CPU |
ac6c7998 | 159 | static int platform_cpu_kill(unsigned int cpu) |
abcee5fb MZ |
160 | { |
161 | if (smp_ops.cpu_kill) | |
162 | return smp_ops.cpu_kill(cpu); | |
163 | return 1; | |
164 | } | |
165 | ||
ac6c7998 | 166 | static int platform_cpu_disable(unsigned int cpu) |
abcee5fb MZ |
167 | { |
168 | if (smp_ops.cpu_disable) | |
169 | return smp_ops.cpu_disable(cpu); | |
170 | ||
171 | /* | |
172 | * By default, allow disabling all CPUs except the first one, | |
173 | * since this is special on a lot of platforms, e.g. because | |
174 | * of clock tick interrupts. | |
175 | */ | |
176 | return cpu == 0 ? -EPERM : 0; | |
177 | } | |
a054a811 RK |
178 | /* |
179 | * __cpu_disable runs on the processor to be shutdown. | |
180 | */ | |
8bd26e3a | 181 | int __cpu_disable(void) |
a054a811 RK |
182 | { |
183 | unsigned int cpu = smp_processor_id(); | |
a054a811 RK |
184 | int ret; |
185 | ||
8e2a43f5 | 186 | ret = platform_cpu_disable(cpu); |
a054a811 RK |
187 | if (ret) |
188 | return ret; | |
189 | ||
190 | /* | |
191 | * Take this CPU offline. Once we clear this, we can't return, | |
192 | * and we must not schedule until we're ready to give up the cpu. | |
193 | */ | |
e03cdade | 194 | set_cpu_online(cpu, false); |
a054a811 RK |
195 | |
196 | /* | |
197 | * OK - migrate IRQs away from this CPU | |
198 | */ | |
199 | migrate_irqs(); | |
200 | ||
201 | /* | |
202 | * Flush user cache and TLB mappings, and then remove this CPU | |
203 | * from the vm mask set of all processes. | |
e6b866e9 LP |
204 | * |
205 | * Caches are flushed to the Level of Unification Inner Shareable | |
206 | * to write-back dirty lines to unified caches shared by all CPUs. | |
a054a811 | 207 | */ |
e6b866e9 | 208 | flush_cache_louis(); |
a054a811 RK |
209 | local_flush_tlb_all(); |
210 | ||
3eaa73bd | 211 | clear_tasks_mm_cpumask(cpu); |
a054a811 RK |
212 | |
213 | return 0; | |
214 | } | |
215 | ||
3c030bea RK |
216 | static DECLARE_COMPLETION(cpu_died); |
217 | ||
a054a811 RK |
218 | /* |
219 | * called on the thread which is asking for a CPU to be shutdown - | |
220 | * waits until shutdown has completed, or it is timed out. | |
221 | */ | |
8bd26e3a | 222 | void __cpu_die(unsigned int cpu) |
a054a811 | 223 | { |
3c030bea RK |
224 | if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { |
225 | pr_err("CPU%u: cpu didn't die\n", cpu); | |
226 | return; | |
227 | } | |
228 | printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); | |
229 | ||
51acdfd1 RK |
230 | /* |
231 | * platform_cpu_kill() is generally expected to do the powering off | |
232 | * and/or cutting of clocks to the dying CPU. Optionally, this may | |
233 | * be done by the CPU which is dying in preference to supporting | |
234 | * this call, but that means there is _no_ synchronisation between | |
235 | * the requesting CPU and the dying CPU actually losing power. | |
236 | */ | |
a054a811 RK |
237 | if (!platform_cpu_kill(cpu)) |
238 | printk("CPU%u: unable to kill\n", cpu); | |
239 | } | |
240 | ||
241 | /* | |
242 | * Called from the idle thread for the CPU which has been shutdown. | |
243 | * | |
244 | * Note that we disable IRQs here, but do not re-enable them | |
245 | * before returning to the caller. This is also the behaviour | |
246 | * of the other hotplug-cpu capable cores, so presumably coming | |
247 | * out of idle fixes this. | |
248 | */ | |
90140c30 | 249 | void __ref cpu_die(void) |
a054a811 RK |
250 | { |
251 | unsigned int cpu = smp_processor_id(); | |
252 | ||
a054a811 RK |
253 | idle_task_exit(); |
254 | ||
f36d3401 | 255 | local_irq_disable(); |
f36d3401 | 256 | |
51acdfd1 RK |
257 | /* |
258 | * Flush the data out of the L1 cache for this CPU. This must be | |
259 | * before the completion to ensure that data is safely written out | |
260 | * before platform_cpu_kill() gets called - which may disable | |
261 | * *this* CPU and power down its cache. | |
262 | */ | |
263 | flush_cache_louis(); | |
264 | ||
265 | /* | |
266 | * Tell __cpu_die() that this CPU is now safe to dispose of. Once | |
267 | * this returns, power and/or clocks can be removed at any point | |
268 | * from this CPU and its cache by platform_cpu_kill(). | |
269 | */ | |
aa033810 | 270 | complete(&cpu_died); |
3c030bea | 271 | |
a054a811 | 272 | /* |
51acdfd1 RK |
273 | * Ensure that the cache lines associated with that completion are |
274 | * written out. This covers the case where _this_ CPU is doing the | |
275 | * powering down, to ensure that the completion is visible to the | |
276 | * CPU waiting for this one. | |
277 | */ | |
278 | flush_cache_louis(); | |
279 | ||
280 | /* | |
281 | * The actual CPU shutdown procedure is at least platform (if not | |
282 | * CPU) specific. This may remove power, or it may simply spin. | |
283 | * | |
284 | * Platforms are generally expected *NOT* to return from this call, | |
285 | * although there are some which do because they have no way to | |
286 | * power down the CPU. These platforms are the _only_ reason we | |
287 | * have a return path which uses the fragment of assembly below. | |
288 | * | |
289 | * The return path should not be used for platforms which can | |
290 | * power off the CPU. | |
a054a811 | 291 | */ |
0a301110 RK |
292 | if (smp_ops.cpu_die) |
293 | smp_ops.cpu_die(cpu); | |
a054a811 | 294 | |
668bc386 RK |
295 | pr_warn("CPU%u: smp_ops.cpu_die() returned, trying to resuscitate\n", |
296 | cpu); | |
297 | ||
a054a811 RK |
298 | /* |
299 | * Do not return to the idle loop - jump back to the secondary | |
300 | * cpu initialisation. There's some initialisation which needs | |
301 | * to be repeated to undo the effects of taking the CPU offline. | |
302 | */ | |
303 | __asm__("mov sp, %0\n" | |
faabfa08 | 304 | " mov fp, #0\n" |
a054a811 RK |
305 | " b secondary_start_kernel" |
306 | : | |
32d39a93 | 307 | : "r" (task_stack_page(current) + THREAD_SIZE - 8)); |
a054a811 RK |
308 | } |
309 | #endif /* CONFIG_HOTPLUG_CPU */ | |
310 | ||
05c74a6c RK |
311 | /* |
312 | * Called by both boot and secondaries to move global data into | |
313 | * per-processor storage. | |
314 | */ | |
8bd26e3a | 315 | static void smp_store_cpu_info(unsigned int cpuid) |
05c74a6c RK |
316 | { |
317 | struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); | |
318 | ||
319 | cpu_info->loops_per_jiffy = loops_per_jiffy; | |
e8d432c9 | 320 | cpu_info->cpuid = read_cpuid_id(); |
c9018aab VG |
321 | |
322 | store_cpu_topology(cpuid); | |
05c74a6c RK |
323 | } |
324 | ||
e65f38ed RK |
325 | /* |
326 | * This is the secondary CPU boot entry. We're using this CPUs | |
327 | * idle thread stack, but a set of temporary page tables. | |
328 | */ | |
8bd26e3a | 329 | asmlinkage void secondary_start_kernel(void) |
e65f38ed RK |
330 | { |
331 | struct mm_struct *mm = &init_mm; | |
5f40b909 WD |
332 | unsigned int cpu; |
333 | ||
334 | /* | |
335 | * The identity mapping is uncached (strongly ordered), so | |
336 | * switch away from it before attempting any exclusive accesses. | |
337 | */ | |
338 | cpu_switch_mm(mm->pgd, mm); | |
89c7e4b8 | 339 | local_flush_bp_all(); |
5f40b909 WD |
340 | enter_lazy_tlb(mm, current); |
341 | local_flush_tlb_all(); | |
e65f38ed | 342 | |
e65f38ed RK |
343 | /* |
344 | * All kernel threads share the same mm context; grab a | |
345 | * reference and switch to it. | |
346 | */ | |
5f40b909 | 347 | cpu = smp_processor_id(); |
e65f38ed RK |
348 | atomic_inc(&mm->mm_count); |
349 | current->active_mm = mm; | |
56f8ba83 | 350 | cpumask_set_cpu(cpu, mm_cpumask(mm)); |
e65f38ed | 351 | |
14318efb RH |
352 | cpu_init(); |
353 | ||
fde165b2 CC |
354 | printk("CPU%u: Booted secondary processor\n", cpu); |
355 | ||
5bfb5d69 | 356 | preempt_disable(); |
2c0136db | 357 | trace_hardirqs_off(); |
e65f38ed RK |
358 | |
359 | /* | |
360 | * Give the platform a chance to do its own initialisation. | |
361 | */ | |
0a301110 RK |
362 | if (smp_ops.smp_secondary_init) |
363 | smp_ops.smp_secondary_init(cpu); | |
e65f38ed | 364 | |
e545a614 | 365 | notify_cpu_starting(cpu); |
a8655e83 | 366 | |
e65f38ed RK |
367 | calibrate_delay(); |
368 | ||
369 | smp_store_cpu_info(cpu); | |
370 | ||
371 | /* | |
573619d1 RK |
372 | * OK, now it's safe to let the boot CPU continue. Wait for |
373 | * the CPU migration code to notice that the CPU is online | |
149c2415 | 374 | * before we continue - which happens after __cpu_up returns. |
e65f38ed | 375 | */ |
e03cdade | 376 | set_cpu_online(cpu, true); |
149c2415 | 377 | complete(&cpu_running); |
eb047454 | 378 | |
eb047454 TG |
379 | local_irq_enable(); |
380 | local_fiq_enable(); | |
381 | ||
e65f38ed RK |
382 | /* |
383 | * OK, it's off to the idle thread for us | |
384 | */ | |
f7b861b7 | 385 | cpu_startup_entry(CPUHP_ONLINE); |
e65f38ed RK |
386 | } |
387 | ||
1da177e4 LT |
388 | void __init smp_cpus_done(unsigned int max_cpus) |
389 | { | |
9fc2105a WD |
390 | printk(KERN_INFO "SMP: Total of %d processors activated.\n", |
391 | num_online_cpus()); | |
4588c34d DM |
392 | |
393 | hyp_mode_check(); | |
1da177e4 LT |
394 | } |
395 | ||
396 | void __init smp_prepare_boot_cpu(void) | |
397 | { | |
14318efb | 398 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
1da177e4 LT |
399 | } |
400 | ||
05c74a6c | 401 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1da177e4 | 402 | { |
05c74a6c | 403 | unsigned int ncores = num_possible_cpus(); |
1da177e4 | 404 | |
c9018aab VG |
405 | init_cpu_topology(); |
406 | ||
05c74a6c | 407 | smp_store_cpu_info(smp_processor_id()); |
1da177e4 LT |
408 | |
409 | /* | |
05c74a6c | 410 | * are we trying to boot more cores than exist? |
1da177e4 | 411 | */ |
05c74a6c RK |
412 | if (max_cpus > ncores) |
413 | max_cpus = ncores; | |
7fa22bd5 | 414 | if (ncores > 1 && max_cpus) { |
7fa22bd5 SB |
415 | /* |
416 | * Initialise the present map, which describes the set of CPUs | |
417 | * actually populated at the present time. A platform should | |
0a301110 RK |
418 | * re-initialize the map in the platforms smp_prepare_cpus() |
419 | * if present != possible (e.g. physical hotplug). | |
7fa22bd5 | 420 | */ |
0b5f9c00 | 421 | init_cpu_present(cpu_possible_mask); |
7fa22bd5 | 422 | |
05c74a6c RK |
423 | /* |
424 | * Initialise the SCU if there are more than one CPU | |
425 | * and let them know where to start. | |
426 | */ | |
0a301110 RK |
427 | if (smp_ops.smp_prepare_cpus) |
428 | smp_ops.smp_prepare_cpus(max_cpus); | |
05c74a6c | 429 | } |
1da177e4 LT |
430 | } |
431 | ||
365ec7b1 | 432 | static void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
0f7b332f RK |
433 | |
434 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
435 | { | |
365ec7b1 NP |
436 | if (!__smp_cross_call) |
437 | __smp_cross_call = fn; | |
3e459990 | 438 | } |
3e459990 | 439 | |
365ec7b1 | 440 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
559a5939 SB |
441 | #define S(x,s) [x] = s |
442 | S(IPI_WAKEUP, "CPU wakeup interrupts"), | |
4a88abd7 RK |
443 | S(IPI_TIMER, "Timer broadcast interrupts"), |
444 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), | |
445 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
446 | S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"), | |
447 | S(IPI_CPU_STOP, "CPU stop interrupts"), | |
bf18525f | 448 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5135d875 | 449 | S(IPI_COMPLETION, "completion interrupts"), |
4a88abd7 RK |
450 | }; |
451 | ||
365ec7b1 NP |
452 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
453 | { | |
454 | trace_ipi_raise(target, ipi_types[ipinr]); | |
455 | __smp_cross_call(target, ipinr); | |
456 | } | |
457 | ||
f13cd417 | 458 | void show_ipi_list(struct seq_file *p, int prec) |
1da177e4 | 459 | { |
4a88abd7 | 460 | unsigned int cpu, i; |
1da177e4 | 461 | |
4a88abd7 RK |
462 | for (i = 0; i < NR_IPI; i++) { |
463 | seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); | |
1da177e4 | 464 | |
026b7c6b | 465 | for_each_online_cpu(cpu) |
4a88abd7 RK |
466 | seq_printf(p, "%10u ", |
467 | __get_irq_stat(cpu, ipi_irqs[i])); | |
1da177e4 | 468 | |
4a88abd7 RK |
469 | seq_printf(p, " %s\n", ipi_types[i]); |
470 | } | |
1da177e4 LT |
471 | } |
472 | ||
b54992fe | 473 | u64 smp_irq_stat_cpu(unsigned int cpu) |
37ee16ae | 474 | { |
b54992fe RK |
475 | u64 sum = 0; |
476 | int i; | |
37ee16ae | 477 | |
b54992fe RK |
478 | for (i = 0; i < NR_IPI; i++) |
479 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
37ee16ae | 480 | |
b54992fe | 481 | return sum; |
37ee16ae RK |
482 | } |
483 | ||
365ec7b1 NP |
484 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
485 | { | |
486 | smp_cross_call(mask, IPI_CALL_FUNC); | |
487 | } | |
488 | ||
489 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
490 | { | |
491 | smp_cross_call(mask, IPI_WAKEUP); | |
492 | } | |
493 | ||
494 | void arch_send_call_function_single_ipi(int cpu) | |
495 | { | |
496 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); | |
497 | } | |
498 | ||
499 | #ifdef CONFIG_IRQ_WORK | |
500 | void arch_irq_work_raise(void) | |
501 | { | |
09f6edd4 | 502 | if (arch_irq_work_has_interrupt()) |
365ec7b1 NP |
503 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); |
504 | } | |
505 | #endif | |
506 | ||
bc28248e | 507 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
3d06770e | 508 | void tick_broadcast(const struct cpumask *mask) |
bc28248e | 509 | { |
e3fbb087 | 510 | smp_cross_call(mask, IPI_TIMER); |
bc28248e | 511 | } |
5388a6b2 | 512 | #endif |
bc28248e | 513 | |
bd31b859 | 514 | static DEFINE_RAW_SPINLOCK(stop_lock); |
1da177e4 LT |
515 | |
516 | /* | |
517 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
518 | */ | |
519 | static void ipi_cpu_stop(unsigned int cpu) | |
520 | { | |
3d3f78d7 RK |
521 | if (system_state == SYSTEM_BOOTING || |
522 | system_state == SYSTEM_RUNNING) { | |
bd31b859 | 523 | raw_spin_lock(&stop_lock); |
3d3f78d7 RK |
524 | printk(KERN_CRIT "CPU%u: stopping\n", cpu); |
525 | dump_stack(); | |
bd31b859 | 526 | raw_spin_unlock(&stop_lock); |
3d3f78d7 | 527 | } |
1da177e4 | 528 | |
e03cdade | 529 | set_cpu_online(cpu, false); |
1da177e4 LT |
530 | |
531 | local_fiq_disable(); | |
532 | local_irq_disable(); | |
533 | ||
534 | while (1) | |
535 | cpu_relax(); | |
536 | } | |
537 | ||
5135d875 NP |
538 | static DEFINE_PER_CPU(struct completion *, cpu_completion); |
539 | ||
540 | int register_ipi_completion(struct completion *completion, int cpu) | |
541 | { | |
542 | per_cpu(cpu_completion, cpu) = completion; | |
543 | return IPI_COMPLETION; | |
544 | } | |
545 | ||
546 | static void ipi_complete(unsigned int cpu) | |
547 | { | |
548 | complete(per_cpu(cpu_completion, cpu)); | |
549 | } | |
550 | ||
1da177e4 LT |
551 | /* |
552 | * Main handler for inter-processor interrupts | |
1da177e4 | 553 | */ |
4073723a | 554 | asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) |
0b5a1b95 SG |
555 | { |
556 | handle_IPI(ipinr, regs); | |
557 | } | |
558 | ||
559 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
1da177e4 LT |
560 | { |
561 | unsigned int cpu = smp_processor_id(); | |
c97d4869 | 562 | struct pt_regs *old_regs = set_irq_regs(regs); |
1da177e4 | 563 | |
365ec7b1 NP |
564 | if ((unsigned)ipinr < NR_IPI) { |
565 | trace_ipi_entry(ipi_types[ipinr]); | |
559a5939 | 566 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
365ec7b1 | 567 | } |
1da177e4 | 568 | |
24480d98 | 569 | switch (ipinr) { |
559a5939 SB |
570 | case IPI_WAKEUP: |
571 | break; | |
572 | ||
e2c50119 | 573 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
24480d98 | 574 | case IPI_TIMER: |
7deabca0 | 575 | irq_enter(); |
e2c50119 | 576 | tick_receive_broadcast(); |
7deabca0 | 577 | irq_exit(); |
24480d98 | 578 | break; |
e2c50119 | 579 | #endif |
1da177e4 | 580 | |
24480d98 | 581 | case IPI_RESCHEDULE: |
184748cc | 582 | scheduler_ipi(); |
24480d98 | 583 | break; |
1da177e4 | 584 | |
24480d98 | 585 | case IPI_CALL_FUNC: |
7deabca0 | 586 | irq_enter(); |
24480d98 | 587 | generic_smp_call_function_interrupt(); |
7deabca0 | 588 | irq_exit(); |
24480d98 | 589 | break; |
f6dd9fa5 | 590 | |
24480d98 | 591 | case IPI_CALL_FUNC_SINGLE: |
7deabca0 | 592 | irq_enter(); |
24480d98 | 593 | generic_smp_call_function_single_interrupt(); |
7deabca0 | 594 | irq_exit(); |
24480d98 | 595 | break; |
1da177e4 | 596 | |
24480d98 | 597 | case IPI_CPU_STOP: |
7deabca0 | 598 | irq_enter(); |
24480d98 | 599 | ipi_cpu_stop(cpu); |
7deabca0 | 600 | irq_exit(); |
24480d98 | 601 | break; |
1da177e4 | 602 | |
bf18525f SB |
603 | #ifdef CONFIG_IRQ_WORK |
604 | case IPI_IRQ_WORK: | |
605 | irq_enter(); | |
606 | irq_work_run(); | |
607 | irq_exit(); | |
608 | break; | |
609 | #endif | |
610 | ||
5135d875 NP |
611 | case IPI_COMPLETION: |
612 | irq_enter(); | |
613 | ipi_complete(cpu); | |
614 | irq_exit(); | |
615 | break; | |
616 | ||
24480d98 RK |
617 | default: |
618 | printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n", | |
619 | cpu, ipinr); | |
620 | break; | |
1da177e4 | 621 | } |
365ec7b1 NP |
622 | |
623 | if ((unsigned)ipinr < NR_IPI) | |
624 | trace_ipi_exit(ipi_types[ipinr]); | |
c97d4869 | 625 | set_irq_regs(old_regs); |
1da177e4 LT |
626 | } |
627 | ||
628 | void smp_send_reschedule(int cpu) | |
629 | { | |
e3fbb087 | 630 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); |
1da177e4 LT |
631 | } |
632 | ||
1da177e4 LT |
633 | void smp_send_stop(void) |
634 | { | |
28e18293 | 635 | unsigned long timeout; |
6fa99b7f | 636 | struct cpumask mask; |
1da177e4 | 637 | |
6fa99b7f WD |
638 | cpumask_copy(&mask, cpu_online_mask); |
639 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
c5dff4ff JMC |
640 | if (!cpumask_empty(&mask)) |
641 | smp_cross_call(&mask, IPI_CPU_STOP); | |
4b0ef3b1 | 642 | |
28e18293 RK |
643 | /* Wait up to one second for other CPUs to stop */ |
644 | timeout = USEC_PER_SEC; | |
645 | while (num_online_cpus() > 1 && timeout--) | |
646 | udelay(1); | |
4b0ef3b1 | 647 | |
28e18293 | 648 | if (num_online_cpus() > 1) |
8b521cb2 | 649 | pr_warn("SMP: failed to stop secondary CPUs\n"); |
4b0ef3b1 RK |
650 | } |
651 | ||
4b0ef3b1 | 652 | /* |
1da177e4 | 653 | * not supported here |
4b0ef3b1 | 654 | */ |
5048bcba | 655 | int setup_profiling_timer(unsigned int multiplier) |
4b0ef3b1 | 656 | { |
1da177e4 | 657 | return -EINVAL; |
4b0ef3b1 | 658 | } |
ec971ea5 RZ |
659 | |
660 | #ifdef CONFIG_CPU_FREQ | |
661 | ||
662 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref); | |
663 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq); | |
664 | static unsigned long global_l_p_j_ref; | |
665 | static unsigned long global_l_p_j_ref_freq; | |
666 | ||
667 | static int cpufreq_callback(struct notifier_block *nb, | |
668 | unsigned long val, void *data) | |
669 | { | |
670 | struct cpufreq_freqs *freq = data; | |
671 | int cpu = freq->cpu; | |
672 | ||
673 | if (freq->flags & CPUFREQ_CONST_LOOPS) | |
674 | return NOTIFY_OK; | |
675 | ||
676 | if (!per_cpu(l_p_j_ref, cpu)) { | |
677 | per_cpu(l_p_j_ref, cpu) = | |
678 | per_cpu(cpu_data, cpu).loops_per_jiffy; | |
679 | per_cpu(l_p_j_ref_freq, cpu) = freq->old; | |
680 | if (!global_l_p_j_ref) { | |
681 | global_l_p_j_ref = loops_per_jiffy; | |
682 | global_l_p_j_ref_freq = freq->old; | |
683 | } | |
684 | } | |
685 | ||
686 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 687 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
ec971ea5 RZ |
688 | loops_per_jiffy = cpufreq_scale(global_l_p_j_ref, |
689 | global_l_p_j_ref_freq, | |
690 | freq->new); | |
691 | per_cpu(cpu_data, cpu).loops_per_jiffy = | |
692 | cpufreq_scale(per_cpu(l_p_j_ref, cpu), | |
693 | per_cpu(l_p_j_ref_freq, cpu), | |
694 | freq->new); | |
695 | } | |
696 | return NOTIFY_OK; | |
697 | } | |
698 | ||
699 | static struct notifier_block cpufreq_notifier = { | |
700 | .notifier_call = cpufreq_callback, | |
701 | }; | |
702 | ||
703 | static int __init register_cpufreq_notifier(void) | |
704 | { | |
705 | return cpufreq_register_notifier(&cpufreq_notifier, | |
706 | CPUFREQ_TRANSITION_NOTIFIER); | |
707 | } | |
708 | core_initcall(register_cpufreq_notifier); | |
709 | ||
710 | #endif |