Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/smp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
c97d4869 | 10 | #include <linux/module.h> |
1da177e4 LT |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/cache.h> | |
17 | #include <linux/profile.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/mm.h> | |
4e950f6f | 20 | #include <linux/err.h> |
1da177e4 | 21 | #include <linux/cpu.h> |
1da177e4 | 22 | #include <linux/seq_file.h> |
c97d4869 | 23 | #include <linux/irq.h> |
bc28248e RK |
24 | #include <linux/percpu.h> |
25 | #include <linux/clockchips.h> | |
3c030bea | 26 | #include <linux/completion.h> |
ec971ea5 | 27 | #include <linux/cpufreq.h> |
bf18525f | 28 | #include <linux/irq_work.h> |
1da177e4 | 29 | |
60063497 | 30 | #include <linux/atomic.h> |
abcee5fb | 31 | #include <asm/smp.h> |
1da177e4 LT |
32 | #include <asm/cacheflush.h> |
33 | #include <asm/cpu.h> | |
42578c82 | 34 | #include <asm/cputype.h> |
5a567d78 | 35 | #include <asm/exception.h> |
8903826d | 36 | #include <asm/idmap.h> |
c9018aab | 37 | #include <asm/topology.h> |
e65f38ed RK |
38 | #include <asm/mmu_context.h> |
39 | #include <asm/pgtable.h> | |
40 | #include <asm/pgalloc.h> | |
1da177e4 | 41 | #include <asm/processor.h> |
37b05b63 | 42 | #include <asm/sections.h> |
1da177e4 LT |
43 | #include <asm/tlbflush.h> |
44 | #include <asm/ptrace.h> | |
d6257288 | 45 | #include <asm/smp_plat.h> |
4588c34d | 46 | #include <asm/virt.h> |
abcee5fb | 47 | #include <asm/mach/arch.h> |
eb08375e | 48 | #include <asm/mpu.h> |
1da177e4 | 49 | |
e65f38ed RK |
50 | /* |
51 | * as from 2.5, kernels no longer have an init_tasks structure | |
52 | * so we need some other way of telling a new secondary core | |
53 | * where to place its SVC stack | |
54 | */ | |
55 | struct secondary_data secondary_data; | |
56 | ||
28e8e29c MZ |
57 | /* |
58 | * control for which core is the next to come out of the secondary | |
59 | * boot "holding pen" | |
60 | */ | |
8bd26e3a | 61 | volatile int pen_release = -1; |
28e8e29c | 62 | |
1da177e4 | 63 | enum ipi_msg_type { |
559a5939 SB |
64 | IPI_WAKEUP, |
65 | IPI_TIMER, | |
1da177e4 LT |
66 | IPI_RESCHEDULE, |
67 | IPI_CALL_FUNC, | |
f6dd9fa5 | 68 | IPI_CALL_FUNC_SINGLE, |
1da177e4 | 69 | IPI_CPU_STOP, |
bf18525f | 70 | IPI_IRQ_WORK, |
5135d875 | 71 | IPI_COMPLETION, |
1da177e4 LT |
72 | }; |
73 | ||
149c2415 RK |
74 | static DECLARE_COMPLETION(cpu_running); |
75 | ||
abcee5fb MZ |
76 | static struct smp_operations smp_ops; |
77 | ||
78 | void __init smp_set_ops(struct smp_operations *ops) | |
79 | { | |
80 | if (ops) | |
81 | smp_ops = *ops; | |
82 | }; | |
83 | ||
4756dcbf CC |
84 | static unsigned long get_arch_pgd(pgd_t *pgd) |
85 | { | |
4dc9a817 | 86 | phys_addr_t pgdir = virt_to_idmap(pgd); |
4756dcbf CC |
87 | BUG_ON(pgdir & ARCH_PGD_MASK); |
88 | return pgdir >> ARCH_PGD_SHIFT; | |
89 | } | |
90 | ||
8bd26e3a | 91 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
1da177e4 | 92 | { |
1da177e4 LT |
93 | int ret; |
94 | ||
e65f38ed RK |
95 | /* |
96 | * We need to tell the secondary core where to find | |
97 | * its stack and the page tables. | |
98 | */ | |
32d39a93 | 99 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; |
eb08375e JA |
100 | #ifdef CONFIG_ARM_MPU |
101 | secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr; | |
102 | #endif | |
103 | ||
c4a1f032 | 104 | #ifdef CONFIG_MMU |
4756dcbf CC |
105 | secondary_data.pgdir = get_arch_pgd(idmap_pgd); |
106 | secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir); | |
c4a1f032 | 107 | #endif |
efcfc46e | 108 | sync_cache_w(&secondary_data); |
e65f38ed | 109 | |
1da177e4 LT |
110 | /* |
111 | * Now bring the CPU into our world. | |
112 | */ | |
113 | ret = boot_secondary(cpu, idle); | |
e65f38ed | 114 | if (ret == 0) { |
e65f38ed RK |
115 | /* |
116 | * CPU was successfully started, wait for it | |
117 | * to come online or time out. | |
118 | */ | |
149c2415 RK |
119 | wait_for_completion_timeout(&cpu_running, |
120 | msecs_to_jiffies(1000)); | |
e65f38ed | 121 | |
58613cd1 RK |
122 | if (!cpu_online(cpu)) { |
123 | pr_crit("CPU%u: failed to come online\n", cpu); | |
e65f38ed | 124 | ret = -EIO; |
58613cd1 RK |
125 | } |
126 | } else { | |
127 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
e65f38ed RK |
128 | } |
129 | ||
e65f38ed | 130 | |
eb08375e | 131 | memset(&secondary_data, 0, sizeof(secondary_data)); |
1da177e4 LT |
132 | return ret; |
133 | } | |
134 | ||
abcee5fb | 135 | /* platform specific SMP operations */ |
ac6c7998 | 136 | void __init smp_init_cpus(void) |
abcee5fb MZ |
137 | { |
138 | if (smp_ops.smp_init_cpus) | |
139 | smp_ops.smp_init_cpus(); | |
140 | } | |
141 | ||
8bd26e3a | 142 | int boot_secondary(unsigned int cpu, struct task_struct *idle) |
abcee5fb MZ |
143 | { |
144 | if (smp_ops.smp_boot_secondary) | |
145 | return smp_ops.smp_boot_secondary(cpu, idle); | |
146 | return -ENOSYS; | |
147 | } | |
148 | ||
2103f6cb SW |
149 | int platform_can_cpu_hotplug(void) |
150 | { | |
151 | #ifdef CONFIG_HOTPLUG_CPU | |
152 | if (smp_ops.cpu_kill) | |
153 | return 1; | |
154 | #endif | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
a054a811 | 159 | #ifdef CONFIG_HOTPLUG_CPU |
ac6c7998 | 160 | static int platform_cpu_kill(unsigned int cpu) |
abcee5fb MZ |
161 | { |
162 | if (smp_ops.cpu_kill) | |
163 | return smp_ops.cpu_kill(cpu); | |
164 | return 1; | |
165 | } | |
166 | ||
ac6c7998 | 167 | static int platform_cpu_disable(unsigned int cpu) |
abcee5fb MZ |
168 | { |
169 | if (smp_ops.cpu_disable) | |
170 | return smp_ops.cpu_disable(cpu); | |
171 | ||
172 | /* | |
173 | * By default, allow disabling all CPUs except the first one, | |
174 | * since this is special on a lot of platforms, e.g. because | |
175 | * of clock tick interrupts. | |
176 | */ | |
177 | return cpu == 0 ? -EPERM : 0; | |
178 | } | |
a054a811 RK |
179 | /* |
180 | * __cpu_disable runs on the processor to be shutdown. | |
181 | */ | |
8bd26e3a | 182 | int __cpu_disable(void) |
a054a811 RK |
183 | { |
184 | unsigned int cpu = smp_processor_id(); | |
a054a811 RK |
185 | int ret; |
186 | ||
8e2a43f5 | 187 | ret = platform_cpu_disable(cpu); |
a054a811 RK |
188 | if (ret) |
189 | return ret; | |
190 | ||
191 | /* | |
192 | * Take this CPU offline. Once we clear this, we can't return, | |
193 | * and we must not schedule until we're ready to give up the cpu. | |
194 | */ | |
e03cdade | 195 | set_cpu_online(cpu, false); |
a054a811 RK |
196 | |
197 | /* | |
198 | * OK - migrate IRQs away from this CPU | |
199 | */ | |
200 | migrate_irqs(); | |
201 | ||
202 | /* | |
203 | * Flush user cache and TLB mappings, and then remove this CPU | |
204 | * from the vm mask set of all processes. | |
e6b866e9 LP |
205 | * |
206 | * Caches are flushed to the Level of Unification Inner Shareable | |
207 | * to write-back dirty lines to unified caches shared by all CPUs. | |
a054a811 | 208 | */ |
e6b866e9 | 209 | flush_cache_louis(); |
a054a811 RK |
210 | local_flush_tlb_all(); |
211 | ||
3eaa73bd | 212 | clear_tasks_mm_cpumask(cpu); |
a054a811 RK |
213 | |
214 | return 0; | |
215 | } | |
216 | ||
3c030bea RK |
217 | static DECLARE_COMPLETION(cpu_died); |
218 | ||
a054a811 RK |
219 | /* |
220 | * called on the thread which is asking for a CPU to be shutdown - | |
221 | * waits until shutdown has completed, or it is timed out. | |
222 | */ | |
8bd26e3a | 223 | void __cpu_die(unsigned int cpu) |
a054a811 | 224 | { |
3c030bea RK |
225 | if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { |
226 | pr_err("CPU%u: cpu didn't die\n", cpu); | |
227 | return; | |
228 | } | |
229 | printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); | |
230 | ||
51acdfd1 RK |
231 | /* |
232 | * platform_cpu_kill() is generally expected to do the powering off | |
233 | * and/or cutting of clocks to the dying CPU. Optionally, this may | |
234 | * be done by the CPU which is dying in preference to supporting | |
235 | * this call, but that means there is _no_ synchronisation between | |
236 | * the requesting CPU and the dying CPU actually losing power. | |
237 | */ | |
a054a811 RK |
238 | if (!platform_cpu_kill(cpu)) |
239 | printk("CPU%u: unable to kill\n", cpu); | |
240 | } | |
241 | ||
242 | /* | |
243 | * Called from the idle thread for the CPU which has been shutdown. | |
244 | * | |
245 | * Note that we disable IRQs here, but do not re-enable them | |
246 | * before returning to the caller. This is also the behaviour | |
247 | * of the other hotplug-cpu capable cores, so presumably coming | |
248 | * out of idle fixes this. | |
249 | */ | |
90140c30 | 250 | void __ref cpu_die(void) |
a054a811 RK |
251 | { |
252 | unsigned int cpu = smp_processor_id(); | |
253 | ||
a054a811 RK |
254 | idle_task_exit(); |
255 | ||
f36d3401 | 256 | local_irq_disable(); |
f36d3401 | 257 | |
51acdfd1 RK |
258 | /* |
259 | * Flush the data out of the L1 cache for this CPU. This must be | |
260 | * before the completion to ensure that data is safely written out | |
261 | * before platform_cpu_kill() gets called - which may disable | |
262 | * *this* CPU and power down its cache. | |
263 | */ | |
264 | flush_cache_louis(); | |
265 | ||
266 | /* | |
267 | * Tell __cpu_die() that this CPU is now safe to dispose of. Once | |
268 | * this returns, power and/or clocks can be removed at any point | |
269 | * from this CPU and its cache by platform_cpu_kill(). | |
270 | */ | |
aa033810 | 271 | complete(&cpu_died); |
3c030bea | 272 | |
a054a811 | 273 | /* |
51acdfd1 RK |
274 | * Ensure that the cache lines associated with that completion are |
275 | * written out. This covers the case where _this_ CPU is doing the | |
276 | * powering down, to ensure that the completion is visible to the | |
277 | * CPU waiting for this one. | |
278 | */ | |
279 | flush_cache_louis(); | |
280 | ||
281 | /* | |
282 | * The actual CPU shutdown procedure is at least platform (if not | |
283 | * CPU) specific. This may remove power, or it may simply spin. | |
284 | * | |
285 | * Platforms are generally expected *NOT* to return from this call, | |
286 | * although there are some which do because they have no way to | |
287 | * power down the CPU. These platforms are the _only_ reason we | |
288 | * have a return path which uses the fragment of assembly below. | |
289 | * | |
290 | * The return path should not be used for platforms which can | |
291 | * power off the CPU. | |
a054a811 | 292 | */ |
0a301110 RK |
293 | if (smp_ops.cpu_die) |
294 | smp_ops.cpu_die(cpu); | |
a054a811 | 295 | |
668bc386 RK |
296 | pr_warn("CPU%u: smp_ops.cpu_die() returned, trying to resuscitate\n", |
297 | cpu); | |
298 | ||
a054a811 RK |
299 | /* |
300 | * Do not return to the idle loop - jump back to the secondary | |
301 | * cpu initialisation. There's some initialisation which needs | |
302 | * to be repeated to undo the effects of taking the CPU offline. | |
303 | */ | |
304 | __asm__("mov sp, %0\n" | |
faabfa08 | 305 | " mov fp, #0\n" |
a054a811 RK |
306 | " b secondary_start_kernel" |
307 | : | |
32d39a93 | 308 | : "r" (task_stack_page(current) + THREAD_SIZE - 8)); |
a054a811 RK |
309 | } |
310 | #endif /* CONFIG_HOTPLUG_CPU */ | |
311 | ||
05c74a6c RK |
312 | /* |
313 | * Called by both boot and secondaries to move global data into | |
314 | * per-processor storage. | |
315 | */ | |
8bd26e3a | 316 | static void smp_store_cpu_info(unsigned int cpuid) |
05c74a6c RK |
317 | { |
318 | struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); | |
319 | ||
320 | cpu_info->loops_per_jiffy = loops_per_jiffy; | |
e8d432c9 | 321 | cpu_info->cpuid = read_cpuid_id(); |
c9018aab VG |
322 | |
323 | store_cpu_topology(cpuid); | |
05c74a6c RK |
324 | } |
325 | ||
e65f38ed RK |
326 | /* |
327 | * This is the secondary CPU boot entry. We're using this CPUs | |
328 | * idle thread stack, but a set of temporary page tables. | |
329 | */ | |
8bd26e3a | 330 | asmlinkage void secondary_start_kernel(void) |
e65f38ed RK |
331 | { |
332 | struct mm_struct *mm = &init_mm; | |
5f40b909 WD |
333 | unsigned int cpu; |
334 | ||
335 | /* | |
336 | * The identity mapping is uncached (strongly ordered), so | |
337 | * switch away from it before attempting any exclusive accesses. | |
338 | */ | |
339 | cpu_switch_mm(mm->pgd, mm); | |
89c7e4b8 | 340 | local_flush_bp_all(); |
5f40b909 WD |
341 | enter_lazy_tlb(mm, current); |
342 | local_flush_tlb_all(); | |
e65f38ed | 343 | |
e65f38ed RK |
344 | /* |
345 | * All kernel threads share the same mm context; grab a | |
346 | * reference and switch to it. | |
347 | */ | |
5f40b909 | 348 | cpu = smp_processor_id(); |
e65f38ed RK |
349 | atomic_inc(&mm->mm_count); |
350 | current->active_mm = mm; | |
56f8ba83 | 351 | cpumask_set_cpu(cpu, mm_cpumask(mm)); |
e65f38ed | 352 | |
14318efb RH |
353 | cpu_init(); |
354 | ||
fde165b2 CC |
355 | printk("CPU%u: Booted secondary processor\n", cpu); |
356 | ||
5bfb5d69 | 357 | preempt_disable(); |
2c0136db | 358 | trace_hardirqs_off(); |
e65f38ed RK |
359 | |
360 | /* | |
361 | * Give the platform a chance to do its own initialisation. | |
362 | */ | |
0a301110 RK |
363 | if (smp_ops.smp_secondary_init) |
364 | smp_ops.smp_secondary_init(cpu); | |
e65f38ed | 365 | |
e545a614 | 366 | notify_cpu_starting(cpu); |
a8655e83 | 367 | |
e65f38ed RK |
368 | calibrate_delay(); |
369 | ||
370 | smp_store_cpu_info(cpu); | |
371 | ||
372 | /* | |
573619d1 RK |
373 | * OK, now it's safe to let the boot CPU continue. Wait for |
374 | * the CPU migration code to notice that the CPU is online | |
149c2415 | 375 | * before we continue - which happens after __cpu_up returns. |
e65f38ed | 376 | */ |
e03cdade | 377 | set_cpu_online(cpu, true); |
149c2415 | 378 | complete(&cpu_running); |
eb047454 | 379 | |
eb047454 TG |
380 | local_irq_enable(); |
381 | local_fiq_enable(); | |
382 | ||
e65f38ed RK |
383 | /* |
384 | * OK, it's off to the idle thread for us | |
385 | */ | |
f7b861b7 | 386 | cpu_startup_entry(CPUHP_ONLINE); |
e65f38ed RK |
387 | } |
388 | ||
1da177e4 LT |
389 | void __init smp_cpus_done(unsigned int max_cpus) |
390 | { | |
9fc2105a WD |
391 | printk(KERN_INFO "SMP: Total of %d processors activated.\n", |
392 | num_online_cpus()); | |
4588c34d DM |
393 | |
394 | hyp_mode_check(); | |
1da177e4 LT |
395 | } |
396 | ||
397 | void __init smp_prepare_boot_cpu(void) | |
398 | { | |
14318efb | 399 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
1da177e4 LT |
400 | } |
401 | ||
05c74a6c | 402 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1da177e4 | 403 | { |
05c74a6c | 404 | unsigned int ncores = num_possible_cpus(); |
1da177e4 | 405 | |
c9018aab VG |
406 | init_cpu_topology(); |
407 | ||
05c74a6c | 408 | smp_store_cpu_info(smp_processor_id()); |
1da177e4 LT |
409 | |
410 | /* | |
05c74a6c | 411 | * are we trying to boot more cores than exist? |
1da177e4 | 412 | */ |
05c74a6c RK |
413 | if (max_cpus > ncores) |
414 | max_cpus = ncores; | |
7fa22bd5 | 415 | if (ncores > 1 && max_cpus) { |
7fa22bd5 SB |
416 | /* |
417 | * Initialise the present map, which describes the set of CPUs | |
418 | * actually populated at the present time. A platform should | |
0a301110 RK |
419 | * re-initialize the map in the platforms smp_prepare_cpus() |
420 | * if present != possible (e.g. physical hotplug). | |
7fa22bd5 | 421 | */ |
0b5f9c00 | 422 | init_cpu_present(cpu_possible_mask); |
7fa22bd5 | 423 | |
05c74a6c RK |
424 | /* |
425 | * Initialise the SCU if there are more than one CPU | |
426 | * and let them know where to start. | |
427 | */ | |
0a301110 RK |
428 | if (smp_ops.smp_prepare_cpus) |
429 | smp_ops.smp_prepare_cpus(max_cpus); | |
05c74a6c | 430 | } |
1da177e4 LT |
431 | } |
432 | ||
0f7b332f RK |
433 | static void (*smp_cross_call)(const struct cpumask *, unsigned int); |
434 | ||
435 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
436 | { | |
b1cffebf RH |
437 | if (!smp_cross_call) |
438 | smp_cross_call = fn; | |
0f7b332f RK |
439 | } |
440 | ||
82668104 | 441 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
1da177e4 | 442 | { |
e3fbb087 | 443 | smp_cross_call(mask, IPI_CALL_FUNC); |
1da177e4 LT |
444 | } |
445 | ||
b62655f4 SG |
446 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) |
447 | { | |
448 | smp_cross_call(mask, IPI_WAKEUP); | |
449 | } | |
450 | ||
f6dd9fa5 | 451 | void arch_send_call_function_single_ipi(int cpu) |
3e459990 | 452 | { |
e3fbb087 | 453 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); |
3e459990 | 454 | } |
3e459990 | 455 | |
bf18525f SB |
456 | #ifdef CONFIG_IRQ_WORK |
457 | void arch_irq_work_raise(void) | |
458 | { | |
c682e51d SB |
459 | if (is_smp()) |
460 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
bf18525f SB |
461 | } |
462 | #endif | |
463 | ||
4a88abd7 | 464 | static const char *ipi_types[NR_IPI] = { |
559a5939 SB |
465 | #define S(x,s) [x] = s |
466 | S(IPI_WAKEUP, "CPU wakeup interrupts"), | |
4a88abd7 RK |
467 | S(IPI_TIMER, "Timer broadcast interrupts"), |
468 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), | |
469 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
470 | S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"), | |
471 | S(IPI_CPU_STOP, "CPU stop interrupts"), | |
bf18525f | 472 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5135d875 | 473 | S(IPI_COMPLETION, "completion interrupts"), |
4a88abd7 RK |
474 | }; |
475 | ||
f13cd417 | 476 | void show_ipi_list(struct seq_file *p, int prec) |
1da177e4 | 477 | { |
4a88abd7 | 478 | unsigned int cpu, i; |
1da177e4 | 479 | |
4a88abd7 RK |
480 | for (i = 0; i < NR_IPI; i++) { |
481 | seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); | |
1da177e4 | 482 | |
026b7c6b | 483 | for_each_online_cpu(cpu) |
4a88abd7 RK |
484 | seq_printf(p, "%10u ", |
485 | __get_irq_stat(cpu, ipi_irqs[i])); | |
1da177e4 | 486 | |
4a88abd7 RK |
487 | seq_printf(p, " %s\n", ipi_types[i]); |
488 | } | |
1da177e4 LT |
489 | } |
490 | ||
b54992fe | 491 | u64 smp_irq_stat_cpu(unsigned int cpu) |
37ee16ae | 492 | { |
b54992fe RK |
493 | u64 sum = 0; |
494 | int i; | |
37ee16ae | 495 | |
b54992fe RK |
496 | for (i = 0; i < NR_IPI; i++) |
497 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
37ee16ae | 498 | |
b54992fe | 499 | return sum; |
37ee16ae RK |
500 | } |
501 | ||
bc28248e | 502 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
3d06770e | 503 | void tick_broadcast(const struct cpumask *mask) |
bc28248e | 504 | { |
e3fbb087 | 505 | smp_cross_call(mask, IPI_TIMER); |
bc28248e | 506 | } |
5388a6b2 | 507 | #endif |
bc28248e | 508 | |
bd31b859 | 509 | static DEFINE_RAW_SPINLOCK(stop_lock); |
1da177e4 LT |
510 | |
511 | /* | |
512 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
513 | */ | |
514 | static void ipi_cpu_stop(unsigned int cpu) | |
515 | { | |
3d3f78d7 RK |
516 | if (system_state == SYSTEM_BOOTING || |
517 | system_state == SYSTEM_RUNNING) { | |
bd31b859 | 518 | raw_spin_lock(&stop_lock); |
3d3f78d7 RK |
519 | printk(KERN_CRIT "CPU%u: stopping\n", cpu); |
520 | dump_stack(); | |
bd31b859 | 521 | raw_spin_unlock(&stop_lock); |
3d3f78d7 | 522 | } |
1da177e4 | 523 | |
e03cdade | 524 | set_cpu_online(cpu, false); |
1da177e4 LT |
525 | |
526 | local_fiq_disable(); | |
527 | local_irq_disable(); | |
528 | ||
529 | while (1) | |
530 | cpu_relax(); | |
531 | } | |
532 | ||
5135d875 NP |
533 | static DEFINE_PER_CPU(struct completion *, cpu_completion); |
534 | ||
535 | int register_ipi_completion(struct completion *completion, int cpu) | |
536 | { | |
537 | per_cpu(cpu_completion, cpu) = completion; | |
538 | return IPI_COMPLETION; | |
539 | } | |
540 | ||
541 | static void ipi_complete(unsigned int cpu) | |
542 | { | |
543 | complete(per_cpu(cpu_completion, cpu)); | |
544 | } | |
545 | ||
1da177e4 LT |
546 | /* |
547 | * Main handler for inter-processor interrupts | |
1da177e4 | 548 | */ |
4073723a | 549 | asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) |
0b5a1b95 SG |
550 | { |
551 | handle_IPI(ipinr, regs); | |
552 | } | |
553 | ||
554 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
1da177e4 LT |
555 | { |
556 | unsigned int cpu = smp_processor_id(); | |
c97d4869 | 557 | struct pt_regs *old_regs = set_irq_regs(regs); |
1da177e4 | 558 | |
559a5939 SB |
559 | if (ipinr < NR_IPI) |
560 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); | |
1da177e4 | 561 | |
24480d98 | 562 | switch (ipinr) { |
559a5939 SB |
563 | case IPI_WAKEUP: |
564 | break; | |
565 | ||
e2c50119 | 566 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
24480d98 | 567 | case IPI_TIMER: |
7deabca0 | 568 | irq_enter(); |
e2c50119 | 569 | tick_receive_broadcast(); |
7deabca0 | 570 | irq_exit(); |
24480d98 | 571 | break; |
e2c50119 | 572 | #endif |
1da177e4 | 573 | |
24480d98 | 574 | case IPI_RESCHEDULE: |
184748cc | 575 | scheduler_ipi(); |
24480d98 | 576 | break; |
1da177e4 | 577 | |
24480d98 | 578 | case IPI_CALL_FUNC: |
7deabca0 | 579 | irq_enter(); |
24480d98 | 580 | generic_smp_call_function_interrupt(); |
7deabca0 | 581 | irq_exit(); |
24480d98 | 582 | break; |
f6dd9fa5 | 583 | |
24480d98 | 584 | case IPI_CALL_FUNC_SINGLE: |
7deabca0 | 585 | irq_enter(); |
24480d98 | 586 | generic_smp_call_function_single_interrupt(); |
7deabca0 | 587 | irq_exit(); |
24480d98 | 588 | break; |
1da177e4 | 589 | |
24480d98 | 590 | case IPI_CPU_STOP: |
7deabca0 | 591 | irq_enter(); |
24480d98 | 592 | ipi_cpu_stop(cpu); |
7deabca0 | 593 | irq_exit(); |
24480d98 | 594 | break; |
1da177e4 | 595 | |
bf18525f SB |
596 | #ifdef CONFIG_IRQ_WORK |
597 | case IPI_IRQ_WORK: | |
598 | irq_enter(); | |
599 | irq_work_run(); | |
600 | irq_exit(); | |
601 | break; | |
602 | #endif | |
603 | ||
5135d875 NP |
604 | case IPI_COMPLETION: |
605 | irq_enter(); | |
606 | ipi_complete(cpu); | |
607 | irq_exit(); | |
608 | break; | |
609 | ||
24480d98 RK |
610 | default: |
611 | printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n", | |
612 | cpu, ipinr); | |
613 | break; | |
1da177e4 | 614 | } |
c97d4869 | 615 | set_irq_regs(old_regs); |
1da177e4 LT |
616 | } |
617 | ||
618 | void smp_send_reschedule(int cpu) | |
619 | { | |
e3fbb087 | 620 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); |
1da177e4 LT |
621 | } |
622 | ||
1da177e4 LT |
623 | void smp_send_stop(void) |
624 | { | |
28e18293 | 625 | unsigned long timeout; |
6fa99b7f | 626 | struct cpumask mask; |
1da177e4 | 627 | |
6fa99b7f WD |
628 | cpumask_copy(&mask, cpu_online_mask); |
629 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
c5dff4ff JMC |
630 | if (!cpumask_empty(&mask)) |
631 | smp_cross_call(&mask, IPI_CPU_STOP); | |
4b0ef3b1 | 632 | |
28e18293 RK |
633 | /* Wait up to one second for other CPUs to stop */ |
634 | timeout = USEC_PER_SEC; | |
635 | while (num_online_cpus() > 1 && timeout--) | |
636 | udelay(1); | |
4b0ef3b1 | 637 | |
28e18293 RK |
638 | if (num_online_cpus() > 1) |
639 | pr_warning("SMP: failed to stop secondary CPUs\n"); | |
4b0ef3b1 RK |
640 | } |
641 | ||
4b0ef3b1 | 642 | /* |
1da177e4 | 643 | * not supported here |
4b0ef3b1 | 644 | */ |
5048bcba | 645 | int setup_profiling_timer(unsigned int multiplier) |
4b0ef3b1 | 646 | { |
1da177e4 | 647 | return -EINVAL; |
4b0ef3b1 | 648 | } |
ec971ea5 RZ |
649 | |
650 | #ifdef CONFIG_CPU_FREQ | |
651 | ||
652 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref); | |
653 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq); | |
654 | static unsigned long global_l_p_j_ref; | |
655 | static unsigned long global_l_p_j_ref_freq; | |
656 | ||
657 | static int cpufreq_callback(struct notifier_block *nb, | |
658 | unsigned long val, void *data) | |
659 | { | |
660 | struct cpufreq_freqs *freq = data; | |
661 | int cpu = freq->cpu; | |
662 | ||
663 | if (freq->flags & CPUFREQ_CONST_LOOPS) | |
664 | return NOTIFY_OK; | |
665 | ||
666 | if (!per_cpu(l_p_j_ref, cpu)) { | |
667 | per_cpu(l_p_j_ref, cpu) = | |
668 | per_cpu(cpu_data, cpu).loops_per_jiffy; | |
669 | per_cpu(l_p_j_ref_freq, cpu) = freq->old; | |
670 | if (!global_l_p_j_ref) { | |
671 | global_l_p_j_ref = loops_per_jiffy; | |
672 | global_l_p_j_ref_freq = freq->old; | |
673 | } | |
674 | } | |
675 | ||
676 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 677 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
ec971ea5 RZ |
678 | loops_per_jiffy = cpufreq_scale(global_l_p_j_ref, |
679 | global_l_p_j_ref_freq, | |
680 | freq->new); | |
681 | per_cpu(cpu_data, cpu).loops_per_jiffy = | |
682 | cpufreq_scale(per_cpu(l_p_j_ref, cpu), | |
683 | per_cpu(l_p_j_ref_freq, cpu), | |
684 | freq->new); | |
685 | } | |
686 | return NOTIFY_OK; | |
687 | } | |
688 | ||
689 | static struct notifier_block cpufreq_notifier = { | |
690 | .notifier_call = cpufreq_callback, | |
691 | }; | |
692 | ||
693 | static int __init register_cpufreq_notifier(void) | |
694 | { | |
695 | return cpufreq_register_notifier(&cpufreq_notifier, | |
696 | CPUFREQ_TRANSITION_NOTIFIER); | |
697 | } | |
698 | core_initcall(register_cpufreq_notifier); | |
699 | ||
700 | #endif |