arm: omap2+: add missing HWMOD_NO_IDLEST in 81xx hwmod data
[deliverable/linux.git] / arch / arm / kernel / smp.c
CommitLineData
1da177e4
LT
1/*
2 * linux/arch/arm/kernel/smp.c
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
c97d4869 10#include <linux/module.h>
1da177e4
LT
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16#include <linux/cache.h>
17#include <linux/profile.h>
18#include <linux/errno.h>
19#include <linux/mm.h>
4e950f6f 20#include <linux/err.h>
1da177e4 21#include <linux/cpu.h>
1da177e4 22#include <linux/seq_file.h>
c97d4869 23#include <linux/irq.h>
96f0e003 24#include <linux/nmi.h>
bc28248e
RK
25#include <linux/percpu.h>
26#include <linux/clockchips.h>
3c030bea 27#include <linux/completion.h>
ec971ea5 28#include <linux/cpufreq.h>
bf18525f 29#include <linux/irq_work.h>
1da177e4 30
60063497 31#include <linux/atomic.h>
abcee5fb 32#include <asm/smp.h>
1da177e4
LT
33#include <asm/cacheflush.h>
34#include <asm/cpu.h>
42578c82 35#include <asm/cputype.h>
5a567d78 36#include <asm/exception.h>
8903826d 37#include <asm/idmap.h>
c9018aab 38#include <asm/topology.h>
e65f38ed
RK
39#include <asm/mmu_context.h>
40#include <asm/pgtable.h>
41#include <asm/pgalloc.h>
1da177e4 42#include <asm/processor.h>
37b05b63 43#include <asm/sections.h>
1da177e4
LT
44#include <asm/tlbflush.h>
45#include <asm/ptrace.h>
d6257288 46#include <asm/smp_plat.h>
4588c34d 47#include <asm/virt.h>
abcee5fb 48#include <asm/mach/arch.h>
eb08375e 49#include <asm/mpu.h>
1da177e4 50
365ec7b1
NP
51#define CREATE_TRACE_POINTS
52#include <trace/events/ipi.h>
53
e65f38ed
RK
54/*
55 * as from 2.5, kernels no longer have an init_tasks structure
56 * so we need some other way of telling a new secondary core
57 * where to place its SVC stack
58 */
59struct secondary_data secondary_data;
60
28e8e29c
MZ
61/*
62 * control for which core is the next to come out of the secondary
63 * boot "holding pen"
64 */
8bd26e3a 65volatile int pen_release = -1;
28e8e29c 66
1da177e4 67enum ipi_msg_type {
559a5939
SB
68 IPI_WAKEUP,
69 IPI_TIMER,
1da177e4
LT
70 IPI_RESCHEDULE,
71 IPI_CALL_FUNC,
f6dd9fa5 72 IPI_CALL_FUNC_SINGLE,
1da177e4 73 IPI_CPU_STOP,
bf18525f 74 IPI_IRQ_WORK,
5135d875 75 IPI_COMPLETION,
96f0e003 76 IPI_CPU_BACKTRACE = 15,
1da177e4
LT
77};
78
149c2415
RK
79static DECLARE_COMPLETION(cpu_running);
80
abcee5fb
MZ
81static struct smp_operations smp_ops;
82
4caa9dda 83void __init smp_set_ops(const struct smp_operations *ops)
abcee5fb
MZ
84{
85 if (ops)
86 smp_ops = *ops;
87};
88
4756dcbf
CC
89static unsigned long get_arch_pgd(pgd_t *pgd)
90{
b2c3e38a
RK
91#ifdef CONFIG_ARM_LPAE
92 return __phys_to_pfn(virt_to_phys(pgd));
93#else
94 return virt_to_phys(pgd);
95#endif
4756dcbf
CC
96}
97
8bd26e3a 98int __cpu_up(unsigned int cpu, struct task_struct *idle)
1da177e4 99{
1da177e4
LT
100 int ret;
101
084bb5bc
GU
102 if (!smp_ops.smp_boot_secondary)
103 return -ENOSYS;
104
e65f38ed
RK
105 /*
106 * We need to tell the secondary core where to find
107 * its stack and the page tables.
108 */
32d39a93 109 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
eb08375e
JA
110#ifdef CONFIG_ARM_MPU
111 secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr;
112#endif
113
c4a1f032 114#ifdef CONFIG_MMU
b2c3e38a 115 secondary_data.pgdir = virt_to_phys(idmap_pgd);
4756dcbf 116 secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
c4a1f032 117#endif
efcfc46e 118 sync_cache_w(&secondary_data);
e65f38ed 119
1da177e4
LT
120 /*
121 * Now bring the CPU into our world.
122 */
084bb5bc 123 ret = smp_ops.smp_boot_secondary(cpu, idle);
e65f38ed 124 if (ret == 0) {
e65f38ed
RK
125 /*
126 * CPU was successfully started, wait for it
127 * to come online or time out.
128 */
149c2415
RK
129 wait_for_completion_timeout(&cpu_running,
130 msecs_to_jiffies(1000));
e65f38ed 131
58613cd1
RK
132 if (!cpu_online(cpu)) {
133 pr_crit("CPU%u: failed to come online\n", cpu);
e65f38ed 134 ret = -EIO;
58613cd1
RK
135 }
136 } else {
137 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
e65f38ed
RK
138 }
139
e65f38ed 140
eb08375e 141 memset(&secondary_data, 0, sizeof(secondary_data));
1da177e4
LT
142 return ret;
143}
144
abcee5fb 145/* platform specific SMP operations */
ac6c7998 146void __init smp_init_cpus(void)
abcee5fb
MZ
147{
148 if (smp_ops.smp_init_cpus)
149 smp_ops.smp_init_cpus();
150}
151
fee3fd4f
GU
152int platform_can_secondary_boot(void)
153{
154 return !!smp_ops.smp_boot_secondary;
155}
156
2103f6cb
SW
157int platform_can_cpu_hotplug(void)
158{
159#ifdef CONFIG_HOTPLUG_CPU
160 if (smp_ops.cpu_kill)
161 return 1;
162#endif
163
164 return 0;
165}
166
a054a811 167#ifdef CONFIG_HOTPLUG_CPU
ac6c7998 168static int platform_cpu_kill(unsigned int cpu)
abcee5fb
MZ
169{
170 if (smp_ops.cpu_kill)
171 return smp_ops.cpu_kill(cpu);
172 return 1;
173}
174
ac6c7998 175static int platform_cpu_disable(unsigned int cpu)
abcee5fb
MZ
176{
177 if (smp_ops.cpu_disable)
178 return smp_ops.cpu_disable(cpu);
179
787047ee
SB
180 return 0;
181}
182
183int platform_can_hotplug_cpu(unsigned int cpu)
184{
185 /* cpu_die must be specified to support hotplug */
186 if (!smp_ops.cpu_die)
187 return 0;
188
189 if (smp_ops.cpu_can_disable)
190 return smp_ops.cpu_can_disable(cpu);
191
abcee5fb
MZ
192 /*
193 * By default, allow disabling all CPUs except the first one,
194 * since this is special on a lot of platforms, e.g. because
195 * of clock tick interrupts.
196 */
787047ee 197 return cpu != 0;
abcee5fb 198}
787047ee 199
a054a811
RK
200/*
201 * __cpu_disable runs on the processor to be shutdown.
202 */
8bd26e3a 203int __cpu_disable(void)
a054a811
RK
204{
205 unsigned int cpu = smp_processor_id();
a054a811
RK
206 int ret;
207
8e2a43f5 208 ret = platform_cpu_disable(cpu);
a054a811
RK
209 if (ret)
210 return ret;
211
212 /*
213 * Take this CPU offline. Once we clear this, we can't return,
214 * and we must not schedule until we're ready to give up the cpu.
215 */
e03cdade 216 set_cpu_online(cpu, false);
a054a811
RK
217
218 /*
219 * OK - migrate IRQs away from this CPU
220 */
221 migrate_irqs();
222
223 /*
224 * Flush user cache and TLB mappings, and then remove this CPU
225 * from the vm mask set of all processes.
e6b866e9
LP
226 *
227 * Caches are flushed to the Level of Unification Inner Shareable
228 * to write-back dirty lines to unified caches shared by all CPUs.
a054a811 229 */
e6b866e9 230 flush_cache_louis();
a054a811
RK
231 local_flush_tlb_all();
232
3eaa73bd 233 clear_tasks_mm_cpumask(cpu);
a054a811
RK
234
235 return 0;
236}
237
3c030bea
RK
238static DECLARE_COMPLETION(cpu_died);
239
a054a811
RK
240/*
241 * called on the thread which is asking for a CPU to be shutdown -
242 * waits until shutdown has completed, or it is timed out.
243 */
8bd26e3a 244void __cpu_die(unsigned int cpu)
a054a811 245{
3c030bea
RK
246 if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
247 pr_err("CPU%u: cpu didn't die\n", cpu);
248 return;
249 }
4ed89f22 250 pr_notice("CPU%u: shutdown\n", cpu);
3c030bea 251
51acdfd1
RK
252 /*
253 * platform_cpu_kill() is generally expected to do the powering off
254 * and/or cutting of clocks to the dying CPU. Optionally, this may
255 * be done by the CPU which is dying in preference to supporting
256 * this call, but that means there is _no_ synchronisation between
257 * the requesting CPU and the dying CPU actually losing power.
258 */
a054a811 259 if (!platform_cpu_kill(cpu))
4ed89f22 260 pr_err("CPU%u: unable to kill\n", cpu);
a054a811
RK
261}
262
263/*
264 * Called from the idle thread for the CPU which has been shutdown.
265 *
266 * Note that we disable IRQs here, but do not re-enable them
267 * before returning to the caller. This is also the behaviour
268 * of the other hotplug-cpu capable cores, so presumably coming
269 * out of idle fixes this.
270 */
9205b797 271void arch_cpu_idle_dead(void)
a054a811
RK
272{
273 unsigned int cpu = smp_processor_id();
274
a054a811
RK
275 idle_task_exit();
276
f36d3401 277 local_irq_disable();
f36d3401 278
51acdfd1
RK
279 /*
280 * Flush the data out of the L1 cache for this CPU. This must be
281 * before the completion to ensure that data is safely written out
282 * before platform_cpu_kill() gets called - which may disable
283 * *this* CPU and power down its cache.
284 */
285 flush_cache_louis();
286
287 /*
288 * Tell __cpu_die() that this CPU is now safe to dispose of. Once
289 * this returns, power and/or clocks can be removed at any point
290 * from this CPU and its cache by platform_cpu_kill().
291 */
aa033810 292 complete(&cpu_died);
3c030bea 293
a054a811 294 /*
51acdfd1
RK
295 * Ensure that the cache lines associated with that completion are
296 * written out. This covers the case where _this_ CPU is doing the
297 * powering down, to ensure that the completion is visible to the
298 * CPU waiting for this one.
299 */
300 flush_cache_louis();
301
302 /*
303 * The actual CPU shutdown procedure is at least platform (if not
304 * CPU) specific. This may remove power, or it may simply spin.
305 *
306 * Platforms are generally expected *NOT* to return from this call,
307 * although there are some which do because they have no way to
308 * power down the CPU. These platforms are the _only_ reason we
309 * have a return path which uses the fragment of assembly below.
310 *
311 * The return path should not be used for platforms which can
312 * power off the CPU.
a054a811 313 */
0a301110
RK
314 if (smp_ops.cpu_die)
315 smp_ops.cpu_die(cpu);
a054a811 316
668bc386
RK
317 pr_warn("CPU%u: smp_ops.cpu_die() returned, trying to resuscitate\n",
318 cpu);
319
a054a811
RK
320 /*
321 * Do not return to the idle loop - jump back to the secondary
322 * cpu initialisation. There's some initialisation which needs
323 * to be repeated to undo the effects of taking the CPU offline.
324 */
325 __asm__("mov sp, %0\n"
faabfa08 326 " mov fp, #0\n"
a054a811
RK
327 " b secondary_start_kernel"
328 :
32d39a93 329 : "r" (task_stack_page(current) + THREAD_SIZE - 8));
a054a811
RK
330}
331#endif /* CONFIG_HOTPLUG_CPU */
332
05c74a6c
RK
333/*
334 * Called by both boot and secondaries to move global data into
335 * per-processor storage.
336 */
8bd26e3a 337static void smp_store_cpu_info(unsigned int cpuid)
05c74a6c
RK
338{
339 struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
340
341 cpu_info->loops_per_jiffy = loops_per_jiffy;
e8d432c9 342 cpu_info->cpuid = read_cpuid_id();
c9018aab
VG
343
344 store_cpu_topology(cpuid);
05c74a6c
RK
345}
346
e65f38ed
RK
347/*
348 * This is the secondary CPU boot entry. We're using this CPUs
349 * idle thread stack, but a set of temporary page tables.
350 */
8bd26e3a 351asmlinkage void secondary_start_kernel(void)
e65f38ed
RK
352{
353 struct mm_struct *mm = &init_mm;
5f40b909
WD
354 unsigned int cpu;
355
356 /*
357 * The identity mapping is uncached (strongly ordered), so
358 * switch away from it before attempting any exclusive accesses.
359 */
360 cpu_switch_mm(mm->pgd, mm);
89c7e4b8 361 local_flush_bp_all();
5f40b909
WD
362 enter_lazy_tlb(mm, current);
363 local_flush_tlb_all();
e65f38ed 364
e65f38ed
RK
365 /*
366 * All kernel threads share the same mm context; grab a
367 * reference and switch to it.
368 */
5f40b909 369 cpu = smp_processor_id();
e65f38ed
RK
370 atomic_inc(&mm->mm_count);
371 current->active_mm = mm;
56f8ba83 372 cpumask_set_cpu(cpu, mm_cpumask(mm));
e65f38ed 373
14318efb
RH
374 cpu_init();
375
c68b0274 376 pr_debug("CPU%u: Booted secondary processor\n", cpu);
fde165b2 377
5bfb5d69 378 preempt_disable();
2c0136db 379 trace_hardirqs_off();
e65f38ed
RK
380
381 /*
382 * Give the platform a chance to do its own initialisation.
383 */
0a301110
RK
384 if (smp_ops.smp_secondary_init)
385 smp_ops.smp_secondary_init(cpu);
e65f38ed 386
e545a614 387 notify_cpu_starting(cpu);
a8655e83 388
e65f38ed
RK
389 calibrate_delay();
390
391 smp_store_cpu_info(cpu);
392
393 /*
573619d1
RK
394 * OK, now it's safe to let the boot CPU continue. Wait for
395 * the CPU migration code to notice that the CPU is online
149c2415 396 * before we continue - which happens after __cpu_up returns.
e65f38ed 397 */
e03cdade 398 set_cpu_online(cpu, true);
149c2415 399 complete(&cpu_running);
eb047454 400
eb047454
TG
401 local_irq_enable();
402 local_fiq_enable();
bbeb9209 403 local_abt_enable();
eb047454 404
e65f38ed
RK
405 /*
406 * OK, it's off to the idle thread for us
407 */
f7b861b7 408 cpu_startup_entry(CPUHP_ONLINE);
e65f38ed
RK
409}
410
1da177e4
LT
411void __init smp_cpus_done(unsigned int max_cpus)
412{
4bf9636c
PM
413 int cpu;
414 unsigned long bogosum = 0;
415
416 for_each_online_cpu(cpu)
417 bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
418
419 printk(KERN_INFO "SMP: Total of %d processors activated "
420 "(%lu.%02lu BogoMIPS).\n",
421 num_online_cpus(),
422 bogosum / (500000/HZ),
423 (bogosum / (5000/HZ)) % 100);
424
4588c34d 425 hyp_mode_check();
1da177e4
LT
426}
427
428void __init smp_prepare_boot_cpu(void)
429{
14318efb 430 set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
1da177e4
LT
431}
432
05c74a6c 433void __init smp_prepare_cpus(unsigned int max_cpus)
1da177e4 434{
05c74a6c 435 unsigned int ncores = num_possible_cpus();
1da177e4 436
c9018aab
VG
437 init_cpu_topology();
438
05c74a6c 439 smp_store_cpu_info(smp_processor_id());
1da177e4
LT
440
441 /*
05c74a6c 442 * are we trying to boot more cores than exist?
1da177e4 443 */
05c74a6c
RK
444 if (max_cpus > ncores)
445 max_cpus = ncores;
7fa22bd5 446 if (ncores > 1 && max_cpus) {
7fa22bd5
SB
447 /*
448 * Initialise the present map, which describes the set of CPUs
449 * actually populated at the present time. A platform should
0a301110
RK
450 * re-initialize the map in the platforms smp_prepare_cpus()
451 * if present != possible (e.g. physical hotplug).
7fa22bd5 452 */
0b5f9c00 453 init_cpu_present(cpu_possible_mask);
7fa22bd5 454
05c74a6c
RK
455 /*
456 * Initialise the SCU if there are more than one CPU
457 * and let them know where to start.
458 */
0a301110
RK
459 if (smp_ops.smp_prepare_cpus)
460 smp_ops.smp_prepare_cpus(max_cpus);
05c74a6c 461 }
1da177e4
LT
462}
463
365ec7b1 464static void (*__smp_cross_call)(const struct cpumask *, unsigned int);
0f7b332f
RK
465
466void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
467{
365ec7b1
NP
468 if (!__smp_cross_call)
469 __smp_cross_call = fn;
3e459990 470}
3e459990 471
365ec7b1 472static const char *ipi_types[NR_IPI] __tracepoint_string = {
559a5939
SB
473#define S(x,s) [x] = s
474 S(IPI_WAKEUP, "CPU wakeup interrupts"),
4a88abd7
RK
475 S(IPI_TIMER, "Timer broadcast interrupts"),
476 S(IPI_RESCHEDULE, "Rescheduling interrupts"),
477 S(IPI_CALL_FUNC, "Function call interrupts"),
478 S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
479 S(IPI_CPU_STOP, "CPU stop interrupts"),
bf18525f 480 S(IPI_IRQ_WORK, "IRQ work interrupts"),
5135d875 481 S(IPI_COMPLETION, "completion interrupts"),
4a88abd7
RK
482};
483
365ec7b1
NP
484static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
485{
486 trace_ipi_raise(target, ipi_types[ipinr]);
487 __smp_cross_call(target, ipinr);
488}
489
f13cd417 490void show_ipi_list(struct seq_file *p, int prec)
1da177e4 491{
4a88abd7 492 unsigned int cpu, i;
1da177e4 493
4a88abd7
RK
494 for (i = 0; i < NR_IPI; i++) {
495 seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
1da177e4 496
026b7c6b 497 for_each_online_cpu(cpu)
4a88abd7
RK
498 seq_printf(p, "%10u ",
499 __get_irq_stat(cpu, ipi_irqs[i]));
1da177e4 500
4a88abd7
RK
501 seq_printf(p, " %s\n", ipi_types[i]);
502 }
1da177e4
LT
503}
504
b54992fe 505u64 smp_irq_stat_cpu(unsigned int cpu)
37ee16ae 506{
b54992fe
RK
507 u64 sum = 0;
508 int i;
37ee16ae 509
b54992fe
RK
510 for (i = 0; i < NR_IPI; i++)
511 sum += __get_irq_stat(cpu, ipi_irqs[i]);
37ee16ae 512
b54992fe 513 return sum;
37ee16ae
RK
514}
515
365ec7b1
NP
516void arch_send_call_function_ipi_mask(const struct cpumask *mask)
517{
518 smp_cross_call(mask, IPI_CALL_FUNC);
519}
520
521void arch_send_wakeup_ipi_mask(const struct cpumask *mask)
522{
523 smp_cross_call(mask, IPI_WAKEUP);
524}
525
526void arch_send_call_function_single_ipi(int cpu)
527{
528 smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
529}
530
531#ifdef CONFIG_IRQ_WORK
532void arch_irq_work_raise(void)
533{
09f6edd4 534 if (arch_irq_work_has_interrupt())
365ec7b1
NP
535 smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
536}
537#endif
538
bc28248e 539#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
3d06770e 540void tick_broadcast(const struct cpumask *mask)
bc28248e 541{
e3fbb087 542 smp_cross_call(mask, IPI_TIMER);
bc28248e 543}
5388a6b2 544#endif
bc28248e 545
bd31b859 546static DEFINE_RAW_SPINLOCK(stop_lock);
1da177e4
LT
547
548/*
549 * ipi_cpu_stop - handle IPI from smp_send_stop()
550 */
551static void ipi_cpu_stop(unsigned int cpu)
552{
3d3f78d7
RK
553 if (system_state == SYSTEM_BOOTING ||
554 system_state == SYSTEM_RUNNING) {
bd31b859 555 raw_spin_lock(&stop_lock);
4ed89f22 556 pr_crit("CPU%u: stopping\n", cpu);
3d3f78d7 557 dump_stack();
bd31b859 558 raw_spin_unlock(&stop_lock);
3d3f78d7 559 }
1da177e4 560
e03cdade 561 set_cpu_online(cpu, false);
1da177e4
LT
562
563 local_fiq_disable();
564 local_irq_disable();
565
566 while (1)
567 cpu_relax();
568}
569
5135d875
NP
570static DEFINE_PER_CPU(struct completion *, cpu_completion);
571
572int register_ipi_completion(struct completion *completion, int cpu)
573{
574 per_cpu(cpu_completion, cpu) = completion;
575 return IPI_COMPLETION;
576}
577
578static void ipi_complete(unsigned int cpu)
579{
580 complete(per_cpu(cpu_completion, cpu));
581}
582
1da177e4
LT
583/*
584 * Main handler for inter-processor interrupts
1da177e4 585 */
4073723a 586asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs)
0b5a1b95
SG
587{
588 handle_IPI(ipinr, regs);
589}
590
591void handle_IPI(int ipinr, struct pt_regs *regs)
1da177e4
LT
592{
593 unsigned int cpu = smp_processor_id();
c97d4869 594 struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 595
365ec7b1 596 if ((unsigned)ipinr < NR_IPI) {
398f7456 597 trace_ipi_entry_rcuidle(ipi_types[ipinr]);
559a5939 598 __inc_irq_stat(cpu, ipi_irqs[ipinr]);
365ec7b1 599 }
1da177e4 600
24480d98 601 switch (ipinr) {
559a5939
SB
602 case IPI_WAKEUP:
603 break;
604
e2c50119 605#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
24480d98 606 case IPI_TIMER:
7deabca0 607 irq_enter();
e2c50119 608 tick_receive_broadcast();
7deabca0 609 irq_exit();
24480d98 610 break;
e2c50119 611#endif
1da177e4 612
24480d98 613 case IPI_RESCHEDULE:
184748cc 614 scheduler_ipi();
24480d98 615 break;
1da177e4 616
24480d98 617 case IPI_CALL_FUNC:
7deabca0 618 irq_enter();
24480d98 619 generic_smp_call_function_interrupt();
7deabca0 620 irq_exit();
24480d98 621 break;
f6dd9fa5 622
24480d98 623 case IPI_CALL_FUNC_SINGLE:
7deabca0 624 irq_enter();
24480d98 625 generic_smp_call_function_single_interrupt();
7deabca0 626 irq_exit();
24480d98 627 break;
1da177e4 628
24480d98 629 case IPI_CPU_STOP:
7deabca0 630 irq_enter();
24480d98 631 ipi_cpu_stop(cpu);
7deabca0 632 irq_exit();
24480d98 633 break;
1da177e4 634
bf18525f
SB
635#ifdef CONFIG_IRQ_WORK
636 case IPI_IRQ_WORK:
637 irq_enter();
638 irq_work_run();
639 irq_exit();
640 break;
641#endif
642
5135d875
NP
643 case IPI_COMPLETION:
644 irq_enter();
645 ipi_complete(cpu);
646 irq_exit();
647 break;
648
96f0e003
RK
649 case IPI_CPU_BACKTRACE:
650 irq_enter();
651 nmi_cpu_backtrace(regs);
652 irq_exit();
653 break;
654
24480d98 655 default:
4ed89f22
RK
656 pr_crit("CPU%u: Unknown IPI message 0x%x\n",
657 cpu, ipinr);
24480d98 658 break;
1da177e4 659 }
365ec7b1
NP
660
661 if ((unsigned)ipinr < NR_IPI)
398f7456 662 trace_ipi_exit_rcuidle(ipi_types[ipinr]);
c97d4869 663 set_irq_regs(old_regs);
1da177e4
LT
664}
665
666void smp_send_reschedule(int cpu)
667{
e3fbb087 668 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
1da177e4
LT
669}
670
1da177e4
LT
671void smp_send_stop(void)
672{
28e18293 673 unsigned long timeout;
6fa99b7f 674 struct cpumask mask;
1da177e4 675
6fa99b7f
WD
676 cpumask_copy(&mask, cpu_online_mask);
677 cpumask_clear_cpu(smp_processor_id(), &mask);
c5dff4ff
JMC
678 if (!cpumask_empty(&mask))
679 smp_cross_call(&mask, IPI_CPU_STOP);
4b0ef3b1 680
28e18293
RK
681 /* Wait up to one second for other CPUs to stop */
682 timeout = USEC_PER_SEC;
683 while (num_online_cpus() > 1 && timeout--)
684 udelay(1);
4b0ef3b1 685
28e18293 686 if (num_online_cpus() > 1)
8b521cb2 687 pr_warn("SMP: failed to stop secondary CPUs\n");
4b0ef3b1
RK
688}
689
4b0ef3b1 690/*
1da177e4 691 * not supported here
4b0ef3b1 692 */
5048bcba 693int setup_profiling_timer(unsigned int multiplier)
4b0ef3b1 694{
1da177e4 695 return -EINVAL;
4b0ef3b1 696}
ec971ea5
RZ
697
698#ifdef CONFIG_CPU_FREQ
699
700static DEFINE_PER_CPU(unsigned long, l_p_j_ref);
701static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq);
702static unsigned long global_l_p_j_ref;
703static unsigned long global_l_p_j_ref_freq;
704
705static int cpufreq_callback(struct notifier_block *nb,
706 unsigned long val, void *data)
707{
708 struct cpufreq_freqs *freq = data;
709 int cpu = freq->cpu;
710
711 if (freq->flags & CPUFREQ_CONST_LOOPS)
712 return NOTIFY_OK;
713
714 if (!per_cpu(l_p_j_ref, cpu)) {
715 per_cpu(l_p_j_ref, cpu) =
716 per_cpu(cpu_data, cpu).loops_per_jiffy;
717 per_cpu(l_p_j_ref_freq, cpu) = freq->old;
718 if (!global_l_p_j_ref) {
719 global_l_p_j_ref = loops_per_jiffy;
720 global_l_p_j_ref_freq = freq->old;
721 }
722 }
723
724 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
0b443ead 725 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
ec971ea5
RZ
726 loops_per_jiffy = cpufreq_scale(global_l_p_j_ref,
727 global_l_p_j_ref_freq,
728 freq->new);
729 per_cpu(cpu_data, cpu).loops_per_jiffy =
730 cpufreq_scale(per_cpu(l_p_j_ref, cpu),
731 per_cpu(l_p_j_ref_freq, cpu),
732 freq->new);
733 }
734 return NOTIFY_OK;
735}
736
737static struct notifier_block cpufreq_notifier = {
738 .notifier_call = cpufreq_callback,
739};
740
741static int __init register_cpufreq_notifier(void)
742{
743 return cpufreq_register_notifier(&cpufreq_notifier,
744 CPUFREQ_TRANSITION_NOTIFIER);
745}
746core_initcall(register_cpufreq_notifier);
747
748#endif
96f0e003
RK
749
750static void raise_nmi(cpumask_t *mask)
751{
0768330d
DT
752 /*
753 * Generate the backtrace directly if we are running in a calling
754 * context that is not preemptible by the backtrace IPI. Note
755 * that nmi_cpu_backtrace() automatically removes the current cpu
756 * from mask.
757 */
758 if (cpumask_test_cpu(smp_processor_id(), mask) && irqs_disabled())
759 nmi_cpu_backtrace(NULL);
760
96f0e003
RK
761 smp_cross_call(mask, IPI_CPU_BACKTRACE);
762}
763
764void arch_trigger_all_cpu_backtrace(bool include_self)
765{
766 nmi_trigger_all_cpu_backtrace(include_self, raise_nmi);
767}
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