Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/smp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
c97d4869 | 10 | #include <linux/module.h> |
1da177e4 LT |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/cache.h> | |
17 | #include <linux/profile.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/mm.h> | |
4e950f6f | 20 | #include <linux/err.h> |
1da177e4 | 21 | #include <linux/cpu.h> |
1da177e4 | 22 | #include <linux/seq_file.h> |
c97d4869 | 23 | #include <linux/irq.h> |
96f0e003 | 24 | #include <linux/nmi.h> |
bc28248e RK |
25 | #include <linux/percpu.h> |
26 | #include <linux/clockchips.h> | |
3c030bea | 27 | #include <linux/completion.h> |
ec971ea5 | 28 | #include <linux/cpufreq.h> |
bf18525f | 29 | #include <linux/irq_work.h> |
1da177e4 | 30 | |
60063497 | 31 | #include <linux/atomic.h> |
abcee5fb | 32 | #include <asm/smp.h> |
1da177e4 LT |
33 | #include <asm/cacheflush.h> |
34 | #include <asm/cpu.h> | |
42578c82 | 35 | #include <asm/cputype.h> |
5a567d78 | 36 | #include <asm/exception.h> |
8903826d | 37 | #include <asm/idmap.h> |
c9018aab | 38 | #include <asm/topology.h> |
e65f38ed RK |
39 | #include <asm/mmu_context.h> |
40 | #include <asm/pgtable.h> | |
41 | #include <asm/pgalloc.h> | |
1da177e4 | 42 | #include <asm/processor.h> |
37b05b63 | 43 | #include <asm/sections.h> |
1da177e4 LT |
44 | #include <asm/tlbflush.h> |
45 | #include <asm/ptrace.h> | |
d6257288 | 46 | #include <asm/smp_plat.h> |
4588c34d | 47 | #include <asm/virt.h> |
abcee5fb | 48 | #include <asm/mach/arch.h> |
eb08375e | 49 | #include <asm/mpu.h> |
1da177e4 | 50 | |
365ec7b1 NP |
51 | #define CREATE_TRACE_POINTS |
52 | #include <trace/events/ipi.h> | |
53 | ||
e65f38ed RK |
54 | /* |
55 | * as from 2.5, kernels no longer have an init_tasks structure | |
56 | * so we need some other way of telling a new secondary core | |
57 | * where to place its SVC stack | |
58 | */ | |
59 | struct secondary_data secondary_data; | |
60 | ||
28e8e29c MZ |
61 | /* |
62 | * control for which core is the next to come out of the secondary | |
63 | * boot "holding pen" | |
64 | */ | |
8bd26e3a | 65 | volatile int pen_release = -1; |
28e8e29c | 66 | |
1da177e4 | 67 | enum ipi_msg_type { |
559a5939 SB |
68 | IPI_WAKEUP, |
69 | IPI_TIMER, | |
1da177e4 LT |
70 | IPI_RESCHEDULE, |
71 | IPI_CALL_FUNC, | |
72 | IPI_CPU_STOP, | |
bf18525f | 73 | IPI_IRQ_WORK, |
5135d875 | 74 | IPI_COMPLETION, |
e7273ff4 MZ |
75 | IPI_CPU_BACKTRACE, |
76 | /* | |
77 | * SGI8-15 can be reserved by secure firmware, and thus may | |
78 | * not be usable by the kernel. Please keep the above limited | |
79 | * to at most 8 entries. | |
80 | */ | |
1da177e4 LT |
81 | }; |
82 | ||
149c2415 RK |
83 | static DECLARE_COMPLETION(cpu_running); |
84 | ||
abcee5fb MZ |
85 | static struct smp_operations smp_ops; |
86 | ||
4caa9dda | 87 | void __init smp_set_ops(const struct smp_operations *ops) |
abcee5fb MZ |
88 | { |
89 | if (ops) | |
90 | smp_ops = *ops; | |
91 | }; | |
92 | ||
4756dcbf CC |
93 | static unsigned long get_arch_pgd(pgd_t *pgd) |
94 | { | |
b2c3e38a RK |
95 | #ifdef CONFIG_ARM_LPAE |
96 | return __phys_to_pfn(virt_to_phys(pgd)); | |
97 | #else | |
98 | return virt_to_phys(pgd); | |
99 | #endif | |
4756dcbf CC |
100 | } |
101 | ||
8bd26e3a | 102 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
1da177e4 | 103 | { |
1da177e4 LT |
104 | int ret; |
105 | ||
084bb5bc GU |
106 | if (!smp_ops.smp_boot_secondary) |
107 | return -ENOSYS; | |
108 | ||
e65f38ed RK |
109 | /* |
110 | * We need to tell the secondary core where to find | |
111 | * its stack and the page tables. | |
112 | */ | |
32d39a93 | 113 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; |
eb08375e JA |
114 | #ifdef CONFIG_ARM_MPU |
115 | secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr; | |
116 | #endif | |
117 | ||
c4a1f032 | 118 | #ifdef CONFIG_MMU |
b2c3e38a | 119 | secondary_data.pgdir = virt_to_phys(idmap_pgd); |
4756dcbf | 120 | secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir); |
c4a1f032 | 121 | #endif |
efcfc46e | 122 | sync_cache_w(&secondary_data); |
e65f38ed | 123 | |
1da177e4 LT |
124 | /* |
125 | * Now bring the CPU into our world. | |
126 | */ | |
084bb5bc | 127 | ret = smp_ops.smp_boot_secondary(cpu, idle); |
e65f38ed | 128 | if (ret == 0) { |
e65f38ed RK |
129 | /* |
130 | * CPU was successfully started, wait for it | |
131 | * to come online or time out. | |
132 | */ | |
149c2415 RK |
133 | wait_for_completion_timeout(&cpu_running, |
134 | msecs_to_jiffies(1000)); | |
e65f38ed | 135 | |
58613cd1 RK |
136 | if (!cpu_online(cpu)) { |
137 | pr_crit("CPU%u: failed to come online\n", cpu); | |
e65f38ed | 138 | ret = -EIO; |
58613cd1 RK |
139 | } |
140 | } else { | |
141 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
e65f38ed RK |
142 | } |
143 | ||
e65f38ed | 144 | |
eb08375e | 145 | memset(&secondary_data, 0, sizeof(secondary_data)); |
1da177e4 LT |
146 | return ret; |
147 | } | |
148 | ||
abcee5fb | 149 | /* platform specific SMP operations */ |
ac6c7998 | 150 | void __init smp_init_cpus(void) |
abcee5fb MZ |
151 | { |
152 | if (smp_ops.smp_init_cpus) | |
153 | smp_ops.smp_init_cpus(); | |
154 | } | |
155 | ||
fee3fd4f GU |
156 | int platform_can_secondary_boot(void) |
157 | { | |
158 | return !!smp_ops.smp_boot_secondary; | |
159 | } | |
160 | ||
2103f6cb SW |
161 | int platform_can_cpu_hotplug(void) |
162 | { | |
163 | #ifdef CONFIG_HOTPLUG_CPU | |
164 | if (smp_ops.cpu_kill) | |
165 | return 1; | |
166 | #endif | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
a054a811 | 171 | #ifdef CONFIG_HOTPLUG_CPU |
ac6c7998 | 172 | static int platform_cpu_kill(unsigned int cpu) |
abcee5fb MZ |
173 | { |
174 | if (smp_ops.cpu_kill) | |
175 | return smp_ops.cpu_kill(cpu); | |
176 | return 1; | |
177 | } | |
178 | ||
ac6c7998 | 179 | static int platform_cpu_disable(unsigned int cpu) |
abcee5fb MZ |
180 | { |
181 | if (smp_ops.cpu_disable) | |
182 | return smp_ops.cpu_disable(cpu); | |
183 | ||
787047ee SB |
184 | return 0; |
185 | } | |
186 | ||
187 | int platform_can_hotplug_cpu(unsigned int cpu) | |
188 | { | |
189 | /* cpu_die must be specified to support hotplug */ | |
190 | if (!smp_ops.cpu_die) | |
191 | return 0; | |
192 | ||
193 | if (smp_ops.cpu_can_disable) | |
194 | return smp_ops.cpu_can_disable(cpu); | |
195 | ||
abcee5fb MZ |
196 | /* |
197 | * By default, allow disabling all CPUs except the first one, | |
198 | * since this is special on a lot of platforms, e.g. because | |
199 | * of clock tick interrupts. | |
200 | */ | |
787047ee | 201 | return cpu != 0; |
abcee5fb | 202 | } |
787047ee | 203 | |
a054a811 RK |
204 | /* |
205 | * __cpu_disable runs on the processor to be shutdown. | |
206 | */ | |
8bd26e3a | 207 | int __cpu_disable(void) |
a054a811 RK |
208 | { |
209 | unsigned int cpu = smp_processor_id(); | |
a054a811 RK |
210 | int ret; |
211 | ||
8e2a43f5 | 212 | ret = platform_cpu_disable(cpu); |
a054a811 RK |
213 | if (ret) |
214 | return ret; | |
215 | ||
216 | /* | |
217 | * Take this CPU offline. Once we clear this, we can't return, | |
218 | * and we must not schedule until we're ready to give up the cpu. | |
219 | */ | |
e03cdade | 220 | set_cpu_online(cpu, false); |
a054a811 RK |
221 | |
222 | /* | |
223 | * OK - migrate IRQs away from this CPU | |
224 | */ | |
225 | migrate_irqs(); | |
226 | ||
227 | /* | |
228 | * Flush user cache and TLB mappings, and then remove this CPU | |
229 | * from the vm mask set of all processes. | |
e6b866e9 LP |
230 | * |
231 | * Caches are flushed to the Level of Unification Inner Shareable | |
232 | * to write-back dirty lines to unified caches shared by all CPUs. | |
a054a811 | 233 | */ |
e6b866e9 | 234 | flush_cache_louis(); |
a054a811 RK |
235 | local_flush_tlb_all(); |
236 | ||
3eaa73bd | 237 | clear_tasks_mm_cpumask(cpu); |
a054a811 RK |
238 | |
239 | return 0; | |
240 | } | |
241 | ||
3c030bea RK |
242 | static DECLARE_COMPLETION(cpu_died); |
243 | ||
a054a811 RK |
244 | /* |
245 | * called on the thread which is asking for a CPU to be shutdown - | |
246 | * waits until shutdown has completed, or it is timed out. | |
247 | */ | |
8bd26e3a | 248 | void __cpu_die(unsigned int cpu) |
a054a811 | 249 | { |
3c030bea RK |
250 | if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { |
251 | pr_err("CPU%u: cpu didn't die\n", cpu); | |
252 | return; | |
253 | } | |
4ed89f22 | 254 | pr_notice("CPU%u: shutdown\n", cpu); |
3c030bea | 255 | |
51acdfd1 RK |
256 | /* |
257 | * platform_cpu_kill() is generally expected to do the powering off | |
258 | * and/or cutting of clocks to the dying CPU. Optionally, this may | |
259 | * be done by the CPU which is dying in preference to supporting | |
260 | * this call, but that means there is _no_ synchronisation between | |
261 | * the requesting CPU and the dying CPU actually losing power. | |
262 | */ | |
a054a811 | 263 | if (!platform_cpu_kill(cpu)) |
4ed89f22 | 264 | pr_err("CPU%u: unable to kill\n", cpu); |
a054a811 RK |
265 | } |
266 | ||
267 | /* | |
268 | * Called from the idle thread for the CPU which has been shutdown. | |
269 | * | |
270 | * Note that we disable IRQs here, but do not re-enable them | |
271 | * before returning to the caller. This is also the behaviour | |
272 | * of the other hotplug-cpu capable cores, so presumably coming | |
273 | * out of idle fixes this. | |
274 | */ | |
9205b797 | 275 | void arch_cpu_idle_dead(void) |
a054a811 RK |
276 | { |
277 | unsigned int cpu = smp_processor_id(); | |
278 | ||
a054a811 RK |
279 | idle_task_exit(); |
280 | ||
f36d3401 | 281 | local_irq_disable(); |
f36d3401 | 282 | |
51acdfd1 RK |
283 | /* |
284 | * Flush the data out of the L1 cache for this CPU. This must be | |
285 | * before the completion to ensure that data is safely written out | |
286 | * before platform_cpu_kill() gets called - which may disable | |
287 | * *this* CPU and power down its cache. | |
288 | */ | |
289 | flush_cache_louis(); | |
290 | ||
291 | /* | |
292 | * Tell __cpu_die() that this CPU is now safe to dispose of. Once | |
293 | * this returns, power and/or clocks can be removed at any point | |
294 | * from this CPU and its cache by platform_cpu_kill(). | |
295 | */ | |
aa033810 | 296 | complete(&cpu_died); |
3c030bea | 297 | |
a054a811 | 298 | /* |
51acdfd1 RK |
299 | * Ensure that the cache lines associated with that completion are |
300 | * written out. This covers the case where _this_ CPU is doing the | |
301 | * powering down, to ensure that the completion is visible to the | |
302 | * CPU waiting for this one. | |
303 | */ | |
304 | flush_cache_louis(); | |
305 | ||
306 | /* | |
307 | * The actual CPU shutdown procedure is at least platform (if not | |
308 | * CPU) specific. This may remove power, or it may simply spin. | |
309 | * | |
310 | * Platforms are generally expected *NOT* to return from this call, | |
311 | * although there are some which do because they have no way to | |
312 | * power down the CPU. These platforms are the _only_ reason we | |
313 | * have a return path which uses the fragment of assembly below. | |
314 | * | |
315 | * The return path should not be used for platforms which can | |
316 | * power off the CPU. | |
a054a811 | 317 | */ |
0a301110 RK |
318 | if (smp_ops.cpu_die) |
319 | smp_ops.cpu_die(cpu); | |
a054a811 | 320 | |
668bc386 RK |
321 | pr_warn("CPU%u: smp_ops.cpu_die() returned, trying to resuscitate\n", |
322 | cpu); | |
323 | ||
a054a811 RK |
324 | /* |
325 | * Do not return to the idle loop - jump back to the secondary | |
326 | * cpu initialisation. There's some initialisation which needs | |
327 | * to be repeated to undo the effects of taking the CPU offline. | |
328 | */ | |
329 | __asm__("mov sp, %0\n" | |
faabfa08 | 330 | " mov fp, #0\n" |
a054a811 RK |
331 | " b secondary_start_kernel" |
332 | : | |
32d39a93 | 333 | : "r" (task_stack_page(current) + THREAD_SIZE - 8)); |
a054a811 RK |
334 | } |
335 | #endif /* CONFIG_HOTPLUG_CPU */ | |
336 | ||
05c74a6c RK |
337 | /* |
338 | * Called by both boot and secondaries to move global data into | |
339 | * per-processor storage. | |
340 | */ | |
8bd26e3a | 341 | static void smp_store_cpu_info(unsigned int cpuid) |
05c74a6c RK |
342 | { |
343 | struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); | |
344 | ||
345 | cpu_info->loops_per_jiffy = loops_per_jiffy; | |
e8d432c9 | 346 | cpu_info->cpuid = read_cpuid_id(); |
c9018aab VG |
347 | |
348 | store_cpu_topology(cpuid); | |
05c74a6c RK |
349 | } |
350 | ||
e65f38ed RK |
351 | /* |
352 | * This is the secondary CPU boot entry. We're using this CPUs | |
353 | * idle thread stack, but a set of temporary page tables. | |
354 | */ | |
8bd26e3a | 355 | asmlinkage void secondary_start_kernel(void) |
e65f38ed RK |
356 | { |
357 | struct mm_struct *mm = &init_mm; | |
5f40b909 WD |
358 | unsigned int cpu; |
359 | ||
360 | /* | |
361 | * The identity mapping is uncached (strongly ordered), so | |
362 | * switch away from it before attempting any exclusive accesses. | |
363 | */ | |
364 | cpu_switch_mm(mm->pgd, mm); | |
89c7e4b8 | 365 | local_flush_bp_all(); |
5f40b909 WD |
366 | enter_lazy_tlb(mm, current); |
367 | local_flush_tlb_all(); | |
e65f38ed | 368 | |
e65f38ed RK |
369 | /* |
370 | * All kernel threads share the same mm context; grab a | |
371 | * reference and switch to it. | |
372 | */ | |
5f40b909 | 373 | cpu = smp_processor_id(); |
e65f38ed RK |
374 | atomic_inc(&mm->mm_count); |
375 | current->active_mm = mm; | |
56f8ba83 | 376 | cpumask_set_cpu(cpu, mm_cpumask(mm)); |
e65f38ed | 377 | |
14318efb RH |
378 | cpu_init(); |
379 | ||
c68b0274 | 380 | pr_debug("CPU%u: Booted secondary processor\n", cpu); |
fde165b2 | 381 | |
5bfb5d69 | 382 | preempt_disable(); |
2c0136db | 383 | trace_hardirqs_off(); |
e65f38ed RK |
384 | |
385 | /* | |
386 | * Give the platform a chance to do its own initialisation. | |
387 | */ | |
0a301110 RK |
388 | if (smp_ops.smp_secondary_init) |
389 | smp_ops.smp_secondary_init(cpu); | |
e65f38ed | 390 | |
e545a614 | 391 | notify_cpu_starting(cpu); |
a8655e83 | 392 | |
e65f38ed RK |
393 | calibrate_delay(); |
394 | ||
395 | smp_store_cpu_info(cpu); | |
396 | ||
397 | /* | |
573619d1 RK |
398 | * OK, now it's safe to let the boot CPU continue. Wait for |
399 | * the CPU migration code to notice that the CPU is online | |
149c2415 | 400 | * before we continue - which happens after __cpu_up returns. |
e65f38ed | 401 | */ |
e03cdade | 402 | set_cpu_online(cpu, true); |
149c2415 | 403 | complete(&cpu_running); |
eb047454 | 404 | |
eb047454 TG |
405 | local_irq_enable(); |
406 | local_fiq_enable(); | |
bbeb9209 | 407 | local_abt_enable(); |
eb047454 | 408 | |
e65f38ed RK |
409 | /* |
410 | * OK, it's off to the idle thread for us | |
411 | */ | |
fc6d73d6 | 412 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
e65f38ed RK |
413 | } |
414 | ||
1da177e4 LT |
415 | void __init smp_cpus_done(unsigned int max_cpus) |
416 | { | |
4bf9636c PM |
417 | int cpu; |
418 | unsigned long bogosum = 0; | |
419 | ||
420 | for_each_online_cpu(cpu) | |
421 | bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy; | |
422 | ||
423 | printk(KERN_INFO "SMP: Total of %d processors activated " | |
424 | "(%lu.%02lu BogoMIPS).\n", | |
425 | num_online_cpus(), | |
426 | bogosum / (500000/HZ), | |
427 | (bogosum / (5000/HZ)) % 100); | |
428 | ||
4588c34d | 429 | hyp_mode_check(); |
1da177e4 LT |
430 | } |
431 | ||
432 | void __init smp_prepare_boot_cpu(void) | |
433 | { | |
14318efb | 434 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
1da177e4 LT |
435 | } |
436 | ||
05c74a6c | 437 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1da177e4 | 438 | { |
05c74a6c | 439 | unsigned int ncores = num_possible_cpus(); |
1da177e4 | 440 | |
c9018aab VG |
441 | init_cpu_topology(); |
442 | ||
05c74a6c | 443 | smp_store_cpu_info(smp_processor_id()); |
1da177e4 LT |
444 | |
445 | /* | |
05c74a6c | 446 | * are we trying to boot more cores than exist? |
1da177e4 | 447 | */ |
05c74a6c RK |
448 | if (max_cpus > ncores) |
449 | max_cpus = ncores; | |
7fa22bd5 | 450 | if (ncores > 1 && max_cpus) { |
7fa22bd5 SB |
451 | /* |
452 | * Initialise the present map, which describes the set of CPUs | |
453 | * actually populated at the present time. A platform should | |
0a301110 RK |
454 | * re-initialize the map in the platforms smp_prepare_cpus() |
455 | * if present != possible (e.g. physical hotplug). | |
7fa22bd5 | 456 | */ |
0b5f9c00 | 457 | init_cpu_present(cpu_possible_mask); |
7fa22bd5 | 458 | |
05c74a6c RK |
459 | /* |
460 | * Initialise the SCU if there are more than one CPU | |
461 | * and let them know where to start. | |
462 | */ | |
0a301110 RK |
463 | if (smp_ops.smp_prepare_cpus) |
464 | smp_ops.smp_prepare_cpus(max_cpus); | |
05c74a6c | 465 | } |
1da177e4 LT |
466 | } |
467 | ||
365ec7b1 | 468 | static void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
0f7b332f RK |
469 | |
470 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
471 | { | |
365ec7b1 NP |
472 | if (!__smp_cross_call) |
473 | __smp_cross_call = fn; | |
3e459990 | 474 | } |
3e459990 | 475 | |
365ec7b1 | 476 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
559a5939 SB |
477 | #define S(x,s) [x] = s |
478 | S(IPI_WAKEUP, "CPU wakeup interrupts"), | |
4a88abd7 RK |
479 | S(IPI_TIMER, "Timer broadcast interrupts"), |
480 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), | |
481 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
4a88abd7 | 482 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
bf18525f | 483 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5135d875 | 484 | S(IPI_COMPLETION, "completion interrupts"), |
4a88abd7 RK |
485 | }; |
486 | ||
365ec7b1 NP |
487 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
488 | { | |
489 | trace_ipi_raise(target, ipi_types[ipinr]); | |
490 | __smp_cross_call(target, ipinr); | |
491 | } | |
492 | ||
f13cd417 | 493 | void show_ipi_list(struct seq_file *p, int prec) |
1da177e4 | 494 | { |
4a88abd7 | 495 | unsigned int cpu, i; |
1da177e4 | 496 | |
4a88abd7 RK |
497 | for (i = 0; i < NR_IPI; i++) { |
498 | seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); | |
1da177e4 | 499 | |
026b7c6b | 500 | for_each_online_cpu(cpu) |
4a88abd7 RK |
501 | seq_printf(p, "%10u ", |
502 | __get_irq_stat(cpu, ipi_irqs[i])); | |
1da177e4 | 503 | |
4a88abd7 RK |
504 | seq_printf(p, " %s\n", ipi_types[i]); |
505 | } | |
1da177e4 LT |
506 | } |
507 | ||
b54992fe | 508 | u64 smp_irq_stat_cpu(unsigned int cpu) |
37ee16ae | 509 | { |
b54992fe RK |
510 | u64 sum = 0; |
511 | int i; | |
37ee16ae | 512 | |
b54992fe RK |
513 | for (i = 0; i < NR_IPI; i++) |
514 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
37ee16ae | 515 | |
b54992fe | 516 | return sum; |
37ee16ae RK |
517 | } |
518 | ||
365ec7b1 NP |
519 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
520 | { | |
521 | smp_cross_call(mask, IPI_CALL_FUNC); | |
522 | } | |
523 | ||
524 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
525 | { | |
526 | smp_cross_call(mask, IPI_WAKEUP); | |
527 | } | |
528 | ||
529 | void arch_send_call_function_single_ipi(int cpu) | |
530 | { | |
89d798b7 | 531 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
365ec7b1 NP |
532 | } |
533 | ||
534 | #ifdef CONFIG_IRQ_WORK | |
535 | void arch_irq_work_raise(void) | |
536 | { | |
09f6edd4 | 537 | if (arch_irq_work_has_interrupt()) |
365ec7b1 NP |
538 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); |
539 | } | |
540 | #endif | |
541 | ||
bc28248e | 542 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
3d06770e | 543 | void tick_broadcast(const struct cpumask *mask) |
bc28248e | 544 | { |
e3fbb087 | 545 | smp_cross_call(mask, IPI_TIMER); |
bc28248e | 546 | } |
5388a6b2 | 547 | #endif |
bc28248e | 548 | |
bd31b859 | 549 | static DEFINE_RAW_SPINLOCK(stop_lock); |
1da177e4 LT |
550 | |
551 | /* | |
552 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
553 | */ | |
554 | static void ipi_cpu_stop(unsigned int cpu) | |
555 | { | |
3d3f78d7 RK |
556 | if (system_state == SYSTEM_BOOTING || |
557 | system_state == SYSTEM_RUNNING) { | |
bd31b859 | 558 | raw_spin_lock(&stop_lock); |
4ed89f22 | 559 | pr_crit("CPU%u: stopping\n", cpu); |
3d3f78d7 | 560 | dump_stack(); |
bd31b859 | 561 | raw_spin_unlock(&stop_lock); |
3d3f78d7 | 562 | } |
1da177e4 | 563 | |
e03cdade | 564 | set_cpu_online(cpu, false); |
1da177e4 LT |
565 | |
566 | local_fiq_disable(); | |
567 | local_irq_disable(); | |
568 | ||
569 | while (1) | |
570 | cpu_relax(); | |
571 | } | |
572 | ||
5135d875 NP |
573 | static DEFINE_PER_CPU(struct completion *, cpu_completion); |
574 | ||
575 | int register_ipi_completion(struct completion *completion, int cpu) | |
576 | { | |
577 | per_cpu(cpu_completion, cpu) = completion; | |
578 | return IPI_COMPLETION; | |
579 | } | |
580 | ||
581 | static void ipi_complete(unsigned int cpu) | |
582 | { | |
583 | complete(per_cpu(cpu_completion, cpu)); | |
584 | } | |
585 | ||
1da177e4 LT |
586 | /* |
587 | * Main handler for inter-processor interrupts | |
1da177e4 | 588 | */ |
4073723a | 589 | asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) |
0b5a1b95 SG |
590 | { |
591 | handle_IPI(ipinr, regs); | |
592 | } | |
593 | ||
594 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
1da177e4 LT |
595 | { |
596 | unsigned int cpu = smp_processor_id(); | |
c97d4869 | 597 | struct pt_regs *old_regs = set_irq_regs(regs); |
1da177e4 | 598 | |
365ec7b1 | 599 | if ((unsigned)ipinr < NR_IPI) { |
398f7456 | 600 | trace_ipi_entry_rcuidle(ipi_types[ipinr]); |
559a5939 | 601 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
365ec7b1 | 602 | } |
1da177e4 | 603 | |
24480d98 | 604 | switch (ipinr) { |
559a5939 SB |
605 | case IPI_WAKEUP: |
606 | break; | |
607 | ||
e2c50119 | 608 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
24480d98 | 609 | case IPI_TIMER: |
7deabca0 | 610 | irq_enter(); |
e2c50119 | 611 | tick_receive_broadcast(); |
7deabca0 | 612 | irq_exit(); |
24480d98 | 613 | break; |
e2c50119 | 614 | #endif |
1da177e4 | 615 | |
24480d98 | 616 | case IPI_RESCHEDULE: |
184748cc | 617 | scheduler_ipi(); |
24480d98 | 618 | break; |
1da177e4 | 619 | |
24480d98 | 620 | case IPI_CALL_FUNC: |
7deabca0 | 621 | irq_enter(); |
24480d98 | 622 | generic_smp_call_function_interrupt(); |
7deabca0 | 623 | irq_exit(); |
24480d98 | 624 | break; |
1da177e4 | 625 | |
24480d98 | 626 | case IPI_CPU_STOP: |
7deabca0 | 627 | irq_enter(); |
24480d98 | 628 | ipi_cpu_stop(cpu); |
7deabca0 | 629 | irq_exit(); |
24480d98 | 630 | break; |
1da177e4 | 631 | |
bf18525f SB |
632 | #ifdef CONFIG_IRQ_WORK |
633 | case IPI_IRQ_WORK: | |
634 | irq_enter(); | |
635 | irq_work_run(); | |
636 | irq_exit(); | |
637 | break; | |
638 | #endif | |
639 | ||
5135d875 NP |
640 | case IPI_COMPLETION: |
641 | irq_enter(); | |
642 | ipi_complete(cpu); | |
643 | irq_exit(); | |
644 | break; | |
645 | ||
96f0e003 RK |
646 | case IPI_CPU_BACKTRACE: |
647 | irq_enter(); | |
648 | nmi_cpu_backtrace(regs); | |
649 | irq_exit(); | |
650 | break; | |
651 | ||
24480d98 | 652 | default: |
4ed89f22 RK |
653 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", |
654 | cpu, ipinr); | |
24480d98 | 655 | break; |
1da177e4 | 656 | } |
365ec7b1 NP |
657 | |
658 | if ((unsigned)ipinr < NR_IPI) | |
398f7456 | 659 | trace_ipi_exit_rcuidle(ipi_types[ipinr]); |
c97d4869 | 660 | set_irq_regs(old_regs); |
1da177e4 LT |
661 | } |
662 | ||
663 | void smp_send_reschedule(int cpu) | |
664 | { | |
e3fbb087 | 665 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); |
1da177e4 LT |
666 | } |
667 | ||
1da177e4 LT |
668 | void smp_send_stop(void) |
669 | { | |
28e18293 | 670 | unsigned long timeout; |
6fa99b7f | 671 | struct cpumask mask; |
1da177e4 | 672 | |
6fa99b7f WD |
673 | cpumask_copy(&mask, cpu_online_mask); |
674 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
c5dff4ff JMC |
675 | if (!cpumask_empty(&mask)) |
676 | smp_cross_call(&mask, IPI_CPU_STOP); | |
4b0ef3b1 | 677 | |
28e18293 RK |
678 | /* Wait up to one second for other CPUs to stop */ |
679 | timeout = USEC_PER_SEC; | |
680 | while (num_online_cpus() > 1 && timeout--) | |
681 | udelay(1); | |
4b0ef3b1 | 682 | |
28e18293 | 683 | if (num_online_cpus() > 1) |
8b521cb2 | 684 | pr_warn("SMP: failed to stop secondary CPUs\n"); |
4b0ef3b1 RK |
685 | } |
686 | ||
4b0ef3b1 | 687 | /* |
1da177e4 | 688 | * not supported here |
4b0ef3b1 | 689 | */ |
5048bcba | 690 | int setup_profiling_timer(unsigned int multiplier) |
4b0ef3b1 | 691 | { |
1da177e4 | 692 | return -EINVAL; |
4b0ef3b1 | 693 | } |
ec971ea5 RZ |
694 | |
695 | #ifdef CONFIG_CPU_FREQ | |
696 | ||
697 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref); | |
698 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq); | |
699 | static unsigned long global_l_p_j_ref; | |
700 | static unsigned long global_l_p_j_ref_freq; | |
701 | ||
702 | static int cpufreq_callback(struct notifier_block *nb, | |
703 | unsigned long val, void *data) | |
704 | { | |
705 | struct cpufreq_freqs *freq = data; | |
706 | int cpu = freq->cpu; | |
707 | ||
708 | if (freq->flags & CPUFREQ_CONST_LOOPS) | |
709 | return NOTIFY_OK; | |
710 | ||
711 | if (!per_cpu(l_p_j_ref, cpu)) { | |
712 | per_cpu(l_p_j_ref, cpu) = | |
713 | per_cpu(cpu_data, cpu).loops_per_jiffy; | |
714 | per_cpu(l_p_j_ref_freq, cpu) = freq->old; | |
715 | if (!global_l_p_j_ref) { | |
716 | global_l_p_j_ref = loops_per_jiffy; | |
717 | global_l_p_j_ref_freq = freq->old; | |
718 | } | |
719 | } | |
720 | ||
721 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 722 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
ec971ea5 RZ |
723 | loops_per_jiffy = cpufreq_scale(global_l_p_j_ref, |
724 | global_l_p_j_ref_freq, | |
725 | freq->new); | |
726 | per_cpu(cpu_data, cpu).loops_per_jiffy = | |
727 | cpufreq_scale(per_cpu(l_p_j_ref, cpu), | |
728 | per_cpu(l_p_j_ref_freq, cpu), | |
729 | freq->new); | |
730 | } | |
731 | return NOTIFY_OK; | |
732 | } | |
733 | ||
734 | static struct notifier_block cpufreq_notifier = { | |
735 | .notifier_call = cpufreq_callback, | |
736 | }; | |
737 | ||
738 | static int __init register_cpufreq_notifier(void) | |
739 | { | |
740 | return cpufreq_register_notifier(&cpufreq_notifier, | |
741 | CPUFREQ_TRANSITION_NOTIFIER); | |
742 | } | |
743 | core_initcall(register_cpufreq_notifier); | |
744 | ||
745 | #endif | |
96f0e003 RK |
746 | |
747 | static void raise_nmi(cpumask_t *mask) | |
748 | { | |
0768330d DT |
749 | /* |
750 | * Generate the backtrace directly if we are running in a calling | |
751 | * context that is not preemptible by the backtrace IPI. Note | |
752 | * that nmi_cpu_backtrace() automatically removes the current cpu | |
753 | * from mask. | |
754 | */ | |
755 | if (cpumask_test_cpu(smp_processor_id(), mask) && irqs_disabled()) | |
756 | nmi_cpu_backtrace(NULL); | |
757 | ||
96f0e003 RK |
758 | smp_cross_call(mask, IPI_CPU_BACKTRACE); |
759 | } | |
760 | ||
761 | void arch_trigger_all_cpu_backtrace(bool include_self) | |
762 | { | |
763 | nmi_trigger_all_cpu_backtrace(include_self, raise_nmi); | |
764 | } |