[deliverable/linux.git] / arch / arm / kernel / smp_twd.c

/*
 *  linux/arch/arm/kernel/smp_twd.c
 *
 *  Copyright (C) 2002 ARM Ltd.
 *  All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/jiffies.h>
#include <linux/clockchips.h>
#include <linux/irq.h>
#include <linux/io.h>

#include <asm/smp_twd.h>
#include <asm/localtimer.h>
#include <asm/hardware/gic.h>

/* set up by the platform code */
void __iomem *twd_base;

static unsigned long twd_timer_rate;

static struct clock_event_device __percpu **twd_evt;

static void twd_set_mode(enum clock_event_mode mode,
			struct clock_event_device *clk)
{
	unsigned long ctrl;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* timer load already set up */
		ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
			| TWD_TIMER_CONTROL_PERIODIC;
		__raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* period set, and timer enabled in 'next_event' hook */
		ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		ctrl = 0;
	}

	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
}

static int twd_set_next_event(unsigned long evt,
			struct clock_event_device *unused)
{
	unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);

	ctrl |= TWD_TIMER_CONTROL_ENABLE;

	__raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);

	return 0;
}

/*
 * local_timer_ack: checks for a local timer interrupt.
 *
 * If a local timer interrupt has occurred, acknowledge and return 1.
 * Otherwise, return 0.
 */
int twd_timer_ack(void)
{
	if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
		__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
		return 1;
	}

	return 0;
}

void twd_timer_stop(struct clock_event_device *clk)
{
	twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
	disable_percpu_irq(clk->irq);
}

static void __cpuinit twd_calibrate_rate(void)
{
	unsigned long count;
	u64 waitjiffies;

	/*
	 * If this is the first time round, we need to work out how fast
	 * the timer ticks
	 */
	if (twd_timer_rate == 0) {
		printk(KERN_INFO "Calibrating local timer... ");

		/* Wait for a tick to start */
		waitjiffies = get_jiffies_64() + 1;

		while (get_jiffies_64() < waitjiffies)
			udelay(10);

		/* OK, now the tick has started, let's get the timer going */
		waitjiffies += 5;

				 /* enable, no interrupt or reload */
		__raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);

				 /* maximum value */
		__raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);

		while (get_jiffies_64() < waitjiffies)
			udelay(10);

		count = __raw_readl(twd_base + TWD_TIMER_COUNTER);

		twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);

		printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
			(twd_timer_rate / 10000) % 100);
	}
}

static irqreturn_t twd_handler(int irq, void *dev_id)
{
	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;

	if (twd_timer_ack()) {
		evt->event_handler(evt);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

/*
 * Setup the local clock events for a CPU.
 */
void __cpuinit twd_timer_setup(struct clock_event_device *clk)
{
	struct clock_event_device **this_cpu_clk;

	if (!twd_evt) {
		int err;

		twd_evt = alloc_percpu(struct clock_event_device *);
		if (!twd_evt) {
			pr_err("twd: can't allocate memory\n");
			return;
		}

		err = request_percpu_irq(clk->irq, twd_handler,
					 "twd", twd_evt);
		if (err) {
			pr_err("twd: can't register interrupt %d (%d)\n",
			       clk->irq, err);
			return;
		}
	}

	twd_calibrate_rate();

	clk->name = "local_timer";
	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
			CLOCK_EVT_FEAT_C3STOP;
	clk->rating = 350;
	clk->set_mode = twd_set_mode;
	clk->set_next_event = twd_set_next_event;
	clk->shift = 20;
	clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift);
	clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
	clk->min_delta_ns = clockevent_delta2ns(0xf, clk);

	this_cpu_clk = __this_cpu_ptr(twd_evt);
	*this_cpu_clk = clk;

	clockevents_register_device(clk);

	enable_percpu_irq(clk->irq, 0);
}
Commit	Line	Data
f32f4ce2 RK	1	/*
	2	* linux/arch/arm/kernel/smp_twd.c
	3	*
	4	* Copyright (C) 2002 ARM Ltd.
	5	* All Rights Reserved
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/delay.h>
	14	#include <linux/device.h>
	15	#include <linux/smp.h>
	16	#include <linux/jiffies.h>
	17	#include <linux/clockchips.h>
	18	#include <linux/irq.h>
	19	#include <linux/io.h>
	20
	21	#include <asm/smp_twd.h>
28af690a	22	#include <asm/localtimer.h>
f32f4ce2 RK	23	#include <asm/hardware/gic.h>
f32f4ce2 RK	24
f32f4ce2 RK	25	/* set up by the platform code */
	26	void __iomem *twd_base;
	27
	28	static unsigned long twd_timer_rate;
	29
28af690a MZ	30	static struct clock_event_device __percpu **twd_evt;
28af690a MZ	31
f32f4ce2 RK	32	static void twd_set_mode(enum clock_event_mode mode,
	33	struct clock_event_device *clk)
	34	{
	35	unsigned long ctrl;
	36
4c5158d4	37	switch (mode) {
f32f4ce2 RK	38	case CLOCK_EVT_MODE_PERIODIC:
	39	/* timer load already set up */
	40	ctrl = TWD_TIMER_CONTROL_ENABLE \| TWD_TIMER_CONTROL_IT_ENABLE
	41	\| TWD_TIMER_CONTROL_PERIODIC;
03399c1c	42	__raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
f32f4ce2 RK	43	break;
	44	case CLOCK_EVT_MODE_ONESHOT:
	45	/* period set, and timer enabled in 'next_event' hook */
	46	ctrl = TWD_TIMER_CONTROL_IT_ENABLE \| TWD_TIMER_CONTROL_ONESHOT;
	47	break;
	48	case CLOCK_EVT_MODE_UNUSED:
	49	case CLOCK_EVT_MODE_SHUTDOWN:
	50	default:
	51	ctrl = 0;
	52	}
	53
	54	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
	55	}
	56
	57	static int twd_set_next_event(unsigned long evt,
	58	struct clock_event_device *unused)
	59	{
	60	unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
	61
4c5158d4 RK	62	ctrl \|= TWD_TIMER_CONTROL_ENABLE;
4c5158d4 RK	63
f32f4ce2	64	__raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
4c5158d4	65	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
f32f4ce2 RK	66
	67	return 0;
	68	}
	69
	70	/*
	71	* local_timer_ack: checks for a local timer interrupt.
	72	*
	73	* If a local timer interrupt has occurred, acknowledge and return 1.
	74	* Otherwise, return 0.
	75	*/
	76	int twd_timer_ack(void)
	77	{
	78	if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
	79	__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
	80	return 1;
	81	}
	82
	83	return 0;
	84	}
	85
28af690a MZ	86	void twd_timer_stop(struct clock_event_device *clk)
	87	{
	88	twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
	89	disable_percpu_irq(clk->irq);
	90	}
	91
f32f4ce2 RK	92	static void __cpuinit twd_calibrate_rate(void)
f32f4ce2 RK	93	{
03399c1c	94	unsigned long count;
f32f4ce2 RK	95	u64 waitjiffies;
	96
	97	/*
	98	* If this is the first time round, we need to work out how fast
	99	* the timer ticks
	100	*/
	101	if (twd_timer_rate == 0) {
4c5158d4	102	printk(KERN_INFO "Calibrating local timer... ");
f32f4ce2 RK	103
	104	/* Wait for a tick to start */
	105	waitjiffies = get_jiffies_64() + 1;
	106
	107	while (get_jiffies_64() < waitjiffies)
	108	udelay(10);
	109
	110	/* OK, now the tick has started, let's get the timer going */
	111	waitjiffies += 5;
	112
	113	/* enable, no interrupt or reload */
	114	__raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
	115
	116	/* maximum value */
	117	__raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
	118
	119	while (get_jiffies_64() < waitjiffies)
	120	udelay(10);
	121
	122	count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
	123
	124	twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
	125
	126	printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
90c5ffe5	127	(twd_timer_rate / 10000) % 100);
f32f4ce2	128	}
f32f4ce2 RK	129	}
f32f4ce2 RK	130
28af690a MZ	131	static irqreturn_t twd_handler(int irq, void *dev_id)
	132	{
	133	struct clock_event_device evt = (struct clock_event_device **)dev_id;
	134
	135	if (twd_timer_ack()) {
	136	evt->event_handler(evt);
	137	return IRQ_HANDLED;
	138	}
	139
	140	return IRQ_NONE;
	141	}
	142
f32f4ce2 RK	143	/*
	144	* Setup the local clock events for a CPU.
	145	*/
	146	void __cpuinit twd_timer_setup(struct clock_event_device *clk)
	147	{
28af690a MZ	148	struct clock_event_device **this_cpu_clk;
	149
	150	if (!twd_evt) {
	151	int err;
	152
	153	twd_evt = alloc_percpu(struct clock_event_device *);
	154	if (!twd_evt) {
	155	pr_err("twd: can't allocate memory\n");
	156	return;
	157	}
	158
	159	err = request_percpu_irq(clk->irq, twd_handler,
	160	"twd", twd_evt);
	161	if (err) {
	162	pr_err("twd: can't register interrupt %d (%d)\n",
	163	clk->irq, err);
	164	return;
	165	}
	166	}
	167
f32f4ce2 RK	168	twd_calibrate_rate();
f32f4ce2 RK	169
4c5158d4	170	clk->name = "local_timer";
5388a6b2 RK	171	clk->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT \|
5388a6b2 RK	172	CLOCK_EVT_FEAT_C3STOP;
4c5158d4 RK	173	clk->rating = 350;
	174	clk->set_mode = twd_set_mode;
	175	clk->set_next_event = twd_set_next_event;
	176	clk->shift = 20;
	177	clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift);
	178	clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
	179	clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
f32f4ce2	180
28af690a MZ	181	this_cpu_clk = __this_cpu_ptr(twd_evt);
	182	*this_cpu_clk = clk;
	183
dfc40b24 WD	184	clockevents_register_device(clk);
dfc40b24 WD	185
28af690a	186	enable_percpu_irq(clk->irq, 0);
f32f4ce2	187	}