Commit | Line | Data |
---|---|---|
e8ce0eb5 | 1 | #include <linux/init.h> |
7604537b | 2 | #include <linux/slab.h> |
e8ce0eb5 | 3 | |
7604537b | 4 | #include <asm/cacheflush.h> |
e6eadc67 | 5 | #include <asm/idmap.h> |
e8ce0eb5 RK |
6 | #include <asm/pgalloc.h> |
7 | #include <asm/pgtable.h> | |
8 | #include <asm/memory.h> | |
7604537b | 9 | #include <asm/smp_plat.h> |
e8ce0eb5 RK |
10 | #include <asm/suspend.h> |
11 | #include <asm/tlbflush.h> | |
12 | ||
abda1bd5 | 13 | extern int __cpu_suspend(unsigned long, int (*)(unsigned long)); |
62b2d07c | 14 | extern void cpu_resume_mmu(void); |
e8ce0eb5 | 15 | |
aa1aadc3 WD |
16 | #ifdef CONFIG_MMU |
17 | /* | |
18 | * Hide the first two arguments to __cpu_suspend - these are an implementation | |
19 | * detail which platform code shouldn't have to know about. | |
20 | */ | |
21 | int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) | |
22 | { | |
23 | struct mm_struct *mm = current->active_mm; | |
24 | int ret; | |
25 | ||
26 | if (!idmap_pgd) | |
27 | return -EINVAL; | |
28 | ||
29 | /* | |
30 | * Provide a temporary page table with an identity mapping for | |
31 | * the MMU-enable code, required for resuming. On successful | |
32 | * resume (indicated by a zero return code), we need to switch | |
33 | * back to the correct page tables. | |
34 | */ | |
35 | ret = __cpu_suspend(arg, fn); | |
36 | if (ret == 0) { | |
37 | cpu_switch_mm(mm->pgd, mm); | |
38 | local_flush_bp_all(); | |
39 | local_flush_tlb_all(); | |
40 | } | |
41 | ||
42 | return ret; | |
43 | } | |
44 | #else | |
45 | int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) | |
46 | { | |
47 | return __cpu_suspend(arg, fn); | |
48 | } | |
49 | #define idmap_pgd NULL | |
50 | #endif | |
51 | ||
abda1bd5 RK |
52 | /* |
53 | * This is called by __cpu_suspend() to save the state, and do whatever | |
54 | * flushing is required to ensure that when the CPU goes to sleep we have | |
55 | * the necessary data available when the caches are not searched. | |
56 | */ | |
57 | void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr) | |
58 | { | |
dbee0c6f LP |
59 | u32 *ctx = ptr; |
60 | ||
abda1bd5 RK |
61 | *save_ptr = virt_to_phys(ptr); |
62 | ||
63 | /* This must correspond to the LDM in cpu_resume() assembly */ | |
e6eadc67 | 64 | *ptr++ = virt_to_phys(idmap_pgd); |
abda1bd5 RK |
65 | *ptr++ = sp; |
66 | *ptr++ = virt_to_phys(cpu_do_resume); | |
67 | ||
68 | cpu_do_suspend(ptr); | |
69 | ||
dbee0c6f LP |
70 | flush_cache_louis(); |
71 | ||
72 | /* | |
73 | * flush_cache_louis does not guarantee that | |
74 | * save_ptr and ptr are cleaned to main memory, | |
75 | * just up to the Level of Unification Inner Shareable. | |
76 | * Since the context pointer and context itself | |
77 | * are to be retrieved with the MMU off that | |
78 | * data must be cleaned from all cache levels | |
79 | * to main memory using "area" cache primitives. | |
80 | */ | |
81 | __cpuc_flush_dcache_area(ctx, ptrsz); | |
82 | __cpuc_flush_dcache_area(save_ptr, sizeof(*save_ptr)); | |
83 | ||
8e6f83bb RK |
84 | outer_clean_range(*save_ptr, *save_ptr + ptrsz); |
85 | outer_clean_range(virt_to_phys(save_ptr), | |
86 | virt_to_phys(save_ptr) + sizeof(*save_ptr)); | |
abda1bd5 | 87 | } |
7604537b LP |
88 | |
89 | extern struct sleep_save_sp sleep_save_sp; | |
90 | ||
91 | static int cpu_suspend_alloc_sp(void) | |
92 | { | |
93 | void *ctx_ptr; | |
94 | /* ctx_ptr is an array of physical addresses */ | |
95 | ctx_ptr = kcalloc(mpidr_hash_size(), sizeof(u32), GFP_KERNEL); | |
96 | ||
97 | if (WARN_ON(!ctx_ptr)) | |
98 | return -ENOMEM; | |
99 | sleep_save_sp.save_ptr_stash = ctx_ptr; | |
100 | sleep_save_sp.save_ptr_stash_phys = virt_to_phys(ctx_ptr); | |
101 | sync_cache_w(&sleep_save_sp); | |
102 | return 0; | |
103 | } | |
104 | early_initcall(cpu_suspend_alloc_sp); |