Commit | Line | Data |
---|---|---|
e8ce0eb5 | 1 | #include <linux/init.h> |
7604537b | 2 | #include <linux/slab.h> |
e8ce0eb5 | 3 | |
7604537b | 4 | #include <asm/cacheflush.h> |
e6eadc67 | 5 | #include <asm/idmap.h> |
e8ce0eb5 RK |
6 | #include <asm/pgalloc.h> |
7 | #include <asm/pgtable.h> | |
8 | #include <asm/memory.h> | |
7604537b | 9 | #include <asm/smp_plat.h> |
e8ce0eb5 RK |
10 | #include <asm/suspend.h> |
11 | #include <asm/tlbflush.h> | |
12 | ||
71a8986d | 13 | extern int __cpu_suspend(unsigned long, int (*)(unsigned long), u32 cpuid); |
62b2d07c | 14 | extern void cpu_resume_mmu(void); |
e8ce0eb5 | 15 | |
aa1aadc3 | 16 | #ifdef CONFIG_MMU |
aa1aadc3 WD |
17 | int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) |
18 | { | |
19 | struct mm_struct *mm = current->active_mm; | |
71a8986d | 20 | u32 __mpidr = cpu_logical_map(smp_processor_id()); |
aa1aadc3 WD |
21 | int ret; |
22 | ||
23 | if (!idmap_pgd) | |
24 | return -EINVAL; | |
25 | ||
26 | /* | |
27 | * Provide a temporary page table with an identity mapping for | |
28 | * the MMU-enable code, required for resuming. On successful | |
29 | * resume (indicated by a zero return code), we need to switch | |
30 | * back to the correct page tables. | |
31 | */ | |
71a8986d | 32 | ret = __cpu_suspend(arg, fn, __mpidr); |
aa1aadc3 WD |
33 | if (ret == 0) { |
34 | cpu_switch_mm(mm->pgd, mm); | |
35 | local_flush_bp_all(); | |
36 | local_flush_tlb_all(); | |
37 | } | |
38 | ||
39 | return ret; | |
40 | } | |
41 | #else | |
42 | int cpu_suspend(unsigned long arg, int (*fn)(unsigned long)) | |
43 | { | |
71a8986d NP |
44 | u32 __mpidr = cpu_logical_map(smp_processor_id()); |
45 | return __cpu_suspend(arg, fn, __mpidr); | |
aa1aadc3 WD |
46 | } |
47 | #define idmap_pgd NULL | |
48 | #endif | |
49 | ||
abda1bd5 RK |
50 | /* |
51 | * This is called by __cpu_suspend() to save the state, and do whatever | |
52 | * flushing is required to ensure that when the CPU goes to sleep we have | |
53 | * the necessary data available when the caches are not searched. | |
54 | */ | |
55 | void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr) | |
56 | { | |
dbee0c6f LP |
57 | u32 *ctx = ptr; |
58 | ||
abda1bd5 RK |
59 | *save_ptr = virt_to_phys(ptr); |
60 | ||
61 | /* This must correspond to the LDM in cpu_resume() assembly */ | |
e6eadc67 | 62 | *ptr++ = virt_to_phys(idmap_pgd); |
abda1bd5 RK |
63 | *ptr++ = sp; |
64 | *ptr++ = virt_to_phys(cpu_do_resume); | |
65 | ||
66 | cpu_do_suspend(ptr); | |
67 | ||
dbee0c6f LP |
68 | flush_cache_louis(); |
69 | ||
70 | /* | |
71 | * flush_cache_louis does not guarantee that | |
72 | * save_ptr and ptr are cleaned to main memory, | |
73 | * just up to the Level of Unification Inner Shareable. | |
74 | * Since the context pointer and context itself | |
75 | * are to be retrieved with the MMU off that | |
76 | * data must be cleaned from all cache levels | |
77 | * to main memory using "area" cache primitives. | |
78 | */ | |
79 | __cpuc_flush_dcache_area(ctx, ptrsz); | |
80 | __cpuc_flush_dcache_area(save_ptr, sizeof(*save_ptr)); | |
81 | ||
8e6f83bb RK |
82 | outer_clean_range(*save_ptr, *save_ptr + ptrsz); |
83 | outer_clean_range(virt_to_phys(save_ptr), | |
84 | virt_to_phys(save_ptr) + sizeof(*save_ptr)); | |
abda1bd5 | 85 | } |
7604537b LP |
86 | |
87 | extern struct sleep_save_sp sleep_save_sp; | |
88 | ||
89 | static int cpu_suspend_alloc_sp(void) | |
90 | { | |
91 | void *ctx_ptr; | |
92 | /* ctx_ptr is an array of physical addresses */ | |
93 | ctx_ptr = kcalloc(mpidr_hash_size(), sizeof(u32), GFP_KERNEL); | |
94 | ||
95 | if (WARN_ON(!ctx_ptr)) | |
96 | return -ENOMEM; | |
97 | sleep_save_sp.save_ptr_stash = ctx_ptr; | |
98 | sleep_save_sp.save_ptr_stash_phys = virt_to_phys(ctx_ptr); | |
99 | sync_cache_w(&sleep_save_sp); | |
100 | return 0; | |
101 | } | |
102 | early_initcall(cpu_suspend_alloc_sp); |