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Merge remote-tracking branch 'spi/fix/s3c64xx' into spi-linus
[deliverable/linux.git] / arch / arm / kvm / coproc.c
CommitLineData
749cf76c
CD		 1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Authors: Rusty Russell <rusty@rustcorp.com.au>
4 * Christoffer Dall <c.dall@virtualopensystems.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 */
5b3e5e5b 19#include <linux/mm.h>
749cf76c 20#include <linux/kvm_host.h>
1138245c 21#include <linux/uaccess.h>
5b3e5e5b
CD		 22#include <asm/kvm_arm.h>
23#include <asm/kvm_host.h>
24#include <asm/kvm_emulate.h>
25#include <asm/kvm_coproc.h>
26#include <asm/cacheflush.h>
27#include <asm/cputype.h>
28#include <trace/events/kvm.h>
4fe21e4c
RR		 29#include <asm/vfp.h>
30#include "../vfp/vfpinstr.h"
749cf76c 31
5b3e5e5b
CD		 32#include "trace.h"
33#include "coproc.h"
34
35
36/******************************************************************************
37 * Co-processor emulation
38 *****************************************************************************/
39
c27581ed
CD		 40/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
41static u32 cache_levels;
42
43/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
44#define CSSELR_MAX 12
45
5b3e5e5b
CD		 46int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
47{
48 kvm_inject_undefined(vcpu);
49 return 1;
50}
51
52int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
53{
54 /*
55 * We can get here, if the host has been built without VFPv3 support,
56 * but the guest attempted a floating point operation.
57 */
58 kvm_inject_undefined(vcpu);
59 return 1;
60}
61
62int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
63{
64 kvm_inject_undefined(vcpu);
65 return 1;
66}
67
68int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
69{
70 kvm_inject_undefined(vcpu);
71 return 1;
72}
73
74/* See note at ARM ARM B1.14.4 */
75static bool access_dcsw(struct kvm_vcpu *vcpu,
76 const struct coproc_params *p,
77 const struct coproc_reg *r)
78{
db730d8d 79 unsigned long val;
5b3e5e5b
CD		 80 int cpu;
81
5b3e5e5b
CD		 82 if (!p->is_write)
83 return read_from_write_only(vcpu, p);
84
15bbc1b2
MZ		 85 cpu = get_cpu();
86
5b3e5e5b
CD		 87 cpumask_setall(&vcpu->arch.require_dcache_flush);
88 cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
89
90 /* If we were already preempted, take the long way around */
91 if (cpu != vcpu->arch.last_pcpu) {
92 flush_cache_all();
93 goto done;
94 }
95
96 val = *vcpu_reg(vcpu, p->Rt1);
97
98 switch (p->CRm) {
99 case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
100 case 14: /* DCCISW */
101 asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
102 break;
103
104 case 10: /* DCCSW */
105 asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
106 break;
107 }
108
109done:
110 put_cpu();
111
112 return true;
113}
114
115/*
116 * We could trap ID_DFR0 and tell the guest we don't support performance
117 * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
118 * NAKed, so it will read the PMCR anyway.
119 *
120 * Therefore we tell the guest we have 0 counters. Unfortunately, we
121 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
122 * all PM registers, which doesn't crash the guest kernel at least.
123 */
124static bool pm_fake(struct kvm_vcpu *vcpu,
125 const struct coproc_params *p,
126 const struct coproc_reg *r)
127{
128 if (p->is_write)
129 return ignore_write(vcpu, p);
130 else
131 return read_zero(vcpu, p);
132}
133
134#define access_pmcr pm_fake
135#define access_pmcntenset pm_fake
136#define access_pmcntenclr pm_fake
137#define access_pmovsr pm_fake
138#define access_pmselr pm_fake
139#define access_pmceid0 pm_fake
140#define access_pmceid1 pm_fake
141#define access_pmccntr pm_fake
142#define access_pmxevtyper pm_fake
143#define access_pmxevcntr pm_fake
144#define access_pmuserenr pm_fake
145#define access_pmintenset pm_fake
146#define access_pmintenclr pm_fake
147
148/* Architected CP15 registers.
149 * Important: Must be sorted ascending by CRn, CRM, Op1, Op2
150 */
151static const struct coproc_reg cp15_regs[] = {
152 /* CSSELR: swapped by interrupt.S. */
153 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
154 NULL, reset_unknown, c0_CSSELR },
155
156 /* TTBR0/TTBR1: swapped by interrupt.S. */
157 { CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
158 { CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
159
160 /* TTBCR: swapped by interrupt.S. */
161 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
162 NULL, reset_val, c2_TTBCR, 0x00000000 },
163
164 /* DACR: swapped by interrupt.S. */
165 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
166 NULL, reset_unknown, c3_DACR },
167
168 /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
169 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
170 NULL, reset_unknown, c5_DFSR },
171 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
172 NULL, reset_unknown, c5_IFSR },
173 { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
174 NULL, reset_unknown, c5_ADFSR },
175 { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
176 NULL, reset_unknown, c5_AIFSR },
177
178 /* DFAR/IFAR: swapped by interrupt.S. */
179 { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
180 NULL, reset_unknown, c6_DFAR },
181 { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
182 NULL, reset_unknown, c6_IFAR },
6a077e4a
MZ		 183
184 /* PAR swapped by interrupt.S */
185 { CRn( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
186
5b3e5e5b
CD		 187 /*
188 * DC{C,I,CI}SW operations:
189 */
190 { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
191 { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
192 { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
193 /*
194 * Dummy performance monitor implementation.
195 */
196 { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
197 { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
198 { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
199 { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
200 { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
201 { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
202 { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
203 { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
204 { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
205 { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
206 { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
207 { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
208 { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
209
210 /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
211 { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
212 NULL, reset_unknown, c10_PRRR},
213 { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
214 NULL, reset_unknown, c10_NMRR},
215
216 /* VBAR: swapped by interrupt.S. */
217 { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
218 NULL, reset_val, c12_VBAR, 0x00000000 },
219
220 /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
221 { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
222 NULL, reset_val, c13_CID, 0x00000000 },
223 { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
224 NULL, reset_unknown, c13_TID_URW },
225 { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
226 NULL, reset_unknown, c13_TID_URO },
227 { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
228 NULL, reset_unknown, c13_TID_PRIV },
c7e3ba64
MZ		 229
230 /* CNTKCTL: swapped by interrupt.S. */
231 { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
232 NULL, reset_val, c14_CNTKCTL, 0x00000000 },
5b3e5e5b
CD		 233};
234
235/* Target specific emulation tables */
236static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
237
238void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
239{
240 target_tables[table->target] = table;
241}
242
243/* Get specific register table for this target. */
244static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
245{
246 struct kvm_coproc_target_table *table;
247
248 table = target_tables[target];
249 *num = table->num;
250 return table->table;
251}
252
253static const struct coproc_reg *find_reg(const struct coproc_params *params,
254 const struct coproc_reg table[],
255 unsigned int num)
256{
257 unsigned int i;
258
259 for (i = 0; i < num; i++) {
260 const struct coproc_reg *r = &table[i];
261
262 if (params->is_64bit != r->is_64)
263 continue;
264 if (params->CRn != r->CRn)
265 continue;
266 if (params->CRm != r->CRm)
267 continue;
268 if (params->Op1 != r->Op1)
269 continue;
270 if (params->Op2 != r->Op2)
271 continue;
272
273 return r;
274 }
275 return NULL;
276}
277
278static int emulate_cp15(struct kvm_vcpu *vcpu,
279 const struct coproc_params *params)
280{
281 size_t num;
282 const struct coproc_reg *table, *r;
283
284 trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
285 params->CRm, params->Op2, params->is_write);
286
287 table = get_target_table(vcpu->arch.target, &num);
288
289 /* Search target-specific then generic table. */
290 r = find_reg(params, table, num);
291 if (!r)
292 r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
293
294 if (likely(r)) {
295 /* If we don't have an accessor, we should never get here! */
296 BUG_ON(!r->access);
297
298 if (likely(r->access(vcpu, params, r))) {
299 /* Skip instruction, since it was emulated */
23b415d6 300 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
5b3e5e5b
CD		 301 return 1;
302 }
303 /* If access function fails, it should complain. */
304 } else {
db730d8d 305 kvm_err("Unsupported guest CP15 access at: %08lx\n",
5b3e5e5b
CD		 306 *vcpu_pc(vcpu));
307 print_cp_instr(params);
308 }
309 kvm_inject_undefined(vcpu);
310 return 1;
311}
312
313/**
314 * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
315 * @vcpu: The VCPU pointer
316 * @run: The kvm_run struct
317 */
318int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
319{
320 struct coproc_params params;
321
7393b599
MZ		 322 params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
323 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
324 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
5b3e5e5b
CD		 325 params.is_64bit = true;
326
7393b599 327 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
5b3e5e5b 328 params.Op2 = 0;
7393b599 329 params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
5b3e5e5b
CD		 330 params.CRn = 0;
331
332 return emulate_cp15(vcpu, &params);
333}
334
335static void reset_coproc_regs(struct kvm_vcpu *vcpu,
336 const struct coproc_reg *table, size_t num)
337{
338 unsigned long i;
339
340 for (i = 0; i < num; i++)
341 if (table[i].reset)
342 table[i].reset(vcpu, &table[i]);
343}
344
345/**
346 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
347 * @vcpu: The VCPU pointer
348 * @run: The kvm_run struct
349 */
350int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
351{
352 struct coproc_params params;
353
7393b599
MZ		 354 params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
355 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
356 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
5b3e5e5b
CD		 357 params.is_64bit = false;
358
7393b599
MZ		 359 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
360 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
361 params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
5b3e5e5b
CD		 362 params.Rt2 = 0;
363
364 return emulate_cp15(vcpu, &params);
365}
366
1138245c
CD		 367/******************************************************************************
368 * Userspace API
369 *****************************************************************************/
370
371static bool index_to_params(u64 id, struct coproc_params *params)
372{
373 switch (id & KVM_REG_SIZE_MASK) {
374 case KVM_REG_SIZE_U32:
375 /* Any unused index bits means it's not valid. */
376 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
377 | KVM_REG_ARM_COPROC_MASK
378 | KVM_REG_ARM_32_CRN_MASK
379 | KVM_REG_ARM_CRM_MASK
380 | KVM_REG_ARM_OPC1_MASK
381 | KVM_REG_ARM_32_OPC2_MASK))
382 return false;
383
384 params->is_64bit = false;
385 params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
386 >> KVM_REG_ARM_32_CRN_SHIFT);
387 params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
388 >> KVM_REG_ARM_CRM_SHIFT);
389 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
390 >> KVM_REG_ARM_OPC1_SHIFT);
391 params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
392 >> KVM_REG_ARM_32_OPC2_SHIFT);
393 return true;
394 case KVM_REG_SIZE_U64:
395 /* Any unused index bits means it's not valid. */
396 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
397 | KVM_REG_ARM_COPROC_MASK
398 | KVM_REG_ARM_CRM_MASK
399 | KVM_REG_ARM_OPC1_MASK))
400 return false;
401 params->is_64bit = true;
402 params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
403 >> KVM_REG_ARM_CRM_SHIFT);
404 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
405 >> KVM_REG_ARM_OPC1_SHIFT);
406 params->Op2 = 0;
407 params->CRn = 0;
408 return true;
409 default:
410 return false;
411 }
412}
413
414/* Decode an index value, and find the cp15 coproc_reg entry. */
415static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
416 u64 id)
417{
418 size_t num;
419 const struct coproc_reg *table, *r;
420 struct coproc_params params;
421
422 /* We only do cp15 for now. */
423 if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
424 return NULL;
425
426 if (!index_to_params(id, &params))
427 return NULL;
428
429 table = get_target_table(vcpu->arch.target, &num);
430 r = find_reg(&params, table, num);
431 if (!r)
432 r = find_reg(&params, cp15_regs, ARRAY_SIZE(cp15_regs));
433
434 /* Not saved in the cp15 array? */
435 if (r && !r->reg)
436 r = NULL;
437
438 return r;
439}
440
441/*
442 * These are the invariant cp15 registers: we let the guest see the host
443 * versions of these, so they're part of the guest state.
444 *
445 * A future CPU may provide a mechanism to present different values to
446 * the guest, or a future kvm may trap them.
447 */
448/* Unfortunately, there's no register-argument for mrc, so generate. */
449#define FUNCTION_FOR32(crn, crm, op1, op2, name) \
450 static void get_##name(struct kvm_vcpu *v, \
451 const struct coproc_reg *r) \
452 { \
453 u32 val; \
454 \
455 asm volatile("mrc p15, " __stringify(op1) \
456 ", %0, c" __stringify(crn) \
457 ", c" __stringify(crm) \
458 ", " __stringify(op2) "\n" : "=r" (val)); \
459 ((struct coproc_reg *)r)->val = val; \
460 }
461
462FUNCTION_FOR32(0, 0, 0, 0, MIDR)
463FUNCTION_FOR32(0, 0, 0, 1, CTR)
464FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
465FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
466FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
467FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
468FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
469FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
470FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
471FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
472FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
473FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
474FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
475FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
476FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
477FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
478FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
479FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
480FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
481FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
482FUNCTION_FOR32(0, 0, 1, 7, AIDR)
483
484/* ->val is filled in by kvm_invariant_coproc_table_init() */
485static struct coproc_reg invariant_cp15[] = {
486 { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
487 { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
488 { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
489 { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
490 { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
491
492 { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
493 { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
494 { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
495 { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
496 { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
497 { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
498 { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
499 { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
500
501 { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
502 { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
503 { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
504 { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
505 { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
506 { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
507
508 { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
509 { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
510};
511
512static int reg_from_user(void *val, const void __user *uaddr, u64 id)
513{
514 /* This Just Works because we are little endian. */
515 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
516 return -EFAULT;
517 return 0;
518}
519
520static int reg_to_user(void __user *uaddr, const void *val, u64 id)
521{
522 /* This Just Works because we are little endian. */
523 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
524 return -EFAULT;
525 return 0;
526}
527
528static int get_invariant_cp15(u64 id, void __user *uaddr)
529{
530 struct coproc_params params;
531 const struct coproc_reg *r;
532
533 if (!index_to_params(id, &params))
534 return -ENOENT;
535
536 r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
537 if (!r)
538 return -ENOENT;
539
540 return reg_to_user(uaddr, &r->val, id);
541}
542
543static int set_invariant_cp15(u64 id, void __user *uaddr)
544{
545 struct coproc_params params;
546 const struct coproc_reg *r;
547 int err;
548 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
549
550 if (!index_to_params(id, &params))
551 return -ENOENT;
552 r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
553 if (!r)
554 return -ENOENT;
555
556 err = reg_from_user(&val, uaddr, id);
557 if (err)
558 return err;
559
560 /* This is what we mean by invariant: you can't change it. */
561 if (r->val != val)
562 return -EINVAL;
563
564 return 0;
565}
566
c27581ed
CD		 567static bool is_valid_cache(u32 val)
568{
569 u32 level, ctype;
570
571 if (val >= CSSELR_MAX)
572 return -ENOENT;
573
574 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
575 level = (val >> 1);
576 ctype = (cache_levels >> (level * 3)) & 7;
577
578 switch (ctype) {
579 case 0: /* No cache */
580 return false;
581 case 1: /* Instruction cache only */
582 return (val & 1);
583 case 2: /* Data cache only */
584 case 4: /* Unified cache */
585 return !(val & 1);
586 case 3: /* Separate instruction and data caches */
587 return true;
588 default: /* Reserved: we can't know instruction or data. */
589 return false;
590 }
591}
592
593/* Which cache CCSIDR represents depends on CSSELR value. */
594static u32 get_ccsidr(u32 csselr)
595{
596 u32 ccsidr;
597
598 /* Make sure noone else changes CSSELR during this! */
599 local_irq_disable();
600 /* Put value into CSSELR */
601 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
602 isb();
603 /* Read result out of CCSIDR */
604 asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
605 local_irq_enable();
606
607 return ccsidr;
608}
609
610static int demux_c15_get(u64 id, void __user *uaddr)
611{
612 u32 val;
613 u32 __user *uval = uaddr;
614
615 /* Fail if we have unknown bits set. */
616 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
617 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
618 return -ENOENT;
619
620 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
621 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
622 if (KVM_REG_SIZE(id) != 4)
623 return -ENOENT;
624 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
625 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
626 if (!is_valid_cache(val))
627 return -ENOENT;
628
629 return put_user(get_ccsidr(val), uval);
630 default:
631 return -ENOENT;
632 }
633}
634
635static int demux_c15_set(u64 id, void __user *uaddr)
636{
637 u32 val, newval;
638 u32 __user *uval = uaddr;
639
640 /* Fail if we have unknown bits set. */
641 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
642 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
643 return -ENOENT;
644
645 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
646 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
647 if (KVM_REG_SIZE(id) != 4)
648 return -ENOENT;
649 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
650 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
651 if (!is_valid_cache(val))
652 return -ENOENT;
653
654 if (get_user(newval, uval))
655 return -EFAULT;
656
657 /* This is also invariant: you can't change it. */
658 if (newval != get_ccsidr(val))
659 return -EINVAL;
660 return 0;
661 default:
662 return -ENOENT;
663 }
664}
665
4fe21e4c
RR		 666#ifdef CONFIG_VFPv3
667static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
668 KVM_REG_ARM_VFP_FPSCR,
669 KVM_REG_ARM_VFP_FPINST,
670 KVM_REG_ARM_VFP_FPINST2,
671 KVM_REG_ARM_VFP_MVFR0,
672 KVM_REG_ARM_VFP_MVFR1,
673 KVM_REG_ARM_VFP_FPSID };
674
675static unsigned int num_fp_regs(void)
676{
677 if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
678 return 32;
679 else
680 return 16;
681}
682
683static unsigned int num_vfp_regs(void)
684{
685 /* Normal FP regs + control regs. */
686 return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
687}
688
689static int copy_vfp_regids(u64 __user *uindices)
690{
691 unsigned int i;
692 const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
693 const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
694
695 for (i = 0; i < num_fp_regs(); i++) {
696 if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
697 uindices))
698 return -EFAULT;
699 uindices++;
700 }
701
702 for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
703 if (put_user(u32reg | vfp_sysregs[i], uindices))
704 return -EFAULT;
705 uindices++;
706 }
707
708 return num_vfp_regs();
709}
710
711static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
712{
713 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
714 u32 val;
715
716 /* Fail if we have unknown bits set. */
717 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
718 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
719 return -ENOENT;
720
721 if (vfpid < num_fp_regs()) {
722 if (KVM_REG_SIZE(id) != 8)
723 return -ENOENT;
724 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpregs[vfpid],
725 id);
726 }
727
728 /* FP control registers are all 32 bit. */
729 if (KVM_REG_SIZE(id) != 4)
730 return -ENOENT;
731
732 switch (vfpid) {
733 case KVM_REG_ARM_VFP_FPEXC:
734 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpexc, id);
735 case KVM_REG_ARM_VFP_FPSCR:
736 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpscr, id);
737 case KVM_REG_ARM_VFP_FPINST:
738 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst, id);
739 case KVM_REG_ARM_VFP_FPINST2:
740 return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst2, id);
741 case KVM_REG_ARM_VFP_MVFR0:
742 val = fmrx(MVFR0);
743 return reg_to_user(uaddr, &val, id);
744 case KVM_REG_ARM_VFP_MVFR1:
745 val = fmrx(MVFR1);
746 return reg_to_user(uaddr, &val, id);
747 case KVM_REG_ARM_VFP_FPSID:
748 val = fmrx(FPSID);
749 return reg_to_user(uaddr, &val, id);
750 default:
751 return -ENOENT;
752 }
753}
754
755static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
756{
757 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
758 u32 val;
759
760 /* Fail if we have unknown bits set. */
761 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
762 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
763 return -ENOENT;
764
765 if (vfpid < num_fp_regs()) {
766 if (KVM_REG_SIZE(id) != 8)
767 return -ENOENT;
768 return reg_from_user(&vcpu->arch.vfp_guest.fpregs[vfpid],
769 uaddr, id);
770 }
771
772 /* FP control registers are all 32 bit. */
773 if (KVM_REG_SIZE(id) != 4)
774 return -ENOENT;
775
776 switch (vfpid) {
777 case KVM_REG_ARM_VFP_FPEXC:
778 return reg_from_user(&vcpu->arch.vfp_guest.fpexc, uaddr, id);
779 case KVM_REG_ARM_VFP_FPSCR:
780 return reg_from_user(&vcpu->arch.vfp_guest.fpscr, uaddr, id);
781 case KVM_REG_ARM_VFP_FPINST:
782 return reg_from_user(&vcpu->arch.vfp_guest.fpinst, uaddr, id);
783 case KVM_REG_ARM_VFP_FPINST2:
784 return reg_from_user(&vcpu->arch.vfp_guest.fpinst2, uaddr, id);
785 /* These are invariant. */
786 case KVM_REG_ARM_VFP_MVFR0:
787 if (reg_from_user(&val, uaddr, id))
788 return -EFAULT;
789 if (val != fmrx(MVFR0))
790 return -EINVAL;
791 return 0;
792 case KVM_REG_ARM_VFP_MVFR1:
793 if (reg_from_user(&val, uaddr, id))
794 return -EFAULT;
795 if (val != fmrx(MVFR1))
796 return -EINVAL;
797 return 0;
798 case KVM_REG_ARM_VFP_FPSID:
799 if (reg_from_user(&val, uaddr, id))
800 return -EFAULT;
801 if (val != fmrx(FPSID))
802 return -EINVAL;
803 return 0;
804 default:
805 return -ENOENT;
806 }
807}
808#else /* !CONFIG_VFPv3 */
809static unsigned int num_vfp_regs(void)
810{
811 return 0;
812}
813
814static int copy_vfp_regids(u64 __user *uindices)
815{
816 return 0;
817}
818
819static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
820{
821 return -ENOENT;
822}
823
824static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
825{
826 return -ENOENT;
827}
828#endif /* !CONFIG_VFPv3 */
829
1138245c
CD		 830int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
831{
832 const struct coproc_reg *r;
833 void __user *uaddr = (void __user *)(long)reg->addr;
834
c27581ed
CD		 835 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
836 return demux_c15_get(reg->id, uaddr);
837
4fe21e4c
RR		 838 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
839 return vfp_get_reg(vcpu, reg->id, uaddr);
840
1138245c
CD		 841 r = index_to_coproc_reg(vcpu, reg->id);
842 if (!r)
843 return get_invariant_cp15(reg->id, uaddr);
844
845 /* Note: copies two regs if size is 64 bit. */
846 return reg_to_user(uaddr, &vcpu->arch.cp15[r->reg], reg->id);
847}
848
849int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
850{
851 const struct coproc_reg *r;
852 void __user *uaddr = (void __user *)(long)reg->addr;
853
c27581ed
CD		 854 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
855 return demux_c15_set(reg->id, uaddr);
856
4fe21e4c
RR		 857 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
858 return vfp_set_reg(vcpu, reg->id, uaddr);
859
1138245c
CD		 860 r = index_to_coproc_reg(vcpu, reg->id);
861 if (!r)
862 return set_invariant_cp15(reg->id, uaddr);
863
864 /* Note: copies two regs if size is 64 bit */
865 return reg_from_user(&vcpu->arch.cp15[r->reg], uaddr, reg->id);
866}
867
c27581ed
CD		 868static unsigned int num_demux_regs(void)
869{
870 unsigned int i, count = 0;
871
872 for (i = 0; i < CSSELR_MAX; i++)
873 if (is_valid_cache(i))
874 count++;
875
876 return count;
877}
878
879static int write_demux_regids(u64 __user *uindices)
880{
881 u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
882 unsigned int i;
883
884 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
885 for (i = 0; i < CSSELR_MAX; i++) {
886 if (!is_valid_cache(i))
887 continue;
888 if (put_user(val | i, uindices))
889 return -EFAULT;
890 uindices++;
891 }
892 return 0;
893}
894
1138245c
CD		 895static u64 cp15_to_index(const struct coproc_reg *reg)
896{
897 u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
898 if (reg->is_64) {
899 val |= KVM_REG_SIZE_U64;
900 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
901 val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
902 } else {
903 val |= KVM_REG_SIZE_U32;
904 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
905 val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
906 val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
907 val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
908 }
909 return val;
910}
911
912static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
913{
914 if (!*uind)
915 return true;
916
917 if (put_user(cp15_to_index(reg), *uind))
918 return false;
919
920 (*uind)++;
921 return true;
922}
923
924/* Assumed ordered tables, see kvm_coproc_table_init. */
925static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
926{
927 const struct coproc_reg *i1, *i2, *end1, *end2;
928 unsigned int total = 0;
929 size_t num;
930
931 /* We check for duplicates here, to allow arch-specific overrides. */
932 i1 = get_target_table(vcpu->arch.target, &num);
933 end1 = i1 + num;
934 i2 = cp15_regs;
935 end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
936
937 BUG_ON(i1 == end1 || i2 == end2);
938
939 /* Walk carefully, as both tables may refer to the same register. */
940 while (i1 || i2) {
941 int cmp = cmp_reg(i1, i2);
942 /* target-specific overrides generic entry. */
943 if (cmp <= 0) {
944 /* Ignore registers we trap but don't save. */
945 if (i1->reg) {
946 if (!copy_reg_to_user(i1, &uind))
947 return -EFAULT;
948 total++;
949 }
950 } else {
951 /* Ignore registers we trap but don't save. */
952 if (i2->reg) {
953 if (!copy_reg_to_user(i2, &uind))
954 return -EFAULT;
955 total++;
956 }
957 }
958
959 if (cmp <= 0 && ++i1 == end1)
960 i1 = NULL;
961 if (cmp >= 0 && ++i2 == end2)
962 i2 = NULL;
963 }
964 return total;
965}
966
967unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
968{
969 return ARRAY_SIZE(invariant_cp15)
c27581ed 970 + num_demux_regs()
4fe21e4c 971 + num_vfp_regs()
1138245c
CD		 972 + walk_cp15(vcpu, (u64 __user *)NULL);
973}
974
975int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
976{
977 unsigned int i;
978 int err;
979
980 /* Then give them all the invariant registers' indices. */
981 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
982 if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
983 return -EFAULT;
984 uindices++;
985 }
986
987 err = walk_cp15(vcpu, uindices);
c27581ed
CD		 988 if (err < 0)
989 return err;
990 uindices += err;
991
4fe21e4c
RR		 992 err = copy_vfp_regids(uindices);
993 if (err < 0)
994 return err;
995 uindices += err;
996
c27581ed 997 return write_demux_regids(uindices);
1138245c
CD		 998}
999
5b3e5e5b
CD		 1000void kvm_coproc_table_init(void)
1001{
1002 unsigned int i;
1003
1004 /* Make sure tables are unique and in order. */
1005 for (i = 1; i < ARRAY_SIZE(cp15_regs); i++)
1006 BUG_ON(cmp_reg(&cp15_regs[i-1], &cp15_regs[i]) >= 0);
1138245c
CD		 1007
1008 /* We abuse the reset function to overwrite the table itself. */
1009 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
1010 invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
c27581ed
CD		 1011
1012 /*
1013 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
1014 *
1015 * If software reads the Cache Type fields from Ctype1
1016 * upwards, once it has seen a value of 0b000, no caches
1017 * exist at further-out levels of the hierarchy. So, for
1018 * example, if Ctype3 is the first Cache Type field with a
1019 * value of 0b000, the values of Ctype4 to Ctype7 must be
1020 * ignored.
1021 */
1022 asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
1023 for (i = 0; i < 7; i++)
1024 if (((cache_levels >> (i*3)) & 7) == 0)
1025 break;
1026 /* Clear all higher bits. */
1027 cache_levels &= (1 << (i*3))-1;
5b3e5e5b
CD		 1028}
1029
1030/**
1031 * kvm_reset_coprocs - sets cp15 registers to reset value
1032 * @vcpu: The VCPU pointer
1033 *
1034 * This function finds the right table above and sets the registers on the
1035 * virtual CPU struct to their architecturally defined reset values.
1036 */
749cf76c
CD		 1037void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
1038{
5b3e5e5b
CD		 1039 size_t num;
1040 const struct coproc_reg *table;
1041
1042 /* Catch someone adding a register without putting in reset entry. */
1043 memset(vcpu->arch.cp15, 0x42, sizeof(vcpu->arch.cp15));
1044
1045 /* Generic chip reset first (so target could override). */
1046 reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
1047
1048 table = get_target_table(vcpu->arch.target, &num);
1049 reset_coproc_regs(vcpu, table, num);
1050
1051 for (num = 1; num < NR_CP15_REGS; num++)
1052 if (vcpu->arch.cp15[num] == 0x42424242)
1053 panic("Didn't reset vcpu->arch.cp15[%zi]", num);
749cf76c 1054}
Linux kernel - Deliverables
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