[deliverable/linux.git] / arch / arm / kvm / emulate.c

/*
 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#include <asm/kvm_emulate.h>

#define VCPU_NR_MODES		6
#define VCPU_REG_OFFSET_USR	0
#define VCPU_REG_OFFSET_FIQ	1
#define VCPU_REG_OFFSET_IRQ	2
#define VCPU_REG_OFFSET_SVC	3
#define VCPU_REG_OFFSET_ABT	4
#define VCPU_REG_OFFSET_UND	5
#define REG_OFFSET(_reg) \
	(offsetof(struct kvm_regs, _reg) / sizeof(u32))

#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])

static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
	/* USR/SYS Registers */
	[VCPU_REG_OFFSET_USR] = {
		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
		USR_REG_OFFSET(12), USR_REG_OFFSET(13),	USR_REG_OFFSET(14),
	},

	/* FIQ Registers */
	[VCPU_REG_OFFSET_FIQ] = {
		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
		USR_REG_OFFSET(6), USR_REG_OFFSET(7),
		REG_OFFSET(fiq_regs[0]), /* r8 */
		REG_OFFSET(fiq_regs[1]), /* r9 */
		REG_OFFSET(fiq_regs[2]), /* r10 */
		REG_OFFSET(fiq_regs[3]), /* r11 */
		REG_OFFSET(fiq_regs[4]), /* r12 */
		REG_OFFSET(fiq_regs[5]), /* r13 */
		REG_OFFSET(fiq_regs[6]), /* r14 */
	},

	/* IRQ Registers */
	[VCPU_REG_OFFSET_IRQ] = {
		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
		USR_REG_OFFSET(12),
		REG_OFFSET(irq_regs[0]), /* r13 */
		REG_OFFSET(irq_regs[1]), /* r14 */
	},

	/* SVC Registers */
	[VCPU_REG_OFFSET_SVC] = {
		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
		USR_REG_OFFSET(12),
		REG_OFFSET(svc_regs[0]), /* r13 */
		REG_OFFSET(svc_regs[1]), /* r14 */
	},

	/* ABT Registers */
	[VCPU_REG_OFFSET_ABT] = {
		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
		USR_REG_OFFSET(12),
		REG_OFFSET(abt_regs[0]), /* r13 */
		REG_OFFSET(abt_regs[1]), /* r14 */
	},

	/* UND Registers */
	[VCPU_REG_OFFSET_UND] = {
		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
		USR_REG_OFFSET(12),
		REG_OFFSET(und_regs[0]), /* r13 */
		REG_OFFSET(und_regs[1]), /* r14 */
	},
};

/*
 * Return a pointer to the register number valid in the current mode of
 * the virtual CPU.
 */
u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
{
	u32 *reg_array = (u32 *)&vcpu->arch.regs;
	u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;

	switch (mode) {
	case USR_MODE...SVC_MODE:
		mode &= ~MODE32_BIT; /* 0 ... 3 */
		break;

	case ABT_MODE:
		mode = VCPU_REG_OFFSET_ABT;
		break;

	case UND_MODE:
		mode = VCPU_REG_OFFSET_UND;
		break;

	case SYSTEM_MODE:
		mode = VCPU_REG_OFFSET_USR;
		break;

	default:
		BUG();
	}

	return reg_array + vcpu_reg_offsets[mode][reg_num];
}

/*
 * Return the SPSR for the current mode of the virtual CPU.
 */
u32 *vcpu_spsr(struct kvm_vcpu *vcpu)
{
	u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
	switch (mode) {
	case SVC_MODE:
		return &vcpu->arch.regs.KVM_ARM_SVC_spsr;
	case ABT_MODE:
		return &vcpu->arch.regs.KVM_ARM_ABT_spsr;
	case UND_MODE:
		return &vcpu->arch.regs.KVM_ARM_UND_spsr;
	case IRQ_MODE:
		return &vcpu->arch.regs.KVM_ARM_IRQ_spsr;
	case FIQ_MODE:
		return &vcpu->arch.regs.KVM_ARM_FIQ_spsr;
	default:
		BUG();
	}
}
Commit	Line	Data
749cf76c CD	1	/*
	2	* Copyright (C) 2012 - Virtual Open Systems and Columbia University
	3	* Author: Christoffer Dall <c.dall@virtualopensystems.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License, version 2, as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	17	*/
	18
	19	#include <asm/kvm_emulate.h>
	20
	21	#define VCPU_NR_MODES 6
	22	#define VCPU_REG_OFFSET_USR 0
	23	#define VCPU_REG_OFFSET_FIQ 1
	24	#define VCPU_REG_OFFSET_IRQ 2
	25	#define VCPU_REG_OFFSET_SVC 3
	26	#define VCPU_REG_OFFSET_ABT 4
	27	#define VCPU_REG_OFFSET_UND 5
	28	#define REG_OFFSET(_reg) \
	29	(offsetof(struct kvm_regs, _reg) / sizeof(u32))
	30
	31	#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
	32
	33	static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
	34	/* USR/SYS Registers */
	35	[VCPU_REG_OFFSET_USR] = {
	36	USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
	37	USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
	38	USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
	39	USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
	40	USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
	41	},
	42
	43	/* FIQ Registers */
	44	[VCPU_REG_OFFSET_FIQ] = {
	45	USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
	46	USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
	47	USR_REG_OFFSET(6), USR_REG_OFFSET(7),
	48	REG_OFFSET(fiq_regs[0]), /* r8 */
	49	REG_OFFSET(fiq_regs[1]), /* r9 */
	50	REG_OFFSET(fiq_regs[2]), /* r10 */
	51	REG_OFFSET(fiq_regs[3]), /* r11 */
	52	REG_OFFSET(fiq_regs[4]), /* r12 */
	53	REG_OFFSET(fiq_regs[5]), /* r13 */
	54	REG_OFFSET(fiq_regs[6]), /* r14 */
	55	},
	56
	57	/* IRQ Registers */
	58	[VCPU_REG_OFFSET_IRQ] = {
	59	USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
	60	USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
	61	USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
	62	USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
	63	USR_REG_OFFSET(12),
	64	REG_OFFSET(irq_regs[0]), /* r13 */
65	REG_OFFSET(irq_regs[1]), /* r14 */
66	},
67
68	/* SVC Registers */
69	[VCPU_REG_OFFSET_SVC] = {
70	USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
71	USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
72	USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
73	USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
74	USR_REG_OFFSET(12),
75	REG_OFFSET(svc_regs[0]), /* r13 */
76	REG_OFFSET(svc_regs[1]), /* r14 */
77	},
78
79	/* ABT Registers */
80	[VCPU_REG_OFFSET_ABT] = {
81	USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
82	USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
83	USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
84	USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
85	USR_REG_OFFSET(12),
86	REG_OFFSET(abt_regs[0]), /* r13 */
87	REG_OFFSET(abt_regs[1]), /* r14 */
88	},
89
90	/* UND Registers */
91	[VCPU_REG_OFFSET_UND] = {
92	USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
93	USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
94	USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
95	USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
96	USR_REG_OFFSET(12),
97	REG_OFFSET(und_regs[0]), /* r13 */
98	REG_OFFSET(und_regs[1]), /* r14 */
99	},
100	};
101
102	/*
103	* Return a pointer to the register number valid in the current mode of
104	* the virtual CPU.
105	*/
106	u32 vcpu_reg(struct kvm_vcpu vcpu, u8 reg_num)
107	{
108	u32 reg_array = (u32 )&vcpu->arch.regs;
109	u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
110
111	switch (mode) {
112	case USR_MODE...SVC_MODE:
113	mode &= ~MODE32_BIT; /* 0 ... 3 */
114	break;
115
116	case ABT_MODE:
117	mode = VCPU_REG_OFFSET_ABT;
118	break;
119
120	case UND_MODE:
121	mode = VCPU_REG_OFFSET_UND;
122	break;
123
124	case SYSTEM_MODE:
125	mode = VCPU_REG_OFFSET_USR;
126	break;
127
128	default:
129	BUG();
130	}
131
132	return reg_array + vcpu_reg_offsets[mode][reg_num];
133	}
134
135	/*
136	* Return the SPSR for the current mode of the virtual CPU.
137	*/
138	u32 vcpu_spsr(struct kvm_vcpu vcpu)
139	{
140	u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
141	switch (mode) {
142	case SVC_MODE:
143	return &vcpu->arch.regs.KVM_ARM_SVC_spsr;
144	case ABT_MODE:
145	return &vcpu->arch.regs.KVM_ARM_ABT_spsr;
146	case UND_MODE:
147	return &vcpu->arch.regs.KVM_ARM_UND_spsr;
148	case IRQ_MODE:
149	return &vcpu->arch.regs.KVM_ARM_IRQ_spsr;
150	case FIQ_MODE:
151	return &vcpu->arch.regs.KVM_ARM_FIQ_spsr;
152	default:
153	BUG();
154	}
155	}