[deliverable/linux.git] / arch / arm / kvm / psci.c

/*
 * Copyright (C) 2012 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kvm_host.h>
#include <linux/wait.h>

#include <asm/cputype.h>
#include <asm/kvm_emulate.h>
#include <asm/kvm_psci.h>

/*
 * This is an implementation of the Power State Coordination Interface
 * as described in ARM document number ARM DEN 0022A.
 */

#define AFFINITY_MASK(level)	~((0x1UL << ((level) * MPIDR_LEVEL_BITS)) - 1)

static unsigned long psci_affinity_mask(unsigned long affinity_level)
{
	if (affinity_level <= 3)
		return MPIDR_HWID_BITMASK & AFFINITY_MASK(affinity_level);

	return 0;
}

static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu)
{
	vcpu->arch.pause = true;
}

static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
{
	struct kvm *kvm = source_vcpu->kvm;
	struct kvm_vcpu *vcpu = NULL, *tmp;
	wait_queue_head_t *wq;
	unsigned long cpu_id;
	unsigned long mpidr;
	phys_addr_t target_pc;
	int i;

	cpu_id = *vcpu_reg(source_vcpu, 1);
	if (vcpu_mode_is_32bit(source_vcpu))
		cpu_id &= ~((u32) 0);

	kvm_for_each_vcpu(i, tmp, kvm) {
		mpidr = kvm_vcpu_get_mpidr(tmp);
		if ((mpidr & MPIDR_HWID_BITMASK) == (cpu_id & MPIDR_HWID_BITMASK)) {
			vcpu = tmp;
			break;
		}
	}

	/*
	 * Make sure the caller requested a valid CPU and that the CPU is
	 * turned off.
	 */
	if (!vcpu || !vcpu->arch.pause)
		return PSCI_RET_INVALID_PARAMS;

	target_pc = *vcpu_reg(source_vcpu, 2);

	kvm_reset_vcpu(vcpu);

	/* Gracefully handle Thumb2 entry point */
	if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
		target_pc &= ~((phys_addr_t) 1);
		vcpu_set_thumb(vcpu);
	}

	/* Propagate caller endianness */
	if (kvm_vcpu_is_be(source_vcpu))
		kvm_vcpu_set_be(vcpu);

	*vcpu_pc(vcpu) = target_pc;
	vcpu->arch.pause = false;
	smp_mb();		/* Make sure the above is visible */

	wq = kvm_arch_vcpu_wq(vcpu);
	wake_up_interruptible(wq);

	return PSCI_RET_SUCCESS;
}

static unsigned long kvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu)
{
	int i;
	unsigned long mpidr;
	unsigned long target_affinity;
	unsigned long target_affinity_mask;
	unsigned long lowest_affinity_level;
	struct kvm *kvm = vcpu->kvm;
	struct kvm_vcpu *tmp;

	target_affinity = *vcpu_reg(vcpu, 1);
	lowest_affinity_level = *vcpu_reg(vcpu, 2);

	/* Determine target affinity mask */
	target_affinity_mask = psci_affinity_mask(lowest_affinity_level);
	if (!target_affinity_mask)
		return PSCI_RET_INVALID_PARAMS;

	/* Ignore other bits of target affinity */
	target_affinity &= target_affinity_mask;

	/*
	 * If one or more VCPU matching target affinity are running
	 * then ON else OFF
	 */
	kvm_for_each_vcpu(i, tmp, kvm) {
		mpidr = kvm_vcpu_get_mpidr(tmp);
		if (((mpidr & target_affinity_mask) == target_affinity) &&
		    !tmp->arch.pause) {
			return PSCI_0_2_AFFINITY_LEVEL_ON;
		}
	}

	return PSCI_0_2_AFFINITY_LEVEL_OFF;
}

static void kvm_prepare_system_event(struct kvm_vcpu *vcpu, u32 type)
{
	memset(&vcpu->run->system_event, 0, sizeof(vcpu->run->system_event));
	vcpu->run->system_event.type = type;
	vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
}

static void kvm_psci_system_off(struct kvm_vcpu *vcpu)
{
	kvm_prepare_system_event(vcpu, KVM_SYSTEM_EVENT_SHUTDOWN);
}

static void kvm_psci_system_reset(struct kvm_vcpu *vcpu)
{
	kvm_prepare_system_event(vcpu, KVM_SYSTEM_EVENT_RESET);
}

int kvm_psci_version(struct kvm_vcpu *vcpu)
{
	if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features))
		return KVM_ARM_PSCI_0_2;

	return KVM_ARM_PSCI_0_1;
}

static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu)
{
	int ret = 1;
	unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0);
	unsigned long val;

	switch (psci_fn) {
	case PSCI_0_2_FN_PSCI_VERSION:
		/*
		 * Bits[31:16] = Major Version = 0
		 * Bits[15:0] = Minor Version = 2
		 */
		val = 2;
		break;
	case PSCI_0_2_FN_CPU_OFF:
		kvm_psci_vcpu_off(vcpu);
		val = PSCI_RET_SUCCESS;
		break;
	case PSCI_0_2_FN_CPU_ON:
	case PSCI_0_2_FN64_CPU_ON:
		val = kvm_psci_vcpu_on(vcpu);
		break;
	case PSCI_0_2_FN_AFFINITY_INFO:
	case PSCI_0_2_FN64_AFFINITY_INFO:
		val = kvm_psci_vcpu_affinity_info(vcpu);
		break;
	case PSCI_0_2_FN_SYSTEM_OFF:
		kvm_psci_system_off(vcpu);
		/*
		 * We should'nt be going back to guest VCPU after
		 * receiving SYSTEM_OFF request.
		 *
		 * If user space accidently/deliberately resumes
		 * guest VCPU after SYSTEM_OFF request then guest
		 * VCPU should see internal failure from PSCI return
		 * value. To achieve this, we preload r0 (or x0) with
		 * PSCI return value INTERNAL_FAILURE.
		 */
		val = PSCI_RET_INTERNAL_FAILURE;
		ret = 0;
		break;
	case PSCI_0_2_FN_SYSTEM_RESET:
		kvm_psci_system_reset(vcpu);
		/*
		 * Same reason as SYSTEM_OFF for preloading r0 (or x0)
		 * with PSCI return value INTERNAL_FAILURE.
		 */
		val = PSCI_RET_INTERNAL_FAILURE;
		ret = 0;
		break;
	case PSCI_0_2_FN_CPU_SUSPEND:
	case PSCI_0_2_FN_MIGRATE:
	case PSCI_0_2_FN_MIGRATE_INFO_TYPE:
	case PSCI_0_2_FN_MIGRATE_INFO_UP_CPU:
	case PSCI_0_2_FN64_CPU_SUSPEND:
	case PSCI_0_2_FN64_MIGRATE:
	case PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU:
		val = PSCI_RET_NOT_SUPPORTED;
		break;
	default:
		return -EINVAL;
	}

	*vcpu_reg(vcpu, 0) = val;
	return ret;
}

static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu)
{
	unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0);
	unsigned long val;

	switch (psci_fn) {
	case KVM_PSCI_FN_CPU_OFF:
		kvm_psci_vcpu_off(vcpu);
		val = PSCI_RET_SUCCESS;
		break;
	case KVM_PSCI_FN_CPU_ON:
		val = kvm_psci_vcpu_on(vcpu);
		break;
	case KVM_PSCI_FN_CPU_SUSPEND:
	case KVM_PSCI_FN_MIGRATE:
		val = PSCI_RET_NOT_SUPPORTED;
		break;
	default:
		return -EINVAL;
	}

	*vcpu_reg(vcpu, 0) = val;
	return 1;
}

/**
 * kvm_psci_call - handle PSCI call if r0 value is in range
 * @vcpu: Pointer to the VCPU struct
 *
 * Handle PSCI calls from guests through traps from HVC instructions.
 * The calling convention is similar to SMC calls to the secure world
 * where the function number is placed in r0.
 *
 * This function returns: > 0 (success), 0 (success but exit to user
 * space), and < 0 (errors)
 *
 * Errors:
 * -EINVAL: Unrecognized PSCI function
 */
int kvm_psci_call(struct kvm_vcpu *vcpu)
{
	switch (kvm_psci_version(vcpu)) {
	case KVM_ARM_PSCI_0_2:
		return kvm_psci_0_2_call(vcpu);
	case KVM_ARM_PSCI_0_1:
		return kvm_psci_0_1_call(vcpu);
	default:
		return -EINVAL;
	};
}
Commit	Line	Data
aa024c2f MZ	1	/*
	2	* Copyright (C) 2012 - ARM Ltd
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#include <linux/kvm_host.h>
	19	#include <linux/wait.h>
	20
79c64880	21	#include <asm/cputype.h>
aa024c2f MZ	22	#include <asm/kvm_emulate.h>
	23	#include <asm/kvm_psci.h>
	24
	25	/*
	26	* This is an implementation of the Power State Coordination Interface
	27	* as described in ARM document number ARM DEN 0022A.
	28	*/
	29
e6bc13c8 AP	30	#define AFFINITY_MASK(level) ~((0x1UL << ((level) * MPIDR_LEVEL_BITS)) - 1)
	31
	32	static unsigned long psci_affinity_mask(unsigned long affinity_level)
	33	{
	34	if (affinity_level <= 3)
	35	return MPIDR_HWID_BITMASK & AFFINITY_MASK(affinity_level);
	36
	37	return 0;
	38	}
	39
aa024c2f MZ	40	static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu)
	41	{
	42	vcpu->arch.pause = true;
	43	}
	44
	45	static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
	46	{
	47	struct kvm *kvm = source_vcpu->kvm;
79c64880	48	struct kvm_vcpu vcpu = NULL, tmp;
aa024c2f MZ	49	wait_queue_head_t *wq;
aa024c2f MZ	50	unsigned long cpu_id;
79c64880	51	unsigned long mpidr;
aa024c2f	52	phys_addr_t target_pc;
79c64880	53	int i;
aa024c2f MZ	54
	55	cpu_id = *vcpu_reg(source_vcpu, 1);
	56	if (vcpu_mode_is_32bit(source_vcpu))
	57	cpu_id &= ~((u32) 0);
	58
79c64880 MZ	59	kvm_for_each_vcpu(i, tmp, kvm) {
	60	mpidr = kvm_vcpu_get_mpidr(tmp);
	61	if ((mpidr & MPIDR_HWID_BITMASK) == (cpu_id & MPIDR_HWID_BITMASK)) {
	62	vcpu = tmp;
	63	break;
	64	}
	65	}
	66
478a8237 CD	67	/*
	68	* Make sure the caller requested a valid CPU and that the CPU is
	69	* turned off.
	70	*/
	71	if (!vcpu \|\| !vcpu->arch.pause)
7d0f84aa	72	return PSCI_RET_INVALID_PARAMS;
aa024c2f MZ	73
	74	target_pc = *vcpu_reg(source_vcpu, 2);
	75
aa024c2f MZ	76	kvm_reset_vcpu(vcpu);
	77
	78	/* Gracefully handle Thumb2 entry point */
	79	if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
	80	target_pc &= ~((phys_addr_t) 1);
	81	vcpu_set_thumb(vcpu);
	82	}
	83
ce94fe93 MZ	84	/* Propagate caller endianness */
	85	if (kvm_vcpu_is_be(source_vcpu))
	86	kvm_vcpu_set_be(vcpu);
	87
aa024c2f MZ	88	*vcpu_pc(vcpu) = target_pc;
	89	vcpu->arch.pause = false;
	90	smp_mb(); /* Make sure the above is visible */
	91
478a8237	92	wq = kvm_arch_vcpu_wq(vcpu);
aa024c2f MZ	93	wake_up_interruptible(wq);
aa024c2f MZ	94
7d0f84aa	95	return PSCI_RET_SUCCESS;
aa024c2f MZ	96	}
aa024c2f MZ	97
e6bc13c8 AP	98	static unsigned long kvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu)
	99	{
	100	int i;
	101	unsigned long mpidr;
	102	unsigned long target_affinity;
	103	unsigned long target_affinity_mask;
	104	unsigned long lowest_affinity_level;
	105	struct kvm *kvm = vcpu->kvm;
	106	struct kvm_vcpu *tmp;
	107
	108	target_affinity = *vcpu_reg(vcpu, 1);
	109	lowest_affinity_level = *vcpu_reg(vcpu, 2);
	110
	111	/* Determine target affinity mask */
	112	target_affinity_mask = psci_affinity_mask(lowest_affinity_level);
	113	if (!target_affinity_mask)
	114	return PSCI_RET_INVALID_PARAMS;
	115
	116	/* Ignore other bits of target affinity */
	117	target_affinity &= target_affinity_mask;
	118
	119	/*
	120	* If one or more VCPU matching target affinity are running
	121	* then ON else OFF
	122	*/
	123	kvm_for_each_vcpu(i, tmp, kvm) {
	124	mpidr = kvm_vcpu_get_mpidr(tmp);
	125	if (((mpidr & target_affinity_mask) == target_affinity) &&
	126	!tmp->arch.pause) {
	127	return PSCI_0_2_AFFINITY_LEVEL_ON;
	128	}
	129	}
	130
	131	return PSCI_0_2_AFFINITY_LEVEL_OFF;
	132	}
	133
4b123826 AP	134	static void kvm_prepare_system_event(struct kvm_vcpu *vcpu, u32 type)
	135	{
	136	memset(&vcpu->run->system_event, 0, sizeof(vcpu->run->system_event));
	137	vcpu->run->system_event.type = type;
	138	vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
	139	}
	140
	141	static void kvm_psci_system_off(struct kvm_vcpu *vcpu)
	142	{
	143	kvm_prepare_system_event(vcpu, KVM_SYSTEM_EVENT_SHUTDOWN);
	144	}
	145
	146	static void kvm_psci_system_reset(struct kvm_vcpu *vcpu)
	147	{
	148	kvm_prepare_system_event(vcpu, KVM_SYSTEM_EVENT_RESET);
	149	}
	150
7d0f84aa AP	151	int kvm_psci_version(struct kvm_vcpu *vcpu)
	152	{
	153	if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features))
	154	return KVM_ARM_PSCI_0_2;
	155
	156	return KVM_ARM_PSCI_0_1;
	157	}
	158
e8e7fcc5	159	static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu)
7d0f84aa	160	{
4b123826	161	int ret = 1;
7d0f84aa AP	162	unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0);
	163	unsigned long val;
	164
	165	switch (psci_fn) {
	166	case PSCI_0_2_FN_PSCI_VERSION:
	167	/*
	168	* Bits[31:16] = Major Version = 0
	169	* Bits[15:0] = Minor Version = 2
	170	*/
	171	val = 2;
	172	break;
	173	case PSCI_0_2_FN_CPU_OFF:
	174	kvm_psci_vcpu_off(vcpu);
	175	val = PSCI_RET_SUCCESS;
	176	break;
	177	case PSCI_0_2_FN_CPU_ON:
	178	case PSCI_0_2_FN64_CPU_ON:
	179	val = kvm_psci_vcpu_on(vcpu);
	180	break;
e6bc13c8 AP	181	case PSCI_0_2_FN_AFFINITY_INFO:
	182	case PSCI_0_2_FN64_AFFINITY_INFO:
	183	val = kvm_psci_vcpu_affinity_info(vcpu);
	184	break;
4b123826 AP	185	case PSCI_0_2_FN_SYSTEM_OFF:
	186	kvm_psci_system_off(vcpu);
	187	/*
	188	* We should'nt be going back to guest VCPU after
	189	* receiving SYSTEM_OFF request.
	190	*
	191	* If user space accidently/deliberately resumes
	192	* guest VCPU after SYSTEM_OFF request then guest
	193	* VCPU should see internal failure from PSCI return
	194	* value. To achieve this, we preload r0 (or x0) with
	195	* PSCI return value INTERNAL_FAILURE.
	196	*/
	197	val = PSCI_RET_INTERNAL_FAILURE;
	198	ret = 0;
	199	break;
	200	case PSCI_0_2_FN_SYSTEM_RESET:
	201	kvm_psci_system_reset(vcpu);
	202	/*
	203	* Same reason as SYSTEM_OFF for preloading r0 (or x0)
	204	* with PSCI return value INTERNAL_FAILURE.
	205	*/
	206	val = PSCI_RET_INTERNAL_FAILURE;
	207	ret = 0;
	208	break;
7d0f84aa	209	case PSCI_0_2_FN_CPU_SUSPEND:
7d0f84aa AP	210	case PSCI_0_2_FN_MIGRATE:
	211	case PSCI_0_2_FN_MIGRATE_INFO_TYPE:
	212	case PSCI_0_2_FN_MIGRATE_INFO_UP_CPU:
7d0f84aa	213	case PSCI_0_2_FN64_CPU_SUSPEND:
7d0f84aa AP	214	case PSCI_0_2_FN64_MIGRATE:
	215	case PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU:
	216	val = PSCI_RET_NOT_SUPPORTED;
	217	break;
	218	default:
e8e7fcc5	219	return -EINVAL;
7d0f84aa AP	220	}
	221
	222	*vcpu_reg(vcpu, 0) = val;
4b123826	223	return ret;
7d0f84aa AP	224	}
7d0f84aa AP	225
e8e7fcc5	226	static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu)
aa024c2f MZ	227	{
	228	unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0);
	229	unsigned long val;
	230
	231	switch (psci_fn) {
	232	case KVM_PSCI_FN_CPU_OFF:
	233	kvm_psci_vcpu_off(vcpu);
7d0f84aa	234	val = PSCI_RET_SUCCESS;
aa024c2f MZ	235	break;
	236	case KVM_PSCI_FN_CPU_ON:
	237	val = kvm_psci_vcpu_on(vcpu);
	238	break;
	239	case KVM_PSCI_FN_CPU_SUSPEND:
	240	case KVM_PSCI_FN_MIGRATE:
7d0f84aa	241	val = PSCI_RET_NOT_SUPPORTED;
aa024c2f	242	break;
aa024c2f	243	default:
e8e7fcc5	244	return -EINVAL;
aa024c2f MZ	245	}
	246
	247	*vcpu_reg(vcpu, 0) = val;
e8e7fcc5	248	return 1;
aa024c2f	249	}
7d0f84aa AP	250
	251	/**
	252	* kvm_psci_call - handle PSCI call if r0 value is in range
	253	* @vcpu: Pointer to the VCPU struct
	254	*
	255	* Handle PSCI calls from guests through traps from HVC instructions.
e8e7fcc5 AP	256	* The calling convention is similar to SMC calls to the secure world
	257	* where the function number is placed in r0.
	258	*
	259	* This function returns: > 0 (success), 0 (success but exit to user
	260	* space), and < 0 (errors)
	261	*
	262	* Errors:
	263	* -EINVAL: Unrecognized PSCI function
7d0f84aa	264	*/
e8e7fcc5	265	int kvm_psci_call(struct kvm_vcpu *vcpu)
7d0f84aa AP	266	{
	267	switch (kvm_psci_version(vcpu)) {
	268	case KVM_ARM_PSCI_0_2:
	269	return kvm_psci_0_2_call(vcpu);
	270	case KVM_ARM_PSCI_0_1:
	271	return kvm_psci_0_1_call(vcpu);
	272	default:
e8e7fcc5	273	return -EINVAL;
7d0f84aa AP	274	};
7d0f84aa AP	275	}