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1 | #include <asm/unwind.h> |
2 | ||
6323f0cc | 3 | #if __LINUX_ARM_ARCH__ >= 6 |
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4 | .macro bitop, name, instr |
5 | ENTRY( \name ) | |
6 | UNWIND( .fnstart ) | |
a16ede35 RK |
7 | ands ip, r1, #3 |
8 | strneb r1, [ip] @ assert word-aligned | |
54ea06f6 | 9 | mov r2, #1 |
6323f0cc RK |
10 | and r3, r0, #31 @ Get bit offset |
11 | mov r0, r0, lsr #5 | |
12 | add r1, r1, r0, lsl #2 @ Get word offset | |
b7ec6994 | 13 | #if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) |
d779c07d WD |
14 | .arch_extension mp |
15 | ALT_SMP(W(pldw) [r1]) | |
16 | ALT_UP(W(nop)) | |
17 | #endif | |
54ea06f6 | 18 | mov r3, r2, lsl r3 |
6323f0cc | 19 | 1: ldrex r2, [r1] |
54ea06f6 | 20 | \instr r2, r2, r3 |
6323f0cc | 21 | strex r0, r2, [r1] |
e7ec0293 | 22 | cmp r0, #0 |
54ea06f6 | 23 | bne 1b |
3ba6e69a | 24 | bx lr |
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25 | UNWIND( .fnend ) |
26 | ENDPROC(\name ) | |
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27 | .endm |
28 | ||
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29 | .macro testop, name, instr, store |
30 | ENTRY( \name ) | |
31 | UNWIND( .fnstart ) | |
a16ede35 RK |
32 | ands ip, r1, #3 |
33 | strneb r1, [ip] @ assert word-aligned | |
54ea06f6 | 34 | mov r2, #1 |
6323f0cc RK |
35 | and r3, r0, #31 @ Get bit offset |
36 | mov r0, r0, lsr #5 | |
37 | add r1, r1, r0, lsl #2 @ Get word offset | |
54ea06f6 | 38 | mov r3, r2, lsl r3 @ create mask |
bac4e960 | 39 | smp_dmb |
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40 | #if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) |
41 | .arch_extension mp | |
42 | ALT_SMP(W(pldw) [r1]) | |
43 | ALT_UP(W(nop)) | |
44 | #endif | |
6323f0cc | 45 | 1: ldrex r2, [r1] |
54ea06f6 | 46 | ands r0, r2, r3 @ save old value of bit |
6323f0cc RK |
47 | \instr r2, r2, r3 @ toggle bit |
48 | strex ip, r2, [r1] | |
614d73ed | 49 | cmp ip, #0 |
54ea06f6 | 50 | bne 1b |
bac4e960 | 51 | smp_dmb |
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52 | cmp r0, #0 |
53 | movne r0, #1 | |
3ba6e69a | 54 | 2: bx lr |
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55 | UNWIND( .fnend ) |
56 | ENDPROC(\name ) | |
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57 | .endm |
58 | #else | |
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59 | .macro bitop, name, instr |
60 | ENTRY( \name ) | |
61 | UNWIND( .fnstart ) | |
a16ede35 RK |
62 | ands ip, r1, #3 |
63 | strneb r1, [ip] @ assert word-aligned | |
6323f0cc RK |
64 | and r2, r0, #31 |
65 | mov r0, r0, lsr #5 | |
7a55fd0b RK |
66 | mov r3, #1 |
67 | mov r3, r3, lsl r2 | |
59d1ff3b | 68 | save_and_disable_irqs ip |
6323f0cc | 69 | ldr r2, [r1, r0, lsl #2] |
7a55fd0b | 70 | \instr r2, r2, r3 |
6323f0cc | 71 | str r2, [r1, r0, lsl #2] |
7a55fd0b RK |
72 | restore_irqs ip |
73 | mov pc, lr | |
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74 | UNWIND( .fnend ) |
75 | ENDPROC(\name ) | |
7a55fd0b RK |
76 | .endm |
77 | ||
78 | /** | |
79 | * testop - implement a test_and_xxx_bit operation. | |
80 | * @instr: operational instruction | |
81 | * @store: store instruction | |
82 | * | |
83 | * Note: we can trivially conditionalise the store instruction | |
6cbdc8c5 | 84 | * to avoid dirtying the data cache. |
7a55fd0b | 85 | */ |
c36ef4b1 WD |
86 | .macro testop, name, instr, store |
87 | ENTRY( \name ) | |
88 | UNWIND( .fnstart ) | |
a16ede35 RK |
89 | ands ip, r1, #3 |
90 | strneb r1, [ip] @ assert word-aligned | |
6323f0cc RK |
91 | and r3, r0, #31 |
92 | mov r0, r0, lsr #5 | |
59d1ff3b | 93 | save_and_disable_irqs ip |
6323f0cc RK |
94 | ldr r2, [r1, r0, lsl #2]! |
95 | mov r0, #1 | |
7a55fd0b RK |
96 | tst r2, r0, lsl r3 |
97 | \instr r2, r2, r0, lsl r3 | |
98 | \store r2, [r1] | |
7a55fd0b | 99 | moveq r0, #0 |
0d928b0b | 100 | restore_irqs ip |
7a55fd0b | 101 | mov pc, lr |
c36ef4b1 WD |
102 | UNWIND( .fnend ) |
103 | ENDPROC(\name ) | |
7a55fd0b | 104 | .endm |
54ea06f6 | 105 | #endif |