[deliverable/linux.git] / arch / arm / mach-at91 / at91cap9.c

/*
 * arch/arm/mach-at91/at91cap9.c
 *
 *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
 *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
 *  Copyright (C) 2007 Atmel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_info.h>
#include <asm/system_misc.h>

#include <mach/cpu.h>
#include <mach/at91cap9.h>
#include <mach/at91_pmc.h>

#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioABCD_clk = {
	.name		= "pioABCD_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_PIOABCD,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mpb0_clk = {
	.name		= "mpb0_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_MPB0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mpb1_clk = {
	.name		= "mpb1_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_MPB1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mpb2_clk = {
	.name		= "mpb2_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_MPB2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mpb3_clk = {
	.name		= "mpb3_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_MPB3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mpb4_clk = {
	.name		= "mpb4_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_MPB4,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
	.name		= "mci0_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_MCI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
	.name		= "mci1_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_MCI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk can_clk = {
	.name		= "can_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_CAN,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
	.name		= "tcb_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_TCB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "pclk",
	.pmc_mask	= 1 << AT91CAP9_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk aestdes_clk = {
	.name		= "aestdes_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_AESTDES,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk adc_clk = {
	.name		= "adc_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_ADC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91CAP9_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioABCD_clk,
	&mpb0_clk,
	&mpb1_clk,
	&mpb2_clk,
	&mpb3_clk,
	&mpb4_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&mmc0_clk,
	&mmc1_clk,
	&can_clk,
	&twi_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&ac97_clk,
	&tcb_clk,
	&pwm_clk,
	&macb_clk,
	&aestdes_clk,
	&adc_clk,
	&isi_clk,
	&lcdc_clk,
	&dma_clk,
	&udphs_clk,
	&ohci_clk,
	// irq0 .. irq1
};

static struct clk_lookup periph_clocks_lookups[] = {
	/* One additional fake clock for macb_hclk */
	CLKDEV_CON_ID("hclk", &macb_clk),
	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	/* fake hclk clock */
	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
	CLKDEV_CON_ID("pioA", &pioABCD_clk),
	CLKDEV_CON_ID("pioB", &pioABCD_clk),
	CLKDEV_CON_ID("pioC", &pioABCD_clk),
	CLKDEV_CON_ID("pioD", &pioABCD_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
};

/*
 * The four programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};
static struct clk pck2 = {
	.name		= "pck2",
	.pmc_mask	= AT91_PMC_PCK2,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 2,
};
static struct clk pck3 = {
	.name		= "pck3",
	.pmc_mask	= AT91_PMC_PCK3,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 3,
};

static void __init at91cap9_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
	clk_register(&pck2);
	clk_register(&pck3);
}

static struct clk_lookup console_clock_lookup;

void __init at91cap9_set_console_clock(int id)
{
	if (id >= ARRAY_SIZE(usart_clocks_lookups))
		return;

	console_clock_lookup.con_id = "usart";
	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	clkdev_add(&console_clock_lookup);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
	{
		.id		= AT91CAP9_ID_PIOABCD,
		.regbase	= AT91CAP9_BASE_PIOA,
	}, {
		.id		= AT91CAP9_ID_PIOABCD,
		.regbase	= AT91CAP9_BASE_PIOB,
	}, {
		.id		= AT91CAP9_ID_PIOABCD,
		.regbase	= AT91CAP9_BASE_PIOC,
	}, {
		.id		= AT91CAP9_ID_PIOABCD,
		.regbase	= AT91CAP9_BASE_PIOD,
	}
};

/* --------------------------------------------------------------------
 *  AT91CAP9 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91cap9_map_io(void)
{
	at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
}

static void __init at91cap9_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
	at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
	at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
}

static void __init at91cap9_initialize(void)
{
	arm_pm_restart = at91sam9g45_restart;
	at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);

	/* Register GPIO subsystem */
	at91_gpio_init(at91cap9_gpio, 4);

	/* Remember the silicon revision */
	if (cpu_is_at91cap9_revB())
		system_rev = 0xB;
	else if (cpu_is_at91cap9_revC())
		system_rev = 0xC;
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller (FIQ) */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A, B, C and D */
	0,	/* MP Block Peripheral 0 */
	0,	/* MP Block Peripheral 1 */
	0,	/* MP Block Peripheral 2 */
	0,	/* MP Block Peripheral 3 */
	0,	/* MP Block Peripheral 4 */
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	0,	/* Multimedia Card Interface 0 */
	0,	/* Multimedia Card Interface 1 */
	3,	/* CAN */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	5,	/* AC97 Controller */
	0,	/* Timer Counter 0, 1 and 2 */
	0,	/* Pulse Width Modulation Controller */
	3,	/* Ethernet */
	0,	/* Advanced Encryption Standard, Triple DES*/
	0,	/* Analog-to-Digital Converter */
	0,	/* Image Sensor Interface */
	3,	/* LCD Controller */
	0,	/* DMA Controller */
	2,	/* USB Device Port */
	2,	/* USB Host port */
	0,	/* Advanced Interrupt Controller (IRQ0) */
	0,	/* Advanced Interrupt Controller (IRQ1) */
};

struct at91_init_soc __initdata at91cap9_soc = {
	.map_io = at91cap9_map_io,
	.default_irq_priority = at91cap9_default_irq_priority,
	.ioremap_registers = at91cap9_ioremap_registers,
	.register_clocks = at91cap9_register_clocks,
	.init = at91cap9_initialize,
};
Commit	Line	Data
2b3b3516 AV	1	/*
	2	* arch/arm/mach-at91/at91cap9.c
	3	*
	4	* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
	5	* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
	6	* Copyright (C) 2007 Atmel Corporation.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	*/
	14
	15	#include <linux/module.h>
	16
80b02c17	17	#include <asm/irq.h>
2b3b3516 AV	18	#include <asm/mach/arch.h>
2b3b3516 AV	19	#include <asm/mach/map.h>
9f97da78 DH	20	#include <asm/system_info.h>
9f97da78 DH	21	#include <asm/system_misc.h>
7be90a6b SP	22
7be90a6b SP	23	#include <mach/cpu.h>
a09e64fb RK	24	#include <mach/at91cap9.h>
a09e64fb RK	25	#include <mach/at91_pmc.h>
2b3b3516	26
21d08b9d	27	#include "soc.h"
2b3b3516 AV	28	#include "generic.h"
2b3b3516 AV	29	#include "clock.h"
faee0cc3	30	#include "sam9_smc.h"
2b3b3516	31
2b3b3516 AV	32	/* --------------------------------------------------------------------
	33	* Clocks
	34	* -------------------------------------------------------------------- */
	35
	36	/*
	37	* The peripheral clocks.
	38	*/
	39	static struct clk pioABCD_clk = {
	40	.name = "pioABCD_clk",
	41	.pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
	42	.type = CLK_TYPE_PERIPHERAL,
	43	};
	44	static struct clk mpb0_clk = {
	45	.name = "mpb0_clk",
	46	.pmc_mask = 1 << AT91CAP9_ID_MPB0,
	47	.type = CLK_TYPE_PERIPHERAL,
	48	};
	49	static struct clk mpb1_clk = {
	50	.name = "mpb1_clk",
	51	.pmc_mask = 1 << AT91CAP9_ID_MPB1,
	52	.type = CLK_TYPE_PERIPHERAL,
	53	};
	54	static struct clk mpb2_clk = {
	55	.name = "mpb2_clk",
	56	.pmc_mask = 1 << AT91CAP9_ID_MPB2,
	57	.type = CLK_TYPE_PERIPHERAL,
	58	};
	59	static struct clk mpb3_clk = {
	60	.name = "mpb3_clk",
	61	.pmc_mask = 1 << AT91CAP9_ID_MPB3,
	62	.type = CLK_TYPE_PERIPHERAL,
	63	};
	64	static struct clk mpb4_clk = {
	65	.name = "mpb4_clk",
	66	.pmc_mask = 1 << AT91CAP9_ID_MPB4,
	67	.type = CLK_TYPE_PERIPHERAL,
	68	};
	69	static struct clk usart0_clk = {
	70	.name = "usart0_clk",
	71	.pmc_mask = 1 << AT91CAP9_ID_US0,
	72	.type = CLK_TYPE_PERIPHERAL,
	73	};
	74	static struct clk usart1_clk = {
	75	.name = "usart1_clk",
	76	.pmc_mask = 1 << AT91CAP9_ID_US1,
	77	.type = CLK_TYPE_PERIPHERAL,
	78	};
	79	static struct clk usart2_clk = {
	80	.name = "usart2_clk",
	81	.pmc_mask = 1 << AT91CAP9_ID_US2,
	82	.type = CLK_TYPE_PERIPHERAL,
	83	};
	84	static struct clk mmc0_clk = {
	85	.name = "mci0_clk",
	86	.pmc_mask = 1 << AT91CAP9_ID_MCI0,
	87	.type = CLK_TYPE_PERIPHERAL,
	88	};
	89	static struct clk mmc1_clk = {
	90	.name = "mci1_clk",
	91	.pmc_mask = 1 << AT91CAP9_ID_MCI1,
	92	.type = CLK_TYPE_PERIPHERAL,
	93	};
	94	static struct clk can_clk = {
	95	.name = "can_clk",
96	.pmc_mask = 1 << AT91CAP9_ID_CAN,
97	.type = CLK_TYPE_PERIPHERAL,
98	};
99	static struct clk twi_clk = {
100	.name = "twi_clk",
101	.pmc_mask = 1 << AT91CAP9_ID_TWI,
102	.type = CLK_TYPE_PERIPHERAL,
103	};
104	static struct clk spi0_clk = {
105	.name = "spi0_clk",
106	.pmc_mask = 1 << AT91CAP9_ID_SPI0,
107	.type = CLK_TYPE_PERIPHERAL,
108	};
109	static struct clk spi1_clk = {
110	.name = "spi1_clk",
111	.pmc_mask = 1 << AT91CAP9_ID_SPI1,
112	.type = CLK_TYPE_PERIPHERAL,
113	};
114	static struct clk ssc0_clk = {
115	.name = "ssc0_clk",
116	.pmc_mask = 1 << AT91CAP9_ID_SSC0,
117	.type = CLK_TYPE_PERIPHERAL,
118	};
119	static struct clk ssc1_clk = {
120	.name = "ssc1_clk",
121	.pmc_mask = 1 << AT91CAP9_ID_SSC1,
122	.type = CLK_TYPE_PERIPHERAL,
123	};
124	static struct clk ac97_clk = {
125	.name = "ac97_clk",
126	.pmc_mask = 1 << AT91CAP9_ID_AC97C,
127	.type = CLK_TYPE_PERIPHERAL,
128	};
129	static struct clk tcb_clk = {
130	.name = "tcb_clk",
131	.pmc_mask = 1 << AT91CAP9_ID_TCB,
132	.type = CLK_TYPE_PERIPHERAL,
133	};
bb1ad68b AV	134	static struct clk pwm_clk = {
bb1ad68b AV	135	.name = "pwm_clk",
2b3b3516 AV	136	.pmc_mask = 1 << AT91CAP9_ID_PWMC,
	137	.type = CLK_TYPE_PERIPHERAL,
	138	};
	139	static struct clk macb_clk = {
865d605e	140	.name = "pclk",
2b3b3516 AV	141	.pmc_mask = 1 << AT91CAP9_ID_EMAC,
	142	.type = CLK_TYPE_PERIPHERAL,
	143	};
	144	static struct clk aestdes_clk = {
	145	.name = "aestdes_clk",
	146	.pmc_mask = 1 << AT91CAP9_ID_AESTDES,
	147	.type = CLK_TYPE_PERIPHERAL,
	148	};
	149	static struct clk adc_clk = {
	150	.name = "adc_clk",
	151	.pmc_mask = 1 << AT91CAP9_ID_ADC,
	152	.type = CLK_TYPE_PERIPHERAL,
	153	};
	154	static struct clk isi_clk = {
	155	.name = "isi_clk",
	156	.pmc_mask = 1 << AT91CAP9_ID_ISI,
	157	.type = CLK_TYPE_PERIPHERAL,
	158	};
	159	static struct clk lcdc_clk = {
	160	.name = "lcdc_clk",
	161	.pmc_mask = 1 << AT91CAP9_ID_LCDC,
	162	.type = CLK_TYPE_PERIPHERAL,
	163	};
	164	static struct clk dma_clk = {
	165	.name = "dma_clk",
	166	.pmc_mask = 1 << AT91CAP9_ID_DMA,
	167	.type = CLK_TYPE_PERIPHERAL,
	168	};
	169	static struct clk udphs_clk = {
	170	.name = "udphs_clk",
	171	.pmc_mask = 1 << AT91CAP9_ID_UDPHS,
	172	.type = CLK_TYPE_PERIPHERAL,
	173	};
	174	static struct clk ohci_clk = {
	175	.name = "ohci_clk",
	176	.pmc_mask = 1 << AT91CAP9_ID_UHP,
	177	.type = CLK_TYPE_PERIPHERAL,
	178	};
	179
	180	static struct clk *periph_clocks[] __initdata = {
	181	&pioABCD_clk,
	182	&mpb0_clk,
	183	&mpb1_clk,
	184	&mpb2_clk,
	185	&mpb3_clk,
	186	&mpb4_clk,
	187	&usart0_clk,
	188	&usart1_clk,
	189	&usart2_clk,
	190	&mmc0_clk,
	191	&mmc1_clk,
	192	&can_clk,
	193	&twi_clk,
	194	&spi0_clk,
	195	&spi1_clk,
	196	&ssc0_clk,
	197	&ssc1_clk,
	198	&ac97_clk,
	199	&tcb_clk,
bb1ad68b	200	&pwm_clk,
2b3b3516 AV	201	&macb_clk,
	202	&aestdes_clk,
	203	&adc_clk,
	204	&isi_clk,
	205	&lcdc_clk,
	206	&dma_clk,
	207	&udphs_clk,
	208	&ohci_clk,
	209	// irq0 .. irq1
	210	};
	211
bd602995	212	static struct clk_lookup periph_clocks_lookups[] = {
865d605e JI	213	/* One additional fake clock for macb_hclk */
865d605e JI	214	CLKDEV_CON_ID("hclk", &macb_clk),
9d87159e JCPV	215	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
9d87159e JCPV	216	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
bd602995 JCPV	217	CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
	218	CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
	219	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	220	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	221	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
c5efefac JE	222	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
c5efefac JE	223	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
0af4316b JCPV	224	/* fake hclk clock */
0af4316b JCPV	225	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
619d4a4b JCPV	226	CLKDEV_CON_ID("pioA", &pioABCD_clk),
	227	CLKDEV_CON_ID("pioB", &pioABCD_clk),
	228	CLKDEV_CON_ID("pioC", &pioABCD_clk),
	229	CLKDEV_CON_ID("pioD", &pioABCD_clk),
bd602995 JCPV	230	};
	231
	232	static struct clk_lookup usart_clocks_lookups[] = {
	233	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	234	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	235	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	236	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	237	};
	238
2b3b3516 AV	239	/*
	240	* The four programmable clocks.
	241	* You must configure pin multiplexing to bring these signals out.
	242	*/
	243	static struct clk pck0 = {
	244	.name = "pck0",
	245	.pmc_mask = AT91_PMC_PCK0,
	246	.type = CLK_TYPE_PROGRAMMABLE,
	247	.id = 0,
	248	};
	249	static struct clk pck1 = {
	250	.name = "pck1",
	251	.pmc_mask = AT91_PMC_PCK1,
	252	.type = CLK_TYPE_PROGRAMMABLE,
	253	.id = 1,
	254	};
	255	static struct clk pck2 = {
	256	.name = "pck2",
	257	.pmc_mask = AT91_PMC_PCK2,
	258	.type = CLK_TYPE_PROGRAMMABLE,
	259	.id = 2,
	260	};
	261	static struct clk pck3 = {
	262	.name = "pck3",
	263	.pmc_mask = AT91_PMC_PCK3,
	264	.type = CLK_TYPE_PROGRAMMABLE,
	265	.id = 3,
	266	};
	267
	268	static void __init at91cap9_register_clocks(void)
	269	{
	270	int i;
	271
	272	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	273	clk_register(periph_clocks[i]);
	274
bd602995 JCPV	275	clkdev_add_table(periph_clocks_lookups,
	276	ARRAY_SIZE(periph_clocks_lookups));
	277	clkdev_add_table(usart_clocks_lookups,
	278	ARRAY_SIZE(usart_clocks_lookups));
	279
2b3b3516 AV	280	clk_register(&pck0);
	281	clk_register(&pck1);
	282	clk_register(&pck2);
	283	clk_register(&pck3);
	284	}
	285
bd602995 JCPV	286	static struct clk_lookup console_clock_lookup;
	287
	288	void __init at91cap9_set_console_clock(int id)
	289	{
	290	if (id >= ARRAY_SIZE(usart_clocks_lookups))
	291	return;
	292
	293	console_clock_lookup.con_id = "usart";
	294	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	295	clkdev_add(&console_clock_lookup);
	296	}
	297
2b3b3516 AV	298	/* --------------------------------------------------------------------
	299	* GPIO
	300	* -------------------------------------------------------------------- */
	301
1a2d9156	302	static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
2b3b3516 AV	303	{
2b3b3516 AV	304	.id = AT91CAP9_ID_PIOABCD,
80e91cb8	305	.regbase = AT91CAP9_BASE_PIOA,
2b3b3516 AV	306	}, {
2b3b3516 AV	307	.id = AT91CAP9_ID_PIOABCD,
80e91cb8	308	.regbase = AT91CAP9_BASE_PIOB,
2b3b3516 AV	309	}, {
2b3b3516 AV	310	.id = AT91CAP9_ID_PIOABCD,
80e91cb8	311	.regbase = AT91CAP9_BASE_PIOC,
2b3b3516 AV	312	}, {
2b3b3516 AV	313	.id = AT91CAP9_ID_PIOABCD,
80e91cb8	314	.regbase = AT91CAP9_BASE_PIOD,
2b3b3516 AV	315	}
	316	};
	317
2b3b3516 AV	318	/* --------------------------------------------------------------------
	319	* AT91CAP9 processor initialization
	320	* -------------------------------------------------------------------- */
	321
21d08b9d	322	static void __init at91cap9_map_io(void)
2b3b3516	323	{
f0051d82	324	at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
1b021a3b	325	}
2b3b3516	326
cfa5a1fe JCPV	327	static void __init at91cap9_ioremap_registers(void)
cfa5a1fe JCPV	328	{
f22deee5	329	at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
e9f68b5c	330	at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
4ab0c599	331	at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
faee0cc3	332	at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
cfa5a1fe JCPV	333	}
cfa5a1fe JCPV	334
46539374 JCPV	335	static void __init at91cap9_initialize(void)
46539374 JCPV	336	{
14f991a7	337	arm_pm_restart = at91sam9g45_restart;
2b3b3516 AV	338	at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) \| (1 << AT91CAP9_ID_IRQ1);
2b3b3516 AV	339
2b3b3516 AV	340	/* Register GPIO subsystem */
2b3b3516 AV	341	at91_gpio_init(at91cap9_gpio, 4);
7be90a6b SP	342
	343	/* Remember the silicon revision */
	344	if (cpu_is_at91cap9_revB())
	345	system_rev = 0xB;
	346	else if (cpu_is_at91cap9_revC())
	347	system_rev = 0xC;
2b3b3516 AV	348	}
	349
	350	/* --------------------------------------------------------------------
	351	* Interrupt initialization
	352	* -------------------------------------------------------------------- */
	353
	354	/*
	355	* The default interrupt priority levels (0 = lowest, 7 = highest).
	356	*/
	357	static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
	358	7, /* Advanced Interrupt Controller (FIQ) */
	359	7, /* System Peripherals */
	360	1, /* Parallel IO Controller A, B, C and D */
	361	0, /* MP Block Peripheral 0 */
	362	0, /* MP Block Peripheral 1 */
	363	0, /* MP Block Peripheral 2 */
	364	0, /* MP Block Peripheral 3 */
	365	0, /* MP Block Peripheral 4 */
	366	5, /* USART 0 */
	367	5, /* USART 1 */
	368	5, /* USART 2 */
	369	0, /* Multimedia Card Interface 0 */
	370	0, /* Multimedia Card Interface 1 */
	371	3, /* CAN */
	372	6, /* Two-Wire Interface */
	373	5, /* Serial Peripheral Interface 0 */
	374	5, /* Serial Peripheral Interface 1 */
	375	4, /* Serial Synchronous Controller 0 */
	376	4, /* Serial Synchronous Controller 1 */
	377	5, /* AC97 Controller */
	378	0, /* Timer Counter 0, 1 and 2 */
	379	0, /* Pulse Width Modulation Controller */
	380	3, /* Ethernet */
	381	0, /* Advanced Encryption Standard, Triple DES*/
	382	0, /* Analog-to-Digital Converter */
	383	0, /* Image Sensor Interface */
	384	3, /* LCD Controller */
	385	0, /* DMA Controller */
	386	2, /* USB Device Port */
	387	2, /* USB Host port */
	388	0, /* Advanced Interrupt Controller (IRQ0) */
	389	0, /* Advanced Interrupt Controller (IRQ1) */
	390	};
	391
8c3583b6	392	struct at91_init_soc __initdata at91cap9_soc = {
21d08b9d	393	.map_io = at91cap9_map_io,
92100c12	394	.default_irq_priority = at91cap9_default_irq_priority,
cfa5a1fe	395	.ioremap_registers = at91cap9_ioremap_registers,
51ddec76	396	.register_clocks = at91cap9_register_clocks,
21d08b9d JCPV	397	.init = at91cap9_initialize,
21d08b9d JCPV	398	};